CN101303620A - Low power consumption multi-channel control system - Google Patents
Low power consumption multi-channel control system Download PDFInfo
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- CN101303620A CN101303620A CNA2008101157781A CN200810115778A CN101303620A CN 101303620 A CN101303620 A CN 101303620A CN A2008101157781 A CNA2008101157781 A CN A2008101157781A CN 200810115778 A CN200810115778 A CN 200810115778A CN 101303620 A CN101303620 A CN 101303620A
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Abstract
The invention discloses a multichannel control system with low power consumption, comprising functional modules, a memory control unit, memory units and a clock generator; wherein, the clock generator is respectively provided with clock signal gating units of each functional module and each memory unit, the functional module and the memory unit are respectively connected with a high frequency clock signal and a low frequency clock signal through the gating units, and either of the clock signals is selected as the current working clock according to whether the state is in memory access. By adopting the double-frequency working clock, the multichannel control system of the invention can respectively carry out gating control to the clock signals of each functional module and each memory unit and apply clear operation to idle bus data, thus dramatically lowering system power consumption.
Description
Technical field
The present invention relates to a kind of computer control system, be specifically related to a kind of multi-channel control system of low-power consumption.
Background technology
Complicated day by day along with the computer control system scale, increasing embedded device has adopted the framework of hyperchannel access memory, for example mobile phone, MP3, MP4, digital camera etc., in such system design, the requirement of low-power consumption is more and more important.
For general multichannel memory access system, under a lot of situations, all be that wherein some passages are being used, rest channels then is in idle waiting status.Fig. 1 is existing multi-channel control system structural drawing, and as shown in the figure, this system comprises functional module, memory control unit, internal storage location and clock generator.Each functional module and memory control unit adopt unified non-gated clock to carry out data sync in the system, memory control unit and each internal storage location also carry out data sync with unified non-gated clock, generally, the frequency of this clock is immutable, adopts higher frequency values in order to satisfy the system requirements needs.Therefore, in the time of even without data transmission, clock is also being worked with higher frequency always, bus is also in running order always simultaneously, when promptly not having data transmission or functional module not to obtain the internal storage access authority, also have the saltus step of data or data on the bus, in this process, consumed a lot of useless energy.
Summary of the invention
At the energy consumption problem of the bus of off working state in the existing multi-channel control system, the present invention proposes a kind of low energy consumption multi-channel control system.
For achieving the above object, multi-channel control system of the present invention comprises functional module, memory control unit, internal storage location and clock generator, and wherein, clock generator is respectively equipped with the clock signal gate unit of each functional module, each internal storage location; Functional module, internal storage location connect the doubleclocking signal of high and low frequency respectively by above-mentioned door control unit, according to whether being in the internal storage access state, select one as the work at present clock.
According to a first aspect of the invention, during above-mentioned functional module access memory, the clock signal gate unit of this functional module output high frequency clock signal; When this functional module is idle, its clock gating unit output low frequency clock signal.
Optionally, described memory control unit produces functional module internal storage access indicator signal, the clock gating unit of this functional module is selected high frequency clock signal output according to this indicator signal when internal storage access begins, select low-frequency clock signal output when visit finishes.
Preferably, described clock gating unit is closed before the high frequency clock of the corresponding function module, with the bus data zero clearing of this module.
Preferably, the low-frequency clock of described functional module is a lowest frequency value of keeping its work.
According to a second aspect of the invention, when described internal storage location is accepted the interview, the clock signal gate unit of this internal storage location output high frequency clock signal; When this internal storage location is idle, its clock gating unit output low frequency clock signal.
Optionally, described memory control unit produces the internal storage access indicator signal, the clock gating unit of described accessed internal storage location is selected high frequency clock signal output according to this indicator signal when internal storage access begins, select low-frequency clock signal output when visit finishes.
Preferably, described door control unit is closed before the high frequency clock of correspondence memory unit, with the bus data zero clearing of this internal storage location.
Preferably, the high frequency clock of described internal storage location and the same homophase frequently of the high frequency clock of the functional module that conducts interviews.
Preferably, the lowest frequency value of the low-frequency clock signal of described internal storage location for guaranteeing that these internal storage location data are not lost.
Because the present invention has adopted the two-frequency operation clock, clock signal to each functional module, each internal storage location in the system is carried out gate respectively, and to the suitable clear operation of the bus data of free time, therefore, significantly reduced the power consumption that bus in the multi-channel control system is in waiting status, reduce the power consumption that functional module, internal storage location in the system are in non-access memory state, improved system performance.
Description of drawings
Hereinafter with reference to the accompanying drawings specific embodiments of the present invention is illustrated in more detail, wherein:
Fig. 1 is a multi-channel control system structural drawing in the prior art;
Fig. 2 is a low power consumption multi-channel control system structural drawing of the present invention.
Embodiment
Fig. 2 is a low power consumption multi-channel control system structural drawing of the present invention.As shown in the figure, system provided by the present invention comprises a plurality of functional modules, memory control unit, a plurality of internal storage location and clock generator.
Clock generator provides independently clock signal to each functional module, each internal storage location respectively, and is provided with corresponding door control unit.Each door control unit all connects the input of doubleclocking signal, and is respectively the high and low frequency signal, and its frequency values is by the function decision of service module.According to the indicator signal that memory control unit provides, clock generator commands corresponding door control unit to select the one output of doubleclocking signal.
The clock of each functional module as mentioned above, can select high frequency or low-frequency clock signal as the work at present clock according to the duty of himself all from clock generator.For example, when certain functional module need inwardly deposit into capable reading and writing data, use its low-frequency clock signal, send the application that internal memory uses, reference address is set simultaneously to memory control unit as work clock; After memory control unit was accepted, this functional module used the high frequency clock signal of process gate as work clock; Simultaneously, door control unit also is connected to memory control unit with the clock signal of this functional module, when functional module and memory control unit read and write data when synchronous, also uses the high frequency clock signal of this functional module.
Memory control unit is ranked to request of access after the memory access request that obtains each functional module, gives position more preceding in the formation for the higher request of access of priority.When the memory access request of certain functional module was responded, memory control unit sent indicator signal to clock generator, and this indicator signal comprises module application internal storage access indicator signal and internal storage access indicator signal.Clock generator is commanded the clock gating unit of this functional module, the clock gating unit of correspondence memory unit then according to this signal, selects high frequency clock signal output separately respectively; When certain functional module visit finished, memory control unit sent indicator signal to clock generator once more, and clock generator then commands corresponding door control unit to send low-frequency clock signal.In addition, after visit finishes, can also be with the bus data zero clearing of this functional module and corresponding internal storage location, soon data all are set to " 0 " on its data line, address wire, the control line.
Internal storage location is within it under the commander of portion's controller, and in visit not, the slower low-frequency clock signal that uses clock generator to provide carries out self-refresh, and the frequency values of this signal can be for guaranteeing the not minimum value of obliterated data of the type internal memory; When accessing operation, clock generator passes through the high frequency clock of gate, the internal controller of internal storage location uses this clock transmission of data signals, control signal, and carries out synchronously, this high frequency clock can with the high frequency clock signal of the functional module of positive access memory with homophase frequently.
Should be noted that above description is intended to illustrate specific embodiments of the present invention, can not be interpreted as limitation of the present invention, the present invention's scope required for protection is only limited by claims.
Claims (10)
1, a kind of low power consumption multi-channel control system comprises functional module, memory control unit, internal storage location and clock generator, it is characterized in that:
Described clock generator is respectively equipped with the clock signal gate unit of each functional module, each internal storage location;
Described functional module, internal storage location connect the doubleclocking signal of high and low frequency respectively by described door control unit, according to whether being in the internal storage access state, select one as the work at present clock.
2, multi-channel control system according to claim 1 is characterized in that, during described functional module access memory, and the clock signal gate unit of this functional module output high frequency clock signal; When this functional module is idle, its clock gating unit output low frequency clock signal.
3, multi-channel control system according to claim 2, it is characterized in that, described memory control unit produces functional module internal storage access indicator signal, the clock gating unit of described this functional module is according to this indicator signal, when internal storage access begins, select high frequency clock signal output, select low-frequency clock signal output when visit finishes.
4, multi-channel control system according to claim 3 is characterized in that, described clock gating unit is closed before the high frequency clock of the corresponding function module, with the bus data zero clearing of this module.
5, multi-channel control system according to claim 2 is characterized in that, the low-frequency clock of described functional module is a lowest frequency value of keeping its work.
6, multi-channel control system according to claim 1 is characterized in that, when described internal storage location is accepted the interview, and the clock signal gate unit of this internal storage location output high frequency clock signal; When this internal storage location is idle, its clock gating unit output low frequency clock signal.
7, multi-channel control system according to claim 6, it is characterized in that, described memory control unit produces the internal storage access indicator signal, the clock gating unit of described accessed internal storage location is according to this indicator signal, when internal storage access begins, select high frequency clock signal output, select low-frequency clock signal output when visit finishes.
8, low power consumption multi-channel control system according to claim 7 is characterized in that: described door control unit is closed before the high frequency clock of correspondence memory unit, with the bus data zero clearing of this internal storage location.
9, low power consumption multi-channel control system according to claim 6 is characterized in that, the high frequency clock of the high frequency clock of described internal storage location and the functional module that conducts interviews is with the frequency homophase.
10, low power consumption multi-channel control system according to claim 6 is characterized in that: the lowest frequency value of the low-frequency clock signal of described internal storage location for guaranteeing that these internal storage location data are not lost.
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| Application Number | Priority Date | Filing Date | Title |
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| CNA2008101157781A CN101303620A (en) | 2008-06-27 | 2008-06-27 | Low power consumption multi-channel control system |
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| CNA2008101157781A CN101303620A (en) | 2008-06-27 | 2008-06-27 | Low power consumption multi-channel control system |
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Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103116384A (en) * | 2013-02-01 | 2013-05-22 | 山东华芯半导体有限公司 | System on a chip (SoC) system clock control method and SoC |
| CN103562819A (en) * | 2011-05-31 | 2014-02-05 | 英特尔公司 | Reducing power consumption of uncore circuitry of a processor |
| CN103576826A (en) * | 2012-07-19 | 2014-02-12 | 国民技术股份有限公司 | Memorizer control method and device and memorizer system |
| CN105243026A (en) * | 2014-05-30 | 2016-01-13 | 展讯通信（上海）有限公司 | Memory access control method and apparatus for terminal device |
| CN105446891A (en) * | 2014-05-29 | 2016-03-30 | 展讯通信（上海）有限公司 | Terminal device memory access method and device |
| CN105446911A (en) * | 2014-05-29 | 2016-03-30 | 展讯通信（上海）有限公司 | Terminal device memory access control method and device |
| CN108628793A (en) * | 2017-03-20 | 2018-10-09 | 华大半导体有限公司 | SPI communication circuit and method |
| CN113138202A (en) * | 2021-04-15 | 2021-07-20 | 中国科学技术大学 | Control system and control method of scanning imaging system |
| WO2022252042A1 (en) * | 2021-05-31 | 2022-12-08 | 华为技术有限公司 | Memory management apparatus and method, and electronic device |
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2008
- 2008-06-27 CN CNA2008101157781A patent/CN101303620A/en active Pending
Cited By (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9405358B2 (en) | 2011-05-31 | 2016-08-02 | Intel Corporation | Reducing power consumption of uncore circuitry of a processor |
| CN103562819A (en) * | 2011-05-31 | 2014-02-05 | 英特尔公司 | Reducing power consumption of uncore circuitry of a processor |
| CN103562819B (en) * | 2011-05-31 | 2016-10-12 | 英特尔公司 | Reduce the power consumption of the non-core circuit of processor |
| CN103576826A (en) * | 2012-07-19 | 2014-02-12 | 国民技术股份有限公司 | Memorizer control method and device and memorizer system |
| CN103576826B (en) * | 2012-07-19 | 2017-09-01 | 国民技术股份有限公司 | Memory control methods, device and accumulator system |
| CN103116384A (en) * | 2013-02-01 | 2013-05-22 | 山东华芯半导体有限公司 | System on a chip (SoC) system clock control method and SoC |
| CN105446891A (en) * | 2014-05-29 | 2016-03-30 | 展讯通信（上海）有限公司 | Terminal device memory access method and device |
| CN105446911A (en) * | 2014-05-29 | 2016-03-30 | 展讯通信（上海）有限公司 | Terminal device memory access control method and device |
| CN105446911B (en) * | 2014-05-29 | 2018-05-25 | 展讯通信（上海）有限公司 | The memory access control method and device of terminal device |
| CN105446891B (en) * | 2014-05-29 | 2018-08-21 | 展讯通信（上海）有限公司 | The memory access control method and device of terminal device |
| CN105243026A (en) * | 2014-05-30 | 2016-01-13 | 展讯通信（上海）有限公司 | Memory access control method and apparatus for terminal device |
| CN105243026B (en) * | 2014-05-30 | 2018-06-22 | 展讯通信（上海）有限公司 | The memory access control method and device of terminal device |
| CN108628793A (en) * | 2017-03-20 | 2018-10-09 | 华大半导体有限公司 | SPI communication circuit and method |
| CN108628793B (en) * | 2017-03-20 | 2021-04-02 | 华大半导体有限公司 | SPI communication circuit and method |
| CN113138202A (en) * | 2021-04-15 | 2021-07-20 | 中国科学技术大学 | Control system and control method of scanning imaging system |
| WO2022252042A1 (en) * | 2021-05-31 | 2022-12-08 | 华为技术有限公司 | Memory management apparatus and method, and electronic device |
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