CN101271874A - Semiconductor element with noise suppression function and manufacturing method thereof - Google Patents

Abstract

The invention discloses a semiconductor element with a function of suppressing noise and a manufacturing method thereof. The semiconductor element comprises a wafer, at least a first welding pad and at least a second welding pad which are arranged on the active surface of the wafer, an insulating layer which is arranged on the active surface of the wafer and exposes the first welding pad and the second welding pad, a first conducting layer which is arranged on the insulating layer and is electrically connected with the first welding pad, a dielectric layer which is arranged on the first conducting layer, a second conducting layer which is arranged on the dielectric layer and is electrically connected with the second welding pad, a plurality of periodically arranged patterning areas which are positioned on at least one of the first conducting layer and the second conducting layer, and at least one conducting circuit which is connected with at least two patterning areas. The invention can inhibit the noise generated by the semiconductor element during operation, so as to achieve better electrical performance of the semiconductor element.

Description

Semiconductor element with noise suppression function and manufacturing method thereof

technical field

The invention relates to a semiconductor element, in particular to a semiconductor element with the function of suppressing noise.

Background technique

Integrated circuits are almost ubiquitous in our daily lives. Its main application areas are not only the computer industry which has already been integrated into daily life, but also widely used in various consumer and defense electronic products and communication products, including audio, television, radar, and wireless phones. However, as the operating frequency is greatly increased and in order to produce faster product devices, a serious power disturbance is easily formed on the chip and integrated circuit, which is called simultaneous switch noise (SSN).

Generally speaking, when the element is in the switching state and the instantaneously changing current passes through the inductance in the return path, and then forms an AC voltage drop, the instantaneous switching noise caused will seriously interfere with the normal operation of the electronic device. Because in today's large-scale integrated circuits, as the number of pins increases, the packaging capacity becomes larger, and the signal switching speed increases, the instantaneous switching noise becomes more serious, and the interference to the analog signal is also greater.

The current method to solve the instantaneous switching noise is generally to add a decoupling capacitor outside the packaging component, and eliminate the noise through the decoupling capacitor. However, in actual operation, the distance between the integrated circuit and the decoupling capacitor inside the package will limit the effect of noise suppression, resulting in poor operation of the device. Therefore, how to improve the method of solving the instantaneous switching noise in the current packaging components is an important issue nowadays.

Contents of the invention

Therefore, the main objective of the present invention is to provide a semiconductor device with noise suppression function to solve the above-mentioned known problems.

The invention discloses a semiconductor element with a function of suppressing noise, which comprises a wafer, at least a first pad and at least a second pad disposed on the active surface of the wafer, disposed on the active surface of the wafer and exposed An insulating layer of the first pad and the second pad, a first conductive layer disposed on the insulating layer and electrically connected to the first pad, a dielectric layer disposed on the first conductive layer, disposed on the dielectric A second conductive layer on the layer and electrically connected to the second pad, a plurality of periodically arranged patterned regions located on at least one of the first conductive layer and the second conductive layer, and connecting at least two patterned regions at least one conductive trace.

The present invention also discloses a method for forming a semiconductor element with a noise suppression function, which includes the following steps: firstly, a wafer is provided, which has an active surface, and the wafer includes at least one first active surface located on the wafer. pads and at least one second pad. Then an insulating layer is formed on the active surface of the wafer, and a first conductive layer electrically connected to the first pad is formed. Then the first conductive layer is patterned to form a plurality of patterned regions arranged periodically, and at least one conductive line is formed to connect at least two of the patterned regions. A dielectric layer covering the first conductive layer is then formed, and then a second conductive layer electrically connected to the second pad is formed.

According to an embodiment of the present invention, another method for forming a semiconductor device with a noise suppression function is disclosed, which includes the following steps: firstly, a wafer is provided, which has an active surface, and the wafer includes an active surface located on the wafer. at least one first pad and at least one second pad. Then an insulating layer is formed on the active surface of the wafer, and a first conductive layer electrically connected to the first pad is formed. Then a dielectric layer covering the first conductive layer is formed, and a second conductive layer electrically connected to the second pad is formed. Then the second conductive layer is patterned to form a plurality of periodically arranged patterned regions and simultaneously form at least one conductive circuit connecting at least two of the patterned regions.

The present invention mainly forms a plurality of periodically arranged patterned regions at the same time when patterning the first conductive layer or the second conductive layer, and then supplies power to these patterned regions through the conductive layer, the dielectric layer and the conductive layer. The network is used to suppress the noise generated by the semiconductor device during operation, so that the semiconductor device can achieve better electrical performance.

Description of drawings

1 to 16 are schematic diagrams of manufacturing a semiconductor element with noise suppression function according to a preferred embodiment of the present invention.

17 is a top view of a patterned region formed after patterning the conductive layer in the semiconductor device of the present invention.

Explanation of reference signs

12 wafers 14 active surfaces

16 Solder Pads 18 Solder Pads

20 welding pads 22 protective layers

24 UBM layer 26 Insulation layer

28 patterned photoresist layer 30 openings

32 conductive layer 34 patterned photoresist layer

36 openings 38 dielectric layers

40 patterned photoresist layer 42 openings

44 conductive layer 46 patterned photoresist layer

48 patterned photoresist layer 50 protective layer

52 UBM layer 54 Patterned area

56 capacitance 58 conductive line

60 ground solder balls 62 power solder balls

64 signal solder balls

Detailed ways

Please refer to FIG. 1 to FIG. 16 . FIG. 1 to FIG. 16 are schematic diagrams of manufacturing a semiconductor device with noise suppression function according to a preferred embodiment of the present invention. As shown in FIG. 1 , firstly, a chip 12 is provided, which has an active surface 14 , and the chip 12 includes a plurality of bonding pads 16 , 18 , 20 disposed on the active surface 14 . Wherein, the pads 16 , 18 , and 20 can be respectively ground pads, power pads, or signal pads according to the design of the components. In this embodiment, the pad 16 is a ground pad, the pad 18 is a signal pad, and the pad 20 is a power pad. But not limited to the configuration disclosed in this embodiment, the positions and corresponding functions of the pads can be freely adjusted according to the requirements of the process or product, which should fall within the scope of the present invention. Then cover a protective layer 22 on the active surface 14 of the wafer 12 and use patterning methods such as etching to expose the pads 16, 18, 20, and finally perform steps such as deposition and etching to form an UBM layer respectively. 24 is on each pad 16, 18, 20 and covers part of the protection layer. Since these steps are well-known to those who know the art and those with ordinary knowledge, they will not be repeated here.

As shown in FIG. 2 , an insulating layer 26 is then formed on the active surface 14 and covers each UBM layer 24 and a portion of the passivation layer 22 . Wherein, the insulating layer 26 of this embodiment may include insulating materials such as benzocyclobutene (BCB), and the thickness of the insulating layer 26 is greater than 5 micrometers (μm).

Next, as shown in FIGS. 3 and 4 , a plurality of openings are formed in the insulating layer 26 by photomask, development or etching. For example, the present invention may first form a patterned photoresist layer 28 on the insulating layer 26, and then perform an etching process to remove the insulating layer 26 not covered by the patterned photoresist layer 28. , so as to form a plurality of openings 30 in the insulating layer 26 and respectively expose each UBM layer 24 .

As shown in FIG. 5 , a conductive layer 32 made of aluminum or copper is then formed in the opening 30 and on the insulating layer 26 , and the conductive layer 32 is electrically connected to the pads 16 , 18 , 20 . Wherein, the step of electrically connecting the conductive layer 32 and the pads 16, 18, 20 is to form a conductive medium (ie, the conductive layer 32) in the opening 30, and the step of forming the conductive medium can be selected from deposition, sputtering, electroplating, Various semiconductor or packaging technologies such as printing or implantation.

Then as shown in FIGS. 6 to 7, a patterned photoresist layer 34 is formed on the conductive layer 32, and an etching process is performed to remove part of the conductive layer not covered by the patterned photoresist layer 34. 32 to form a plurality of openings 36 in the conductive layer 32 and expose part of the insulating layer 26 , and then isolate the pads 16 , 18 , 20 through the openings 36 .

As shown in FIG. 8 , a dielectric layer 38 with a low dielectric constant is then formed in the opening 36 and on the conductive layer 32 . The dielectric constant of the dielectric layer may vary depending on product requirements and functional design. In this embodiment, the dielectric constant of the dielectric layer 38 is greater than 10, the thickness of the dielectric layer 38 is less than 0.3 μm, and the dielectric layer 38 is selected from Ta ₂ O ₅ .

Next, as shown in FIGS. 9 to 10 , a plurality of openings corresponding to the positions of the pads 16 , 18 , 20 are formed on the dielectric layer 38 by means of photomask, development or etching. For example, the present invention can first form a patterned photoresist layer 40 on the dielectric layer 38, and then perform an etching process to remove the dielectric layer not covered by the patterned photoresist layer 40 38 to form a plurality of openings 42 in the dielectric layer 38 and expose the conductive layer 32 .

As shown in FIG. 11 , another conductive layer 44 made of aluminum or copper is then formed in the opening 42 and covered on the dielectric layer 38, so that the conductive layer 44 is electrically connected to each pad 16, 18 through the conductive layer 32. , 20. Like the above-mentioned way of electrically connecting the conductive layer 32 and the pads 16, 18, 20, the step of electrically connecting the conductive layer 44 and the pads 16, 18, 20 is to form a conductive medium in the opening 42, and form the conductive medium The steps can be selected from various semiconductor or packaging techniques such as deposition, sputtering, electroplating, printing or implantation.

Then carry out a patterning process to conductive layer 44, for example as shown in Figure 12, first form a patterned photoresist layer 46 on conductive layer 44, then as shown in Figure 13, carry out an etching process, to remove Conductive layer 44 covered by patterned photoresist layer 46 .

Then, as shown in FIG. 14, another patterning process is performed, for example, a patterned photoresist layer 48 is first formed on the conductive layer 44, and then as shown in FIG. 15, another etching process is performed to remove the remaining Conductive layer 44 covered by patterned photoresist layer 48 . In this embodiment, the second pattern transfer process will form the conductive layer 44 into a plurality of patterned regions arranged periodically and at the same time form at least one conductive line connecting at least two patterned regions.

It is worth noting that the present invention mainly forms a plurality of periodically arranged patterned regions at the same time when patterning the conductive layer 44, and then forms the patterned regions through the conductive layer 44, the dielectric layer 38 and the conductive layer 32. The power supply network is used to suppress the noise generated by the semiconductor element during operation, so that the semiconductor element can achieve better electrical performance.

In addition, in this embodiment, the conductive layer 44 is patterned and the patterning process is performed twice to form periodically arranged patterned regions. But not limited to the above method, the two steps of patterning the conductive layer 44 and forming the periodically arranged patterned regions can be combined into one step according to the requirements of the actual process. For example, the present invention can form a plurality of periodically arranged patterned regions while utilizing the patterned photoresist layer 46 to pattern the conductive layer 44 in FIG. 12 , which are all within the scope of the present invention .

In addition, this embodiment takes the patterned conductive layer 44 as an example, but the step of forming the periodically arranged patterned regions can be achieved when patterning the conductive layer 32, and is not limited to the patterned conductive layer 44. That is, the present invention can form a plurality of periodically arranged patterned regions and at least one conductive line to connect at least two patterned regions, which all belong to the scope of the present invention.

Next, as shown in FIG. 16 , another protection layer 50 may be formed on the patterned conductive layer 44 and expose the conductive layer 44 connecting the pads 16 , 18 , 20 . Then, a plurality of UBM layers 52 are formed on the conductive layer 44 exposed by the protective layer 50, and a plurality of solder balls (not shown) can be formed on the UBM layers 52 according to product requirements to complete the process. Fabrication of the semiconductor element of the present invention.

Please refer to FIG. 16 again, which shows a schematic structural diagram of a semiconductor device according to an embodiment of the present invention. As shown in the figure, the semiconductor device of the present invention mainly includes a wafer 12, a plurality of bonding pads 16, 18, 20 arranged on the active surface 14 of the wafer 12, arranged on the active surface 14 of the wafer 12 and exposed A protective layer 22 for each solder pad 16, 18, 20, a plurality of UBM layers 24 disposed on the solder pads 16, 18, 20 and the protective layer 22, covering the protective layer 22 and the UBM layer 24 and expose an insulating layer 26 of each UBM layer 24, a conductive layer 32 disposed on the insulating layer 26 and electrically connected to the pads 16, 18, 20, and a dielectric layer covering the conductive layer 32 The electrical layer 38, a conductive layer 44 disposed on the dielectric layer 38 to electrically connect the pads 16, 18, 20, another protective layer 50 covering the conductive layer 44, and a plurality of bumps disposed on the protective layer 50 Underblock metal layer 52 . Wherein, the conductive layer 44 simultaneously forms a plurality of periodically arranged patterned regions and at least one conductive circuit connecting at least two patterned regions.

Please refer to FIG. 17 at the same time. FIG. 17 is a top view of the patterned region formed after patterning the conductive layer in the semiconductor device of the present invention. As shown in the figure, the present invention can simultaneously form a plurality of periodically arranged patterned regions 54 when patterning the conductive layer 44 or the conductive layer 32 . Among them, in the present invention, only one of the two conductive layers 44, 32 can be patterned to form a patterned area 54 arranged periodically, or both conductive layers 44, 32 can be patterned at the same time, all of which are covered by the present invention scope. In addition, the patterned conductive layer 44 , the dielectric layer 38 and the conductive layer 32 form a plurality of capacitors 56 , and at least one capacitor 56 is located in the above-mentioned patterned area 54 . In this embodiment, each patterned area 54 is electrically connected through a plurality of conductive lines 58, and these conductive lines form a plurality of inductors, and one patterned area 54 is composed of four capacitors 56, but it is not limited thereto. This structure constitutes the entire power supply network to suppress noise. As shown in the figure, a plurality of corresponding solder balls are formed on the capacitor 56, and each solder ball becomes a ground ball (ground ball) 60, a power ball (powerball) 62 or a signal solder ball according to the characteristics of the solder pad. ball (signal ball)64. In addition, the number and configuration of the solder balls disposed on the patterned area 54 can be freely adjusted according to the requirements of the product, and are not limited to those shown in the figure.

The above descriptions are only preferred embodiments of the present invention, and all equivalent changes and modifications made according to the claims of the present invention shall fall within the scope of the present invention.

Claims (25)

1. A semiconductor element with a noise suppression function, comprising: a wafer having an active surface; at least one first bonding pad disposed on the active surface of the wafer; at least one second bonding pad disposed on the active surface of the wafer; an insulating layer located on the active surface and exposing the first pad and the second pad; a first conductive layer disposed on the insulating layer and electrically connected to the first pad; a dielectric layer disposed on the first conductive layer; a second conductive layer disposed on the dielectric layer and electrically connected to the second pad; a plurality of periodically arranged patterned regions located on at least one of the first conductive layer and the second conductive layer; and At least one conductive line connects at least two patterned regions. 2. The semiconductor device according to claim 1, wherein the first pad is a ground pad, the second pad is a power pad, or the first pad is a power pad, and the second pad is ground pad. 3. The semiconductor device as claimed in claim 1, further comprising a first protection layer located between the wafer and the insulating layer. 4. The semiconductor device as claimed in claim 1, further comprising a first UBM layer disposed on at least one of the first pad and the second pad. 5. The semiconductor device as claimed in claim 1, further comprising a second protection layer covering the second conductive layer. 6. The semiconductor device according to claim 5 , further comprising a plurality of openings passing through the second protective layer, the second conductive layer, the dielectric layer, the first conductive layer and the insulating layer, and the openings Located above the first pad and the second pad. 7. The semiconductor device as claimed in claim 5, further comprising a second UBM layer located above the opening and electrically connected to the first pads and the second pads. 8. The semiconductor device as claimed in claim 5, further comprising a conductive medium located in the opening and electrically connected to the first bonding pad and the second bonding pad. 9. The semiconductor device as claimed in claim 1, wherein the wafer further comprises a plurality of third bonding pads, which are signal bonding pads. 10. The semiconductor device as claimed in claim 1, wherein the first conductive layer, the dielectric layer and the second conductive layer form a plurality of capacitors, at least one of which is located in the patterned regions. 11. The semiconductor device as claimed in claim 1, wherein the conductive trace is an inductor. 12. The semiconductor device as claimed in claim 1, wherein the first conductive layer, the dielectric layer and the second conductive layer form a plurality of capacitors, at least one of the capacitors is located in the patterned regions, the conductive circuit is an inductor, The inductor is electrically connected to the capacitor. 13. A method of manufacturing a semiconductor element having a noise suppression function, comprising: providing a wafer having an active surface and comprising at least one first bonding pad and at least one second bonding pad located on the active surface of the wafer; forming an insulating layer on the active surface of the wafer; forming a first conductive layer electrically connected to the first pad; patterning the first conductive layer to form a plurality of periodically arranged patterned regions, and forming at least one conductive line connecting at least two of the patterned regions; forming a dielectric layer overlying the first conductive layer; and A second conductive layer is formed to be electrically connected to the second pad. 14. A method of manufacturing a semiconductor element having a noise suppression function, comprising: providing a wafer having an active surface and comprising at least one first bonding pad and at least one second bonding pad located on the active surface of the wafer; forming an insulating layer on the active surface of the wafer; forming a first conductive layer electrically connected to the first pad; forming a dielectric layer covering the first conductive layer; forming a second conductive layer electrically connected to the second pad; and The second conductive layer is patterned to form a plurality of patterned regions arranged periodically and simultaneously at least one conductive circuit is formed to connect at least two of the patterned regions. 15. The method for manufacturing a semiconductor device according to claim 13 or claim 14, further comprising forming a plurality of first openings on the insulating layer by means of photomask, developing, and etching. 16. The method of manufacturing a semiconductor element as claimed in claim 14 or claim 14, wherein the step of electrically connecting the first conductive layer and the first pad is to form a first conductive medium in the first openings, The method of forming the first conductive medium in the openings is selected from electroplating, printing or injection. 17. The method for manufacturing a semiconductor device according to claim 13 or claim 14, further comprising forming a plurality of second openings on the dielectric layer by means of photomask, development, and etching. 18. The manufacturing method of a semiconductor device as claimed in claim 17, wherein the step of electrically connecting the second conductive layer and the second pad is to form a second conductive medium in the second openings, wherein in the second openings The method of forming the second conductive medium in the opening is selected from electroplating, printing or injection. 19. The method for manufacturing a semiconductor element as claimed in claim 13 or claim 14, further comprising forming a first protective layer, the first protective layer covers the active surface of the wafer and exposes the first pad and the the second pad. 20. The method of manufacturing a semiconductor device according to claim 19, further comprising forming a first UBM layer on the first bonding pad and the second bonding pad, the first UBM layer covering part of the first bonding pad. The protective layer. 21. The manufacturing method of a semiconductor device as claimed in claim 13 or claim 14, further comprising forming a second protection layer on the second conductive layer, and exposing the first pad on the second protection layer and a plurality of third openings above the second pad. 22. The method of manufacturing a semiconductor device as claimed in claim 21, further comprising forming a second UBM layer on the third opening. 23. The method for manufacturing a semiconductor device as claimed in claim 13 or claim 14, wherein the steps of patterning the first conductive layer or patterning the second conductive layer are by means of photomask, development, and etching. 24. The method for manufacturing a semiconductor device as claimed in claim 13, further comprising patterning the second conductive layer, wherein the step of patterning the first conductive layer is by photomask, development, and etching. 25. The method for manufacturing a semiconductor device as claimed in claim 14, further comprising patterning the first conductive layer, wherein the step of patterning the first conductive layer is by means of photomask, development, and etching.

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