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CN101267717B - Multilayer build-up wiring board - Google Patents

Multilayer build-up wiring board Download PDF

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Publication number
CN101267717B
CN101267717B CN2008100810380A CN200810081038A CN101267717B CN 101267717 B CN101267717 B CN 101267717B CN 2008100810380 A CN2008100810380 A CN 2008100810380A CN 200810081038 A CN200810081038 A CN 200810081038A CN 101267717 B CN101267717 B CN 101267717B
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China
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hole
conductor
mentioned
layer
via hole
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CN2008100810380A
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CN101267717A (en
Inventor
广濑直宏
袁本镇
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Ibiden Co Ltd
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Ibiden Co Ltd
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Priority claimed from JP32453598A external-priority patent/JP2000133941A/en
Priority claimed from JP36296198A external-priority patent/JP2000188447A/en
Priority claimed from JP00031599A external-priority patent/JP4127440B2/en
Application filed by Ibiden Co Ltd filed Critical Ibiden Co Ltd
Publication of CN101267717A publication Critical patent/CN101267717A/en
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Publication of CN101267717B publication Critical patent/CN101267717B/en
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  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)

Abstract

The invention relates to a multilayer build-up wiring board. Mesh holes 35a and 59a of upper solid layers 35 and upper solid layers 59 are formed to overlie on one another, so that the insulating properties of interlayer resin insulating layers 50 are not lowered. Here, the diameter of each mesh hole is preferably 75 to 300 mu m. The reason is as follows. If the diameter of the mesh hole is less than 75 mu m, it is difficult to overlay the upper and lower mesh holes on one another. If the diameter exceeds 300 mu m, the insulating properties of the interlayer resin insulating layers deteriorate. In addition, the distance between the mesh holes is preferably 100 to 2000 mu m. The reason is as follows. If the distance is less than 100 mu m, the solid layer cannot function. If the distance exceeds 2000 mu m, the deterioration of the insulating properties of the interlayer resin insulating film occurs.

Description

Multilayer build-up wiring board
The application be application number to be 99811085.X (PCT/JP99/04895), denomination of invention be the dividing an application of female case of " multilayer build-up wiring board ", the applying date of this mother's case is on September 8th, 1998.
Technical field
The present invention relates to a kind of multilayer build-up wiring board, this circuit board is made of the superimposed line layer that is formed at core rod (core) substrate two sides, this superimposed circuit layer is then formed by interlayer resin insulating layers and the mutual lamination of conductor layer, and be particularly related to a kind of have can be used as power supply with conductor layer (bus plane) or conductor layer for grounding (ground plane) and the multilayer build-up wiring board of the flatness layer that forms.
Prior art
In the multilayer build-up wiring board that constitutes utilizing interlayer resin insulating layers to insulate respectively, be that one deck conductor circuit is partly used as ground plane or bus plane, to reach the purpose that reduces noise etc. by a plurality of conductor layers (conductor circuit).As in multilayer build-up wiring board, then shown in Fig. 9 (C), be in the majority with the situation that the flatness layer 559 of conductor layer (bus plane) is formed on the mesh pattern with netted hole 559a will constitute conductor layer for grounding (ground plane) or power supply.Herein, netted hole 559a sets up, system is because flatness layer 559 is by being formed with the low copper of resin connectivity, and is provided in the interlayer resin insulating layers (not shown) on flatness layer upper strata and the connectivity that is provided between the resin molding core substrate (not shown) of lower floor can be by means of at this netted hole 559a place interlayer resin insulating layers directly being contacted with core base and improving.In addition, by this netted hole 559a, by also being easier to disperse at the formed gases such as moisture that interlayer resin insulating layers absorbed.
About the formation position of this netted hole 559a, existing various schemes are suggested.For example, open the technology that is disclosed in flat 1-163634 number the spy, system is shown in Fig. 9 (B), by being staggered in the position of the netted hole 559a of the through hole 559a of upside flatness layer 559 and downside flatness layer 559B, make that the netted hole 559a of the through hole 559a of upside flatness layer 559 and downside flatness layer 559B is not overlapping, thereby just can not form depression on the surface of substrate.
The interlayer resin insulating layers that is used between spaced conductors layer and the conductor layer must have high-insulation.The inventor has promptly found the insulating properties of interlayer resin insulating layers and has been formed between the relative position of the through hole of flatness layer up and down to have correlation.Then, while the position of adjusting through hole, measure the insulating properties of its interlayer resin insulating layers of multilayer build-up wiring board that forms, if the result obtains the words that stagger between the netted hole 559a with the through hole 559a of upside flatness layer 559 and the downside flatness layer 559B insulating properties of the interlayer resin insulating layers conclusion that can descend significantly then shown in Fig. 9 (B).
The present invention can the object of the present invention is to provide a kind of multilayer build-up wiring board in order to solve the above problems, and the situation that this circuit board has flatness layer and an interlayer resin insulating layers insulation degradation seldom.
On the other hand, be suggested about the existing various schemes in the formation position of this netted hole.For example, open the technology that is disclosed in flat 10-200271 number the spy, as shown in figure 23, by on flatness layer 559, not setting netted hole being arranged in the zone in opposite directions that figure C place is used for installing the zone of chip, and only set netted hole 559a in the outside in chip installation area territory, so that this place, chip installation area territory can be not uneven, thereby reach the purpose in the chip installation area territory that can be formed flatly multilayer board.
As above-mentioned, because the gas of interlayer resin insulating layers can be dispersed by netted hole, so if as above-mentioned technology, do not wear netted hole in the chip installation area territory, then moisture just can't be dispersed out from the interlayer resin insulating layers under this chip installation area territory, in addition, interlayer resin insulating layers can be peeled off simultaneously, and then the insulation impedance in the interlayer resin insulating layers of this part will reduce.
The present invention can the object of the present invention is to provide a kind of multilayer build-up wiring board in order to solve the above problems, and the situation of this circuit board interlayer resin insulating layers insulation degradation seldom simultaneously can be formed flatly the chip installation area territory.
On the other hand, by the multilayer build-up wiring board that base plate for packaging constituted that is used for installing IC chip etc., tie up on the core base that forms through hole resin insulating barrier and conductor layer between the lamination of mutual stratum, set the IC chip by face thereon again and connect with projection, the projection that sets in order to the connection motherboard in following side and form.Then, the connection between last lower conductor layer is to be undertaken by forming via hole, and the via hole on core base upper strata then is to be connected by through hole with the via hole of lower floor.
But, because via hole is by setting up non-through hole to form on interlayer resin insulating layers, so the via hole number that can form on a certain size multilayer build-up wiring board has restriction physically, this is one of reason that hinders densification in the multilayer build-up wiring board.
The present invention can the object of the present invention is to provide a kind of multilayer build-up wiring board in order to solve the above problems, and this circuit board can obtain the densification of circuit.
On the other hand; about using the technology of the multilayer build-up wiring board that resin substrate makes; can give an example as in the fair 4-55555 communique of spy disclosed method; this method ties up to utilizes epoxy acrylate to form interlayer resin insulating layers on the glass epoxy resin substrate that forms circuit; then use the method for photoetching that the via hole perforate is set; to electroplating film be set behind the surface coarsening again, and form conductor circuit and via hole by electroplating.
In the past, utilized said method to form after conductor circuit and the via hole, utilized electroless plating to form to be coated on the roughened layer that constitutes by the Cu-Ni-P alloy on the above-mentioned conductor circuit etc., to form interlayer resin insulating layers thereon.
But, if the printed circuit board (PCB) of manufacturing is implemented the words of thermal cycling test etc., then some part wherein can be because by top conductor circuit that metal constituted and by producing thermal expansion difference between the interlayer resin insulating layers that resin constituted, cause reaching above it and lower floor's conductor circuit, thereby the out of use problem of so-called multilayer build-up wiring board takes place by the crack extension that is positioned at interlayer resin insulating layers that the bight produced of top conductor circuit.
The cause of the problems referred to above is inferred system because the bight of top conductor circuit is easy to be near tip shape, so can expand because of the variations in temperature of top conductor circuit, shrink, makes stress concentrate on the bight, and the result has just caused the generation in crack.
The present invention can be in order to address the above problem, the object of the present invention is to provide a kind of circuit substrate and multilayer build-up wiring board, this circuit substrate and multilayer build-up wiring board can prevent the stress concentration phenomenon that the variations in temperature because of formed conductor circuit bight causes, and can prevent to produce the crack at resin insulating barrier.
Disclosure of an invention
In order to reach above-mentioned purpose, can use the multilayer build-up wiring board in the claim 1, this circuit board system is made of interlayer resin insulating layers and the mutual lamination of conductor layer, it is characterized in that: form a plurality of flatness layers (they play a part power supply with conductor layer and conductor layer for grounding) with as above-mentioned conductor layer, and on above-mentioned a plurality of flatness layers, form netted hole in a part of at least overlapping mode.
In addition, also can use the multilayer build-up wiring board in the claim 2, this circuit board is that the superimposed line layer that will be formed by interlayer resin insulating layers and the mutual lamination of conductor layer is formed at that institute constitutes on the two sides of core base, it is characterized in that: will on the one side at least of above-mentioned core base, form flatness layer (they play power supply conductor layer and conductor layer for grounding) by formed conductor layer, simultaneously also will between above-mentioned interlayer resin insulating layers, form flatness layer by one deck at least of formed conductor layer, and on the flatness layer of above-mentioned core base and the flatness layer between above-mentioned interlayer resin insulating layers, form netted hole in a part of at least overlapping mode.
Claim 3 is a multilayer build-up wiring board as claimed in claim 1 or 2, it is characterized by: the diameter system of above-mentioned netted hole forms with 75～300 μ m, and the distance system between each netted hole forms with 100～1500 μ m.
In claim 1, because the netted hole of flatness layer system forms in a part of at least overlapping mode up and down, so the insulating properties of interlayer resin insulating layers can not reduce significantly.
Herein, the diameter of netted hole system thinks that 75～300 μ m are preferable.This be because if diameter less than 75 μ m, up and down the overlapping meeting of netted hole become the difficulty; On the other hand, if surpass 300 μ m, just do not have and be used as the function of power supply with conductor layer (bus plane) or conductor layer for grounding (ground plane).In addition, the distance system between each netted hole thinks that 100～1500 μ m are preferable.This be because if the distance less than 100 μ m, the area of flatness layer can diminish, and can't obtain due function thereby become; On the other hand, if surpass 1500 μ m, then the insulation degradation degree of interlayer resin insulating layers can significantly become big.
In the present invention, to use electroless plating preferable as above-mentioned interlayer resin insulating layers with bonding agent.This electroless plating bonding agent is the heat-resistant resin particle of tool solubility in acid after cure process or oxidant, and is simultaneously the most suitable can be scattered in the unhardened heat-resistant resin that is slightly solubility in acid or oxidant the person.
By handling, the dissolving of heat-resistant resin particle can be removed, and form alligatoring face by adhesion promoting layer (anchor) formation of striated on the surface with acid and oxidant.
Use in the bonding agent, at above-mentioned electroless plating particularly with regard to regard to the above-mentioned heat-resistant resin particle of cure process, so that preferable with having following condition person:
(1) the heat-resistant resin powder of average grain diameter below 10 μ m;
(2) make the agglutination particle of the heat-resistant resin powder aggegation of average grain diameter below 2 μ m;
(3) average grain diameter is the heat-resistant resin powder of 2～10 μ m and the mixture of the heat-resistant resin powder of average grain diameter below 2 μ m;
(4) average grain diameter be the heat-resistant resin powder surface of 2～10 μ m make be attached with average grain diameter below 2 μ m the heat-resistant resin powder or inorganic powder at least a kind of particle-like that composition forms;
(5) average grain diameter is that the heat-resistant resin powder of 0.1～0.8 μ m and average grain diameter surpass 0.8 μ m but less than the mixture of the heat-resistant resin powder of 2 μ m;
(6) average grain diameter is the heat-resistant resin powder of 0.1～1.0 μ m.
This is because they can form more complicated adhesion promoting layer.
The degree of depth of alligatoring face, preferable with Rmax=0.01～20 μ m, because can guarantee close adherence.Particularly in semi-additive process (semi-additive process), preferable with 0.1～5 μ m.Therefore, close adherence can be guaranteed on the one hand, the electroless plating film can be removed on the one hand.
With regard in above-mentioned acid or the oxidant for regard to the heat-resistant resin of slightly solubility, think that " resin complexes that thermosetting resin and thermoplastic resin constitute " or " resin complexes that photoresist and thermoplastic resin constitute " is preferable.The former thermal endurance is higher, and the latter can use photoetching to form the via hole opening.
With above-mentioned thermosetting resin, can use epoxy resin, phenolic resin, poly-imide resin etc.In addition, when implementing sensitization, make thermmohardening base and methacrylic acid or acrylic acid etc. carry out the propylene reaction.Wherein especially with the acrylate of epoxy resin for the most suitable.
With epoxy resin, can use phenol aldehyde type epoxy resins such as phenol phenolic resins (phenol novalak) type, cresols phenolic aldehyde (cresol novalak) type, and the alicyclic epoxy resin of bicyclopentadiene (dicyclopentadiene) modification etc.
With thermoplastic resin, can use polyether sulfone (polyethersulfone) (PES), polysulfones (polysulfone) (PSF), polyhenylene sulfone (polyphenylenesulfone) (PPS), polyhenylene sulfuration thing (polyphenylenesulfide) (PPES), polyphenylene oxide (polyphenylether) (PPE) and polyimide (polyetherimide) (PI) etc.
Thermosetting resin (photoresist) is preferable with thermosetting resin (photoresist)/thermoplastic resin=95/5～50/50 with the mixed proportion system of thermoplastic resin.So, can not undermine under the stable on heating situation, guarantee the high tenacity degree.
The mixed weight ratio of above-mentioned heat-resistant resin particle, for the solids content of heat-resistant resin base material, preferable with 5～50 weight %, particularly 10～40 weight %.
The heat-resistant resin particle can use ammonia resin (melamine (melamine) resin, urea resin, guanamine (guanamine) resin) and epoxy resin etc.
In addition, bonding agent also can constitute by forming 2 layers of different institute.
In addition; to be additional to the scolding tin protective film on multilayer board surface; can use resin miscellaneous, for example using the acrylate etc. of acrylate, phenolic resin type epoxy resin and the phenolic resin type epoxy resin of bisphenol-A (bisphenol A) type epoxy resin, bisphenol A type epoxy resin can be the resin that curing agent or imidazoles (imidazole) curing agent etc. harden with amine.
On the other hand, above-mentioned scolding tin protective film is owing to being constituted with the resin with firm skeleton, so can produce the phenomenon of peeling off.Therefore, can utilize the mode that reinforced layer is set to prevent peeling off of scolding tin protective film.
Herein, with regard to the acrylate of above-mentioned phenolic resin type epoxy resin, can use to allow epoxy resin that epoxy propyl ether (glycidyl ether) and the acrylic or methacrylic acid etc. of phenol phenolic resins or cresol novolac resin react or the like.
Above-mentioned imidazole hardeners is being that aqueous person is preferable at 25 ℃.If because aqueous words just can be mixed by homogeneous.
With the aqueous imidazole hardeners of above-mentioned what is called, can use 1 benzyl 2 methyl imidazole (1-benzyl-2-methylimidazole) (ProductName: 1B2MZ), 1-cyano ethyl-2-ethyl-4-methylimidazole (1-cyanoethyl-2-ethyl-4-methylimidazole) (ProductName: 2E4MZ-CN) and 4-methyl-2-ethyl imidazol(e) (4-methyl-2-ethyl imidazole) (ProductName: 2E4MZ).
The addition of above-mentioned imidazole hardeners, for the total solids content of above-mentioned scolding tin diaphragm constituent, preferable with 1～10 weight %.If being addition, its reason in above-mentioned scope, is easier to the homogeneous mixing.
Constituent before the sclerosis of above-mentioned scolding tin diaphragm is so that the solvent that spent glycol ether (glycol ether) is is as preferred solvents.
Use the scolding tin protective film of above-mentioned constituent can not produce free acid, surface, brazing district (pad) can oxidation yet.In addition, the harmfulness to human body is also very little.
With above-mentioned glycol ether series solvent, system uses as following structural form, particularly with use be selected from diethyleneglycol dimethyl ether (diethyleneglycol dimethyl ether) (DMDG) and trietbhlene glycol dimethyl ether (triethyleneglycol dimethyl ether) (DMTG) at least a kind of composition person preferable.Therefore, the solvent of above-mentioned grade is heated by means of 30～50 ℃ of degree, can make the benzophenone (benzophenone) and the Michler's keton (Michler ' sketohe) dissolving fully of reaction initiator.
CH 3O-(CH 2CH 2O)n-CH 3(n＝1～5)
This glycol ether series solvent is with respect to the total weight of scolding tin diaphragm constituent and be that 10～70 weight % are preferable.
As above-mentioned illustrated scolding tin diaphragm constituent in; also can add other materials, for example various defoamers or smooth dose, in order to improve thermal endurance or alkali resistance and to give flexual thermosetting resin and in order to improve as the photo-sensitive monomer of resolution etc.
For example with regard to smooth dose, with preferable by acrylate polymer institute constitutor.In addition, initiator is then preferable with the イ Le ガ キ ユ ア I 907 that チ バ ガ イ ギ one makes, and emulsion is then preferable with the DETX-S that Japanese chemical drug is made.
Further, in scolding tin diaphragm constituent, also can add pigment and pigment.Therefore can hide circuit pattern.It is preferable that this pigment is eliminated cyanines green (Phthalocyanine Green) with use.
Above-mentioned thermosetting resin with as adding ingredient can use bisphenol-type epoxy resin.Comprise bisphenol A type epoxy resin and bisphenol f type epoxy resin in this bisphenol-type epoxy resin, to use the former preferable, (when paying attention to coating) is then to use the latter preferable under requiring the situation of lowering viscousity under the alkali-proof situation of emphasis.
With the above-mentioned photo-sensitive monomer as the interpolation composition, can use the multivalence propylene is monomer.Using the multivalence propylene is that monomer can make resolution upwards promote.For example, can use the DPE-6A of Japanese chemical drug manufacturing and the R-604 of common prosperity society chemistry manufacturing is monomer as the multivalence propylene.
Again, above-mentioned scolding tin diaphragm constituent, to be that 0.5～10Pas is preferable 25 ℃ the time, 1～10Pas is better.Therefore, available cylinder spreader carries out the low viscosity coating.
In order to achieve the above object, can use the multilayer build-up wiring board in the claim 4, this circuit board system is formed by interlayer resin insulating layers and the mutual lamination of conductor layer, and has a chip installation area territory that is used for installing chip in the superiors, and be to utilize via hole to be connected between conductor layer, it is characterized in that: on as the formed flatness layer of above-mentioned conductor layer, set up netted hole, simultaneously at least one part of the netted hole in zone in opposite directions, setting and be used for connecting through hole or the island (land) of via hole and the welding zone of via hole that is positioned at this hole across said chip installation region and interlayer resin insulating layers.
In the invention of claim 4, owing to tie up in the flatness layer in forming netted hole on the zone in opposite directions across the chip installation area territory of the superiors and interlayer resin insulating layers, the welding zone that will be used for simultaneously connecting through hole or via hole island and via hole in this netted hole in the hole of at least one part leaves mode at interval with the edge with netted hole and is provided with, so interlayer resin insulating layers that is equipped on the flatness layer upper strata and the interlayer resin insulating layers that is equipped on lower floor (or resin molding core substrate) are directly contacted, thereby can improve cementability.In addition, owing to can exhale by the netted hole of being set up in the periphery, island of above-mentioned grade by the formed gases such as moisture that interlayer resin insulating layers absorbed, so can improve the insulating properties of interlayer resin insulating layers.Further, the netted hole in this chip installation area territory is interior to form island and via hole owing to tie up to, thus can be not uneven, thereby can make this chip installation area territory planarization.
In addition, claim 5 is relevant for a kind of multilayer build-up wiring board, this circuit board system is formed by interlayer resin insulating layers and the mutual lamination of conductor layer, and has a chip installation area territory that is used for installing chip in the superiors, and be to utilize via hole to be connected between conductor layer, it is characterized in that: on as the formed flatness layer of above-mentioned conductor layer, set up netted hole, simultaneously at least one part of the netted hole in zone in opposite directions, in this hole, setting the via hole island across said chip installation region and interlayer resin insulating layers.
In the invention of claim 5, owing to tie up in the flatness layer in forming netted hole on the zone in opposite directions across the chip installation area territory of the superiors and interlayer resin insulating layers, in the hole of at least one part in this netted hole mode at interval being left with the edge with netted hole in the via hole island simultaneously is provided with, so can interlayer resin insulating layers that be equipped on the flatness layer upper strata and the interlayer resin insulating layers that is equipped on lower floor (or resin molding core substrate) directly be contacted by means of the netted hole of setting up in the periphery on this via hole island, thereby can improve cementability.In addition, owing to can exhale by the netted hole of setting up in the periphery on this via hole island by the formed gases such as moisture that interlayer resin insulating layers absorbed, so can improve the insulating properties of interlayer resin insulating layers.Further, the netted hole in this chip installation area territory is interior to form via hole owing to tie up to, thus can be not uneven, thereby can make this chip installation area territory planarization.
Claim 6 is relevant for a kind of multilayer build-up wiring board, this circuit board system is formed by interlayer resin insulating layers and the mutual lamination of conductor layer, and has a chip installation area territory that is used for installing chip in the superiors, it is characterized in that: on as the formed flatness layer of above-mentioned conductor layer, set up netted hole, simultaneously at least one part of the netted hole in zone in opposite directions, in this hole, setting β shape conductor layer across said chip installation region and interlayer resin insulating layers.
In the invention of claim 6, owing to tie up in the flatness layer in forming netted hole on the zone in opposite directions across the chip installation area territory of the superiors and interlayer resin insulating layers, in the hole of at least one part in this netted hole β shape conductor layer being left mode at interval with the edge with netted hole simultaneously is provided with, so can interlayer resin insulating layers that be equipped on the flatness layer upper strata and the interlayer resin insulating layers that is equipped on lower floor (or resin molding core substrate) directly be contacted by means of the netted hole of setting up in the periphery of this β shape conductor layer, thereby can improve cementability.In addition, owing to can exhale by the netted hole of setting up in the periphery of this β shape conductor layer by the formed gases such as moisture that interlayer resin insulating layers absorbed, so can improve the insulating properties of interlayer resin insulating layers.Further, owing to tie up to the interior β of formation of the netted hole shape conductor layer in this chip installation area territory, thus can be not uneven, thereby can make this chip installation area territory planarization.
Again, claim 7 is relevant for a kind of multilayer build-up wiring board, this circuit board is to have on the substrate of through hole interlayer resin insulating layers and the mutual lamination of conductor layer and constitute, and has a chip installation area territory that is used for installing chip in the superiors, it is characterized in that: on as the formed flatness layer of above-mentioned conductor layer, set up netted hole, simultaneously at least one part of the netted hole in zone in opposite directions, in this hole, setting the through hole island across this chip installation area territory and interlayer resin insulating layers.
In the invention of claim 7, owing to tie up in the flatness layer in forming netted hole on the zone in opposite directions across the chip installation area territory of the superiors and interlayer resin insulating layers, in the hole of at least one part in this netted hole mode at interval being left with the edge with netted hole in the through hole island simultaneously is provided with, so can interlayer resin insulating layers that be equipped on the flatness layer upper strata and the interlayer resin insulating layers that is equipped on lower floor (or resin molding core substrate) directly be contacted by means of the netted hole of setting up in the periphery on this island, thereby can improve cementability.In addition, owing to can exhale by the netted hole of setting up in the periphery on this island by the formed gases such as moisture that interlayer resin insulating layers absorbed, so can improve the insulating properties of interlayer resin insulating layers.Further, the netted hole in this chip installation area territory is interior to form the island owing to tie up to, thus can be not uneven, thereby can make this chip installation area territory planarization.
In addition, in the present invention, above-mentioned smooth series of strata with the chip installation area territory across the interlayer resin insulating layers more than at least 1 layer and preferable in opposite directions.
In order to solve the above problems, can use the multilayer build-up wiring board in the claim 8, this circuit board system is with interlayer resin insulating layers and conductor layer lamination alternatively, and will be that the multilayer line layer that is connected with via hole is formed on the core base and is constituted between each conductor layer, it is characterized in that: above-mentioned 1 via hole system utilizes a plurality of line conductor to form.
In the multilayer build-up wiring board of claim 8, because 1 via hole system utilizes a plurality of line conductor to constitute, therefore the line conductor that is several times as much as via hole is passed through on interlayer resin insulating layers, so can seek the densification of its circuit of multilayer build-up wiring board.
In addition, claim 9 is relevant for a kind of multilayer build-up wiring board, this circuit board system is with interlayer resin insulating layers and conductor layer lamination alternatively, and will be that the multilayer line layer that is connected with via hole is formed on the core base and is constituted between each conductor layer, it is characterized in that: above-mentioned 1 via hole system utilizes 2 line conductor to form.
In the multilayer build-up wiring board of claim 9, because 1 via hole system utilizes 2 line conductor to constitute, therefore 2 times of line conductors to via hole are passed through on interlayer resin insulating layers, so can seek the densification of its circuit of multilayer build-up wiring board.
In addition, claim 10 is relevant for a kind of multilayer build-up wiring board, this circuit board system is with interlayer resin insulating layers and conductor layer lamination alternatively, and will be that the multilayer line layer that is connected with via hole is formed on the core base between each conductor layer, above-mentioned conductor series of strata are done electric being connected by means of formed through hole on core base with the conductor layer of this core base the inside side, it is characterized in that:
On 1 through hole of above-mentioned core base, set a plurality of line conductors; And on directly over the through hole that sets above-mentioned a plurality of line conductors, set the via hole that a plurality of line conductor constituted that is connected with above-mentioned each line conductor by respectively.
In the multilayer build-up wiring board of claim 10, because on 1 through hole, set a plurality of line conductors, so the line conductor that is several times as much as through hole is passed through on core base, in addition, because the via hole system that is equipped on directly over this through hole is made of a plurality of line conductor, so the line conductor that is several times as much as via hole is passed through on interlayer resin insulating layers.Therefore, can seek the densification of its circuit of multilayer build-up wiring board.Further, because directly over through hole, be formed with via hole, so line length shortens thereby high speed that can corresponding multilayer build-up wiring board.
In addition, when on the single face of core base, setting up superimposed line layer, also because on 1 through hole, be equipped with a plurality of line conductors, thus the line conductor that is several times as much as through hole is passed through on core base, and overlapping layers is set up the wiring degree of freedom of the opposition side of side up promote.
Claim 11 is relevant for a kind of multilayer build-up wiring board, this circuit board system is with interlayer resin insulating layers and conductor layer lamination alternatively, and the multilayer line layer that is connected with via hole between each conductor layer is formed on the two sides of core base, the conductor layer on above-mentioned core base two sides is to do electric connection by means of formed through hole on core base to each other, it is characterized in that: set a plurality of line conductors on 1 through hole of above-mentioned core base; And on directly over the through hole that sets above-mentioned a plurality of line conductors, set the via hole that a plurality of line conductor constituted that is connected with above-mentioned each line conductor by respectively.
In the multilayer build-up wiring board of claim 11, because on 1 through hole, set a plurality of line conductors, so the line conductor that is several times as much as through hole is passed through on core base, in addition, because the via hole system that is equipped on directly over this through hole is made of a plurality of line conductor, so the line conductor that is several times as much as via hole is passed through on interlayer resin insulating layers.Therefore, can seek the densification of its circuit of multilayer build-up wiring board.Further, because directly over through hole, be formed with via hole, so line length shortens thereby high speed that can corresponding multilayer build-up wiring board.
Herein, owing on 1 through hole, be equipped with a plurality of line conductors, so the line conductor that is several times as much as through hole is passed through on core base.Therefore, can with the formed multilayer line layer of the table side of core base and in the inboard formed multilayer line layer under same pace, do the integration of circuit, and by means of the multilayer line of multilayer line layer that makes the upper strata and lower floor layer by layer number equate and the number of plies minimized.
Claim 12 is relevant for a kind of multilayer build-up wiring board, this circuit board system is with interlayer resin insulating layers and conductor layer lamination alternatively, and the multilayer line layer that is connected with via hole between each conductor layer is formed on the two sides of core base, the conductor layer on above-mentioned core base two sides is done electric connection by means of formed through hole on core base to each other, it is characterized in that: in the through hole of above-mentioned core base, filled, form the conductor layer that exposes face that has covered from this filler through hole simultaneously with filler; This through hole and this conductor series of strata are repeatedly cut apart; And on directly over the through hole that is covered by above-mentioned divided conductor layer, set the via hole that line conductor constituted that is connected with this divided conductor layer by respectively.
Its constructional being characterised in that of the multilayer build-up wiring board of claim 12: fill filler in the through hole on being built in core base, and and then form the conductor layer that exposes face covered from this filler through hole; Carry out being connected between superimposed line layer and through hole by means of in this conductor layer, via hole being connected.
According to this formation, can make the dead angle not exist by means of the function that the zone directly over the through hole is served as for the internal layer welding zone.And, because also need be by through hole in order to the circuit the internal layer welding zone in connecting path hole, so the island shape of through hole can form genuine circle.As a result, the configuration density that is arranged on the through hole in the multilayer film core substrate is upwards promoted, and can increase the number of through hole at an easy rate, also can be connected with the overlapping layers on surface simultaneously by the holding wire of this through hole with the superimposed line layer of inboard.By means of on the through hole of this increase number, setting a plurality of line conductors and on via hole, setting a plurality of line conductors, can reach the densification of multilayer build-up wiring board.
On the other hand, in the above-mentioned multilayer build-up wiring board about claim 12, the filler system that is used for filling through hole is with preferable by metallic and thermosetting or thermoplastic resin institute constitutor.
Being used for filling the filler of through hole in the multilayer build-up wiring board of claim 12, is with by metallic, thermosetting resin and curing agent also or preferable by metallic and thermoplastic resin institute constitutor, also can add solvent in case of necessity.Aforesaid filler is if contain metallic, owing to its surface grinding to metal ion can be exposed, and can be via this metal ion that exposes with conductor layer electroplating film formed thereon implement integrated, so even under high temperature harsh as PCT (pressure cooking test) as wets condition more also not can with the interface of conductor layer on the phenomenon peeled off of generation.In addition, this filler is because be to be filled in the through hole that is formed with metal film on wall, so can not produce the diffusion phenomena of metal ion.
With metallic, can use copper, gold, silver, aluminium, nickel, titanium, chromium, tin/lead, palladium, platinum etc.In addition, the particle diameter of this metallic system is preferable with 0.1～50 μ m.Its reason is: if less than 0.1 μ m, the copper surface can make wettability variation to resin because of oxidation; On the other hand, if surpass 50 μ m, then printing can variation.In addition, the allotment amount of this metal ion system is being that 30～90 weight % are preferable with respect to all weight.Its reason is: if lack than 30 weight %, then the closely bonding property of initial plating is understood variation; On the other hand, if surpass 90 weight %, then printing can variation.
With employed resin, can use the fluorine resin of the epoxy resin, phenolic resin of bisphenol A-type, Bisphenol F type etc., poly-imide resin, polytetrafluoroethylene (PTFE) etc., span come acid anhydrides contract imines three azines (bismaleimide triazine) (BT) resin, FEP, PFA, PPS, PEN, PES, nylon (nylon), kill full special (aramite), PEEK, PEKK, PET etc.
With curing agent, can use the curing agent of imidazoles system, phenol system and amine system etc.
With solvent, can use NMP (positive methyl pyrrolidone) (normal methvlpyrrolidone), DMDG (diethyleneglycol dimethyl ether) (diethyleneglycoldimethyl ether), glycerol, water, 1-or 2-or 3-cyclohexanol, cyclohexanone, Propylene Glycol ether (methyl cellosolve), Propylene Glycol ether acetic acid esters (methylcellosolve acetate), methyl alcohol, ethanol, butanols and propyl alcohol etc.
This filler system thinks that non-conductive person is preferable.This is because non-conductive person's sclerosis contraction is very little, is difficult for and conductive layer or via hole peeling off phenomenon.
The inventor through the result of research with keen determination, has expected that with content as follows be the invention that constitutes main idea to achieve these goals.
That is, circuit substrate as claimed in claim 13, this substrate has the conductor circuit that comprises two layers of structure conductor layer, these two layers structure conductor series of strata are by constituting at the second thin metal film of above-mentioned first metal film of the first metal film upper strata pressure ratio, and it is characterized in that: the side that constitutes second metal film of above-mentioned conductor layer is more side-prominent more outward than the side of above-mentioned first metal film.
In addition, the multilayer build-up wiring board of claim 14, have the structure that forms resin insulating barrier and conductor circuit more than 1 layer respectively having on the resin substrate, it is characterized in that: at least 1 series of strata of above-mentioned conductor circuit are to be included in two layers of structure conductor layer that the second thin metal film of above-mentioned first metal film of the first metal film upper strata pressure ratio constitutes; And the side that constitutes second metal film of above-mentioned conductor layer is more side-prominent more outward than the side of above-mentioned first metal film.
If words according to the formation of claim 13, because the side of formed second metal film system is more side-prominent more outward than the side of above-mentioned first metal film on above-mentioned first metal film, so be above-mentioned the grade when forming resin insulating barrier on the conductor layer, even situation such as caused that because of the structure of this overhang temperature changes, stress also can not concentrate on the bight of above-mentioned conductor layer, and the result can prevent to produce the crack on above-mentioned resin insulating barrier.
The accompanying drawing simple declaration
Fig. 1 (A), Fig. 1 (B), Fig. 1 (C) and Fig. 1 (D) are the manufacturing procedure picture of the multilayer build-up wiring board of the present invention the 1st embodiment.
Fig. 2 (E), Fig. 2 (F), Fig. 2 (G) and Fig. 2 (H) are the manufacturing procedure picture of the multilayer build-up wiring board of the present invention the 1st embodiment.
Fig. 3 (I), Fig. 3 (J), Fig. 3 (K) and Fig. 3 (L) are the manufacturing procedure picture of the multilayer build-up wiring board of the present invention the 1st embodiment.
Fig. 4 (M), Fig. 4 (N) and Fig. 4 (O) are the manufacturing procedure picture of the multilayer build-up wiring board of the present invention the 1st embodiment.
Fig. 5 (P) and Fig. 5 (Q) are the manufacturing procedure picture of the multilayer build-up wiring board of the present invention the 1st embodiment.
Fig. 6 is the profile of the multilayer build-up wiring board of the present invention the 1st embodiment.
Fig. 7 (A) is the A-A profile of Fig. 6, and Fig. 7 (B) is the B-B profile of Fig. 6.
Fig. 8 (A) is the profile about the multilayer build-up wiring board of experimental example of the present invention, and Fig. 8 (B) and Fig. 8 (C) then are the configuration instruction figure of netted hole.
Fig. 9 (A) is the profile of the multilayer build-up wiring board of the 1st comparative example, and Fig. 9 (B) is the netted hole configuration instruction figure of the 1st comparative example, and Fig. 9 (C) then is the flatness layer plane graph of prior art.
Figure 10 is the Insulation Test figure of interlayer resin insulating layers of the multilayer build-up wiring board of experimental example and the 1st comparative example.
Figure 11 (A), Figure 11 (B), Figure 11 (C) and Figure 11 (D) are the manufacturing procedure picture of the multilayer build-up wiring board of the present invention the 2nd embodiment.
Figure 12 (E), Figure 12 (F), Figure 12 (G) and Figure 12 (H) are the manufacturing procedure picture of the multilayer build-up wiring board of the present invention the 2nd embodiment.
Figure 13 (I), Figure 13 (J), Figure 13 (K) and Figure 13 (L) are the manufacturing procedure picture of the multilayer build-up wiring board of the present invention the 2nd embodiment.
Figure 14 (M), Figure 14 (N), Figure 14 (O) and Figure 14 (P) are the manufacturing procedure picture of the multilayer build-up wiring board of the present invention the 2nd embodiment.
Figure 15 (Q), Figure 15 (R) and Figure 15 (S) are the manufacturing procedure picture of the multilayer build-up wiring board of the present invention the 2nd embodiment.
Figure 16 is the profile of the multilayer build-up wiring board of the present invention the 2nd embodiment.
Figure 17 is the profile of the multilayer build-up wiring board of the present invention the 2nd embodiment.
Figure 18 (A) is the D-D profile of Figure 17, and Figure 18 (B) is the netted hole enlarged drawing of Figure 18 (A), and Figure 18 (C) then is the netted hole enlarged drawing of Change Example.
Figure 19 system is about the profile of the multilayer build-up wiring board of the 1st Change Example of the 2nd embodiment.
Figure 20 (A) is the F-F profile of Figure 19, and Figure 20 (B) is the enlarged drawing of the netted hole shown in Figure 20 (A), and Figure 20 (C) then is the netted hole enlarged drawing of Change Example.
Figure 21 (A) is the flatness layer plane graph about the multilayer build-up wiring board of the 2nd Change Example of the 2nd embodiment, and Figure 21 (B) then ties up to the expanded view of the netted hole Change Example shown in Figure 21 (A).
Figure 22 (A) is the flatness layer plane graph about the multilayer build-up wiring board of the 3rd Change Example of the 2nd embodiment, and Figure 22 (B) is the profile of this multilayer board, and Figure 22 (C) then is the profile of the multilayer board of Change Example.
Figure 23 system is about the flatness layer plane graph of the multilayer build-up wiring board of prior art.
Figure 24 (A), Figure 24 (B), Figure 24 (C), Figure 24 (D), and Figure 24 (E) be the manufacturing procedure picture of the multilayer build-up wiring board of the present invention the 3rd embodiment.
Figure 25 (F), Figure 25 (G), Figure 25 (H), Figure 25 (I), and Figure 25 (J) be the manufacturing procedure picture of the multilayer build-up wiring board of the present invention the 3rd embodiment.
Figure 26 (K), Figure 26 (L), Figure 26 (M), Figure 26 (N), and Figure 26 (O) be the manufacturing procedure picture of the multilayer build-up wiring board of the present invention the 3rd embodiment.
Figure 27 (P), Figure 27 (Q), Figure 27 (R) and Figure 27 (S) are the manufacturing procedure picture of the multilayer build-up wiring board of the present invention the 3rd embodiment.
Figure 28 (T), Figure 28 (U) and Figure 28 (V) are the manufacturing procedure picture of the multilayer build-up wiring board of the present invention the 3rd embodiment.
Figure 29 (W), Figure 29 (X) and Figure 29 (Y) are the manufacturing procedure picture of the multilayer build-up wiring board of the present invention the 3rd embodiment.
Figure 30 (ZA), Figure 30 (ZB) and Figure 30 (ZC) are the manufacturing procedure picture of the multilayer build-up wiring board of the present invention the 3rd embodiment.
Figure 31 is the profile of the multilayer build-up wiring board of the present invention the 3rd embodiment.
Figure 32 system is about installing the state profile of IC chip on the multilayer build-up wiring board of the present invention the 3rd embodiment.
Figure 33 (A) is the A-A drawing in side sectional elevation of Figure 31, and Figure 33 (B) is the via hole key diagram of the multilayer build-up wiring board of the 3rd embodiment, and Figure 33 (C) is the C-C drawing in side sectional elevation of Figure 31, and Figure 33 (D) is the through hole key diagram of the multilayer build-up wiring board of the 3rd embodiment.
Figure 34 (A), Figure 34 (B) are the profile of multilayer build-up wiring board of the 1st Change Example of the 3rd embodiment.
Figure 35 (A) is the profile of multilayer build-up wiring board of the 1st Change Example of the 3rd embodiment, and Figure 35 (B) the 1st changes the through hole of agent and the plane graph on island.
Figure 36 is the profile of an example of the circuit substrate of the present invention the 4th embodiment.
Figure 37 (A), Figure 37 (B), Figure 37 (C), Figure 37 (D) and Figure 37 (E) are the profile about an example of the manufacturing process of the circuit substrate of the 4th embodiment.
Figure 38 (A), Figure 38 (B), Figure 38 (C) and Figure 38 (D) are a part of profile about the manufacturing process of the multilayer build-up wiring board of the 4th embodiment.
Figure 39 (A), Figure 39 (B), Figure 39 (C) and Figure 39 (D) are a part of profile about the manufacturing process of the multilayer build-up wiring board of the 4th embodiment.
Figure 40 (A), Figure 40 (B), Figure 40 (C) and Figure 40 (D) are a part of profile about the manufacturing process of the multilayer build-up wiring board of the 4th embodiment.
Figure 41 (A), Figure 41 (B), Figure 41 (C) and Figure 41 (D) are a part of profile about the manufacturing process of the multilayer build-up wiring board of the 4th embodiment.
Figure 42 (A), Figure 42 (B) and Figure 42 (C) are a part of profile about the manufacturing process of the multilayer build-up wiring board of the 4th embodiment.
Figure 43 (A), Figure 43 (B) tie up to resulting multilayer build-up wiring board profile among the 4th embodiment.
The most preferred embodiment of invention
The 1st embodiment
Below, just multilayer build-up wiring board and the manufacture method thereof of the present invention the 1st embodiment describe with reference to accompanying drawing.
At first, just the formation of the multilayer build-up wiring board 10 of the present invention the 1st embodiment describes with reference to Fig. 6.In this multilayer build-up wiring board 10, the surface and the inside that tie up to core base 30 are formed with in order to form the flatness layer 35 of ground plane.In addition, on face side flatness layer 35 and the inside side flatness layer 35, be formed with superimposed line layer 80A, 80B.This superimposed line layer 80A system is by being formed with via hole 60, conductor circuit 58 and as the interlayer resin insulating layers 50 of the flatness layer 59 of bus plane, and the interlayer resin insulating layers 150 that has been formed with via hole 160 and conductor circuit 158 constitutes.In addition, superimposed line layer 80B system is by the interlayer resin insulating layers 50 that is formed with via hole 60 and conductor circuit 58, and the interlayer resin insulating layers 150 that has been formed with via hole 160 and conductor circuit 158 constitutes.
Be equipped with solder bump 76U in the above on the side in order to the island that connects integrated circuit (IC) chip (not shown).Solder bump 76U is by via hole 160 and via hole 60 and be connected with through hole 36.On the other hand, be equipped with solder bump 76D below on the side in order to the island that connects daughter board (dot board) (not shown).This solder bump 76D is by via hole 160 and via hole 60 and be connected with through hole 36.
The A-A section of Fig. 6, that is on the surface of interlayer resin insulating layers 50 plane of formed flatness layer 59, as shown in Fig. 7 (A); The B-B section of Fig. 6, that is on the surface of core base 30 plane of formed flatness layer 35, be as shown in Fig. 7 (B).Shown in Fig. 7 (A), on the flatness layer 59 on interlayer resin insulating layers 50 surfaces, the netted hole 59a of diameter 200 μ m is formed with the interval of spacing P (500 μ m).Similarly, shown in Fig. 7 (B), also on the flatness layer 35 of core base 30 face side, the netted hole 35a of diameter 200 μ m is formed with the interval of spacing P (500 μ m).Though not shown, on the side of the inside of core base 30, also form same netted hole 35a.
In the multilayer build-up wiring board 10 of the 1st embodiment, as shown in Figure 6,, dispose in overlapping fully mode with the netted hole 59a of the flatness layer 59 of interlayer resin insulating layers 50 with the flatness layer 35 on core base 30 two sides and 35 netted hole 35a, 35a.Therefore, the insulating properties of interlayer resin insulating layers 50 can not reduce.
Below, describe with reference to accompanying drawing with regard to the manufacture method of the multilayer build-up wiring board of the 1st embodiment.
Herein, describe at the composition of employed A. electroless plating in the manufacture method of the multilayer board of the 1st embodiment with bonding agent, the agent of B. layer insulation, C. resin filler, D. scolding tin diaphragm composition.
A. electroless plating is modulated the feedstock composition (upper strata bonding agent) of usefulness with bonding agent
[resin combination 1.]
For with cresol novolac resin type epoxy resin (Japanese chemical drug system, molecular weight 1700) 25% propen compounds is dissolved in 35 unit of weights, photo-sensitive monomer (the synthetic system in East Asia of the resin liquid of DMDG with the concentration of 80 weight %, ア ロ ニ Star Network ス M315) (サ Application ノ プ コ system, S-65) 0.5 unit of weight and NMP 3.6 unit of weights mix and get for 3.15 unit of weights, defoamer.
[resin combination 2.]
With polyether sulfone (PES) 12 unit of weights, (Sanyo changes into system to the epoxy resin particle, polymer pole (polymer pole)) average grain diameter is that 1.0 μ m persons, 7.2 unit of weights and average grain diameter are after 0.5 μ m person, 3.09 unit of weights are mixed, further add NMP 30 unit of weights again, and mix and get with the particle grinder.
[hardener composition 3.]
(four countries change into system with imidazole hardeners, 2E4MZ-CN) 2 unit of weights, light initiator (チ バ ガ イ ギ one system, イ Le ガ キ ユ ア I-907) 2 unit of weights, (Japanese chemical drug system, DETX-S) 0.2 unit of weight and NMP 1.5 unit of weights mix and get emulsion.
B. the feedstock composition (lower floor's bonding agent) of usefulness is modulated in the agent of interlayer insulation resin
[resin combination 1.]
For with cresol novolac resin type epoxy resin (Japanese chemical drug system, molecular weight 1700) 25% propen compounds is dissolved in 35 unit of weights, photo-sensitive monomer (the synthetic system in East Asia of the resin liquid of DMDG with the concentration of 80 weight %, サ Application ノ プ コ M 315) (ア ロ ニ Star Network ス system, S-65) 0.5 unit of weight and NMP 3.6 unit of weights mix and get for 4 unit of weights, defoamer.
[resin combination 2.]
(Sanyo changes into system with polyether sulfone (PES) 12 unit of weights and epoxy resin particle, polymer pole (polymer pole)) average grain diameter is after 0.5 μ m person, 14.49 unit of weights are mixed, further add NMP 30 unit of weights again, and mix and get with the particle grinder.
[hardener composition 3.]
(four countries change into system with imidazole hardeners, 2E4MZ-CN) 2 unit of weights, light initiator (チ バ ガ イ ギ one system, イ Le ガ キ ユ ア I-907) 2 unit of weights, (Japanese chemical drug system, DETX-S) 0.2 unit of weight and NMP 1.5 unit of weights mix and get emulsion.
C. the resin filler is modulated the feedstock composition of usefulness
[resin combination 1.]
Average grain diameter by being coated with silane coupling agent with bisphenol f type epoxy resin monomer (oiling シ エ Le system: molecular weight 310, trade name YL983U) 100 weight portions, from the teeth outwards is the SiO of 1.6 μ m 2Spherical particle (ア De マ テ Star Network system, CRS1101-CE, herein, the size of maximum particle ties up to below the thickness (15 μ m) of internal layer copper pattern described later) 170 weight portions and smooth dose of (サ Application ノ プ コ system, プ レ ノ one Le S4) 1.5 weight portions are implemented and are mixed, and the viscosity of this mixture is adjusted under 23 ± 1 ℃ is 45,000～49,000cps.
[resin combination 2.]
(four countries change into system to imidazole hardeners: 6.5 weight portions trade name 2E4MZ-CN).
D. scolding tin diaphragm composition
Be dissolved in DMDG 60 weight % cresol novolac resin type epoxy resin (Japanese chemical drug system) epoxy radicals 50% propyleneization give photosensitive oligomer (molecular weight 4000) 46.67 gram; be dissolved in bisphenol A type epoxy resin (the oiling シ エ Le system of 80 weight % of methyl ethyl ketone (methyl ethyl ketone); EPCOAT1001) 15.0 grams; (four countries change into system to imidazole hardeners; 2E4MZ-CN) 1.6 grams; multivalence propylene monomer (the Japanese chemical drug system of photo-sensitive monomer; R604) 3 grams; multivalence propylene monomer of the same type (common prosperity society chemistry system; DPE6A) 1.5 gram and disperse system defoamer (サ Application ノ プ コ corporate systems; S-65) 0.71 gram mixes mutually; further in this mixture, add again as the light initiator benzophenone (Northeast chemistry system) 2 grams and as Michler's keton (Northeast chemistry system) 0.2 gram of sensitizing photo etching, can obtain viscosity is adjusted into 2.0Pas under 25 ℃ scolding tin diaphragm composition.
In addition, Brookfield viscometer (Tokyo gauge, DVL-B type) is then used in viscosimetric analysis, uses rotor (rotor) No.4 under the situation of 60rpm, and use rotor (rotor) No.3 under the situation of 6rpm.
Then, the manufacturing process with regard to the multilayer board of the 1st embodiment describes with reference to Fig. 1～Fig. 6.In the 1st embodiment, multilayer build-up wiring board system utilizes semi-additive process to form.
(1) with the copper plate pressing plate 30A that become at the thickness 1mm shown in Fig. 1 (A) and for the Copper Foil 32 of lamination 18 μ m on by the two sides of glass epoxy resin or BT (span come acid anhydrides the contract imines three azines) substrate 30 that resin was constituted as parent material.At first, this copper plate pressing plate 30A with bit bore, is bestowed electroless plating again and handles, and the according pattern shape is by etching formation through hole 36 and flatness layer 35, to form the core base 30 shown in Fig. 1 (B).With reference to Fig. 7 (B) and as above-mentioned, on flatness layer 35, be formed with netted hole 35a.
(2) will form substrate 30 washing and drying of flatness layer 35 and through hole 36 after, by means of go up use NaOH (10g/l), NaClO at oxidation bath (melanism baths) 2(40g/l), Na 3PO 4(6g/l), on reducing bath, use NaOH (10g/l), NaBH 4OR (6g/l) is handled, and sets up roughened layer 38 (with reference to Fig. 1 (C)) in the surface of flatness layer 35 and through hole 36.
(3) feedstock composition of the resin filler of C being modulated usefulness carries out mixed milling and obtains the resin filler.
(4) by means of the two sides that resulting resin filler 40 in aforementioned (3) was coated on substrate 30 in modulation in back 24 hours with interior use cylinder spreader, within the netted hole 35a and through hole 36 that fill conductor circuit (flatness layer) 35, then following dry 20 minutes in 70 ℃, another side also utilizes the same mode and resin filler 40 is filled within netted hole 35a or the through hole 36, and in 70 ℃ of following heat dryings 20 minutes (with reference to Fig. 1 (D)).
(5) one side of the substrate 30 that will handle end through above-mentioned (4) is ground by means of the banded sander that uses the banded pouncing paper of #600 (three physics and chemistry length of schooling) altogether, with the surface grinding of the island 36a of the surface of flatness layer 35 and through hole 36 to not remaining resin filler, then, carry out grinding because of the polishing that this band shape sander grinds caused scar in order to removal.On the another side of substrate, also carry out the grinding (with reference to Fig. 2 (E)) of the same step.
Then, carry out 100 ℃ following 1 hour, 120 ℃ following 3 hours, 150 ℃ following 1 hour and 180 ℃ of following heat treated of 7 hours so that 40 sclerosis of resin filler.
As mentioned above, be filled in the skin section of resin filler 40 of through hole 36 grades and the roughened layers 38 above the flatness layer 35 by means of removal and with substrate 30 two sides smoothings, the side that can obtain resin filler 40 and flatness layer 35 closely bonds and the internal face of through hole 36 and the printed circuit board (PCB) that resin filler 40 also closely bonds by means of roughened layer 38 strongly by means of roughened layer 38 strongly.That is, by means of this operation, make the surface of resin filler 40 and the surface of flatness layer 35 become same plane.
(6) on the substrate 30 that forms flatness layer 35, carry out the soft etching of alkaline degreasing, then use the catalyst solution that constitutes by palladium bichloride and organic acid to handle, revest Pd catalyst, after this catalyst activityization, in by copper sulphate 3.2 * 10 -2Mol/l, nickelous sulfate 3.9 * 10 -3Mol/l, complexing agent 5.4 * 10 -2Mol/l, inferior sodium phosphate 3.3 * 10 -1Mol/l, boric acid 5.0 * 10 -1Soak in the electroless plating liquid that condition constituted such as mol/l and interfacial agent (day letter chemical industrial company system, surfino1465) 0.1g/l and pH=9, and after soaking 1 minute, carry out per 4 seconds 1 time longitudinal and transverse vibration, on the surface of the island 36a of flatness layer 35 and through hole 36, acicular alloy coating and the roughened layer 42 (with reference to Fig. 2 (F)) that is made of Cu-Ni-P to be set.
And then, under the condition of boron tin fluoride 0.1mol/l, thio urea 1.0mol/l, 35 ℃ of temperature and pH=1.2, carry out the Cu-Sn displacement reaction, with surface the Sn layer (not shown) that thickness is 0.3 μ m is set in roughened layer.
(7) feedstock composition with the interlayer insulation resin agent of B modulation usefulness mixes, and obtains the interlayer insulation resin agent that viscosity is adjusted into 1.5Pas (lower floor with).
Then, the feedstock composition that the electroless plating of A is modulated usefulness with bonding agent mixes, and obtains the electroless plating adhesive solution (upper strata is used) that viscosity is adjusted into 7Pas.
(8) on the two sides of the substrate of aforementioned (6) with aforementioned (7) in resulting viscosity be that the interlayer insulation resin agent (lower floor with) 44 of 1.5Pas is coated with interior use cylinder spreader in back 24 hours of modulation, and after under level, placing 20 minutes, in 60 ℃ of down dry 30 minutes (prebake conditions), then, the photosensitive adhesive agent solution (upper strata with) 46 that with resulting viscosity in aforementioned (7) is 7Pas is coated with interior in back 24 hours of modulation, and after under level, placing 20 minutes, in 60 ℃ of down dry (preceding bakings) in 30 minutes, can form thickness is bond layer 50 α (with reference to Fig. 2 (G)) of 35 μ m.
(9) will form in above-mentioned (8) on the two sides of substrate 30 of bond layer, the not shown photomask (not shown) that is printed with the black circle of φ 85 μ m has been closely bonded, and use extra-high-pressure mercury vapour lamp with 500mJ/cm 2Expose.Then develop, further use extra-high-pressure mercury vapour lamp with 3000mJ/cm this substrate 30 again with DMTG solution hydro-peening 2Expose, and by means of bestow 100 ℃ following 1 hour, 120 ℃ following 1 hour and after in 150 ℃ of following heat treated of 3 hours (back baking), and form the interlayer resin insulating layers (2 layers of structure) 50 (with reference to Fig. 2 (H)) of the thickness 35 μ m with the φ 85 μ m openings (via hole formation perforate) 48 that are equivalent to photomask size and precision excellence.In addition, at perforate 48 places tin electrodeposited coating (not shown) is exposed partially as via hole.
(10) impregnated in the chromic acid 19 minutes by means of the substrate 30 that will form perforate 48, the epoxy resin particle dissolving that is present in interlayer resin insulating layers 50 surfaces can be removed, and the surface (with reference to Fig. 3 (I)) of this interlayer resin insulating layers 50 of alligatoring simultaneously.Again resulting substrate impregnated in neutralization solution (シ プ レ イ society system) after again washing thereafter.
(11) through the process of above-mentioned (10) and on the surface of the substrate 30 after the alligatoring,, catalyst core is attached on the surface of interlayer resin insulating layers 50 by means of giving of palladium catalyst (ア ト テ Star Network system).Afterwards, substrate 30 is immersed in the electrolytic copper free electroplating aqueous solution of composition as shown below, and forms the electroless plating film 52 that all thickness is 0.6 μ m (with reference to Fig. 3 (J)).
[the electroless plating aqueous solution]
EDTA 150g/l
Copper sulphate 20g/l
HCHO 30ml/l
NaOH 40g/l
α, α '-bipyridyl 80mg/l
(α，α′-bipyridyl)
PEG 0.1g/l
[electroless plating condition]
Following 30 minutes of the liquid that temperature is 70 ℃
(12) in above-mentioned (11), stick commercially available photosensitive dry film on the formed electrolytic copper free electroplating film 52, mask then is installed, again with 100mJ/cm 2Expose, and carry out development treatment, and the electroplating film 54 (with reference to Fig. 3 (K)) of thickness 15 μ m is set with 0.8% sodium carbonate.
(13) then, implement the cathode copper of following condition in the part that does not form diaphragm and electroplate, and the cathode copper electroplating film 56 (with reference to Fig. 3 (L)) of formation thickness 15 μ m.
[the metallide aqueous solution]
Sulfuric acid 180g/l
Copper sulphate 80g/l
Additive (ア ト テ Star Network Japan system, trade name カ パ ラ シ De GL)
1ml/l
[metallide condition]
Current density 1A/dm 2
30 minutes time
The degree room temperature
(14) electroplating film 54 is peeled off removal with 5%KOH after; again the electrolytic copper free electroplating film 52 under this electroplating film being implemented etch processes and dissolved removal with the mixed liquor of sulfuric acid and hydrogen peroxide, is conductor circuit 58, flatness layer 59 and the via hole 60 (Fig. 4 (M)) of 18 μ m and form the thickness that is made of electrolytic copper free electroplating film 52 and cathode copper electroplating film 56.Herein, as above-mentioned, on flatness layer 59, be formed with netted hole 59a, and this netted hole 59a forms in overlapping mode with the netted hole 35a of formed flatness layer 35 on the two sides of core base 30 with reference to Fig. 7 (A).
(15) carry out the processing identical, and on the surface of conductor circuit 58, flatness layer 59 and via hole 60, form the alligatoring face 62 that constitutes by Cu-Ni-P, and further implement Sn displacement (with reference to Fig. 4 (N)) on its surface with (6).
(16), and finish the manufacturing (with reference to Fig. 4 (O)) of multilayer build-up wiring board by means of the process of repeatable operation (7)～(15) interlayer resin insulating layers 150, via hole 160 and conductor circuit 158 with further formation upper strata.In addition, in the process of the conductor circuit that forms this upper strata, do not carry out the Sn displacement.
(17) then, on above-mentioned multilayer build-up wiring board, form solder bump.In above-mentioned (16) on the two sides of resulting substrate 30, the scolding tin diaphragm composition that is illustrated among the above-mentioned D. is coated with the thickness of 45 μ m.Secondly, finish in 70 ℃ following 20 minutes and after 70 ℃ of following dried of 30 minutes, making and describing circle diagram case (mask pattern) and thickness is that the photomask (not shown) of 5mm closely bonds, again with 1000mJ/cm 2Ultraviolet ray expose, and carry out the DMTG development treatment.And then, partly (comprise via hole and island thereof partly) and form scolding tin protective film (thickness 20 μ m) 70 (with reference to Fig. 5 (P)) of (the opening footpath 200 μ m) 71 that have opening in the scolding tin welding zone further implementing under 80 ℃ following 1 hour, 100 ℃ following 1 hour, 120 ℃ following 1 hour and 150 ℃ of following 3 hours the conditions after the heat treated.
(18) secondly, this substrate 30 be impregnated in by nickel chloride 2.31 * 10 -1Mol/l, inferior sodium phosphate 2.8 * 10 -1Mol/l and natrium citricum 1.85 * 10 -1In the no electrolytic nickel electroplate liquid of the pH=4.5 that mol/l constituted 20 minutes, and on peristome 71, form the nickel electrodeposited coating 72 of thickness 5 μ m.Then, further this substrate be impregnated in by potassium auricyanide 4.1 * 10 under 80 ℃ condition again -2Mol/l, ammonium chloride 1.87 * 10 -1Mol/l, natrium citricum 1.16 * 10 -1Mol/l and inferior sodium phosphate 1.7 * 10 -1In the electroless gold plating liquid for forming gold plating film for wire bonding that mol/l constituted 7 minutes and 20 seconds, form scolding tin welding zone 75 (with reference to Fig. 5 (Q)) to go up in via hole 160 and conductor circuit (not shown) by means of the golden electrodeposited coating 74 that on the nickel electrodeposited coating, forms thickness 0.03 μ m.
(19) then, carry out soft heat and form solder bump (scolding tin body) 76U, 76D, promptly finish the manufacturing (with reference to Fig. 6) of multilayer board 10 by means of printed solder paste on the peristome 71 of scolding tin protective film 70 and with 200 ℃.
(experimental example)
Continue, describe with reference to Fig. 8 and Fig. 9 with regard to experimental example of the present invention and the 1st comparative example.
It shown in Fig. 8 (A) profile relevant for the multilayer build-up wiring board of experimental example of the present invention.The multilayer build-up wiring board of this experimental example system utilizes the method identical with multilayer build-up wiring board 10 among above-mentioned the 1st embodiment and forms.Yet, in the 1st embodiment, have on core base, to form through hole, but in this experimental example, do not form through hole.In addition, in this experimental example, form flatness layer 135 below not only on core base 130, reaching, also form flatness layer 179,189 on the interlayer resin insulating layers 170 of side and following side and the outermost interlayer resin insulating layers 180 in the above respectively simultaneously.Tie up to the netted hole 179a and the corresponding relation figure between the netted hole 189a of formed flatness layer 189 on the outermost interlayer resin insulating layers 180 of formed flatness layer 179 on the interlayer resin insulating layers 170 shown in Fig. 8 (B).In this experimental example,, utilize overlapping mode to form netted hole 135a, the netted hole 179a of flatness layer 179 of the flatness layer 135 of core base 130 and the netted hole 189a of flatness layer 189 with reference to Fig. 6 and same with the 1st above-mentioned embodiment.Herein, netted hole system disposes with diameter 250 μ m, spacing 550 μ m.
On the other hand, be the profile relevant for the multilayer build-up wiring board of the 1st comparative example shown in Fig. 9 (A), Fig. 9 (B) is the corresponding relation figure between the netted hole 189a of the netted hole 179a of flatness layer 179 of multilayer build-up wiring board of the 1st comparative example and flatness layer 189.The manufacture method of the multilayer build-up wiring board of the 1st comparative example is fully identical with above-mentioned experimental example, have only differently with the experimental example shown in Fig. 8 (A), that is the netted hole 135a of the flatness layer 135 of core base 130, the netted hole 179a of flatness layer 179 and the netted hole 189a of flatness layer 189 are not configured in overlapping mode each other.
Herein, the result that the interlayer resin insulating layers of experimental example and the 1st comparative example is carried out Insulation Test just describes with reference to the figure of Figure 10.
Herein, implement the STEC test of Insulation Test.This STEC test system is at 10 multilayer build-up wiring boards, under 121 ℃, the cond of 100%Rh, 2.1atm, keep 336 hours after, measure the insulation impedance between its interlayer resin insulating layers.In the drawings, longitudinal axis numeral multiplier, transverse axis are then taken from spacing (μ m) and the netted hole diameter (μ m) between netted hole.
In experimental example, the netted hole diameter is set at 250 μ m, spacing is set at (shown in (a) among the figure) in the 550 μ m, insulation impedance can maintain 1 * 10 9Near the Ω.In the 1st comparative example under the same conditions, then as (c) among the figure, insulation impedance is reduced to 1 * 10 8The degree of Ω.On the other hand, in experimental example, the netted hole diameter is set at 250 μ m, spacing is set at (shown in (b) among the figure) in the 500 μ m, insulation impedance can maintain 1 * 10 9More than the Ω.In the 1st comparative example under the same conditions, then as (d) among the figure, insulation impedance is reduced to 1 * 10 8The degree of Ω.
By this result of the test as can be known, have correlation between the position of netted hole and the insulation impedance of interlayer resin insulating layers, therefore by means of as experimental example with netted hole with about overlapping mode set, can improve the insulation impedance of interlayer resin insulating layers.
In addition, if with the overlapping some of netted hole up and down, also can improve the insulation impedance of interlayer resin insulating layers.Tie up to the netted hole 189a and the location diagram between the netted hole 179a of formed flatness layer 179 on the interlayer resin insulating layers 170 of formed flatness layer 189 on the outermost interlayer resin insulating layers 180 shown in Fig. 8 (c).When utilizing above-mentioned manufacture method, can produce the site error of 35 μ m degree in netted hole 189a up and down, 179a place with reference to the 1st embodiment.Though can produce the site error of 35 μ m degree and since the diameter of netted hole system with 70 μ m with on form, so the some of netted hole can be overlapping at least, therefore can improve the insulation impedance of interlayer resin insulating layers.
In the multilayer build-up wiring board of aforesaid the 1st embodiment, because the netted hole of flatness layer system forms in a part of at least overlapping mode up and down, so the insulating properties of interlayer resin insulating layers can not reduce.
[the 2nd embodiment]
Below, just multilayer build-up wiring board and the manufacture method thereof of the present invention the 2nd embodiment describe with reference to accompanying drawing.
At first, just the formation of the multilayer build-up wiring board 10 of the present invention the 2nd embodiment describes with reference to Figure 16, Figure 17 and Figure 18.
Shown in Figure 16 is the profile of the multilayer board 10 before I C chip is installed.Shown in Figure 17 is that IC chip 90 will be on the multilayer board shown in Figure 16 10 be installed, and circuit board is installed on state diagram on the daughter board 94.
In multilayer build-up wiring board 10 as shown in Figure 16, in core base 30, form through hole 36, go up to form the flatness layer 34U as bus plane again in the surface of this core base 30 (IC chip side), (daughter board side) forms the flatness layer 34D as ground plane then and in the inside.Above this flatness layer 34U, 34D, set the lower layer side interlayer resin insulating layers 50 that forms via hole 60 and conductor circuit 58 again.Disposed on this lower interlayer resin insulating layers 50 form on via hole 160 and the conductor circuit 158 (only being illustrated in the inside side) layer by layer between resin insulating barrier 150.
On the upper face side of as shown in figure 17 multilayer board, set solder bump 76U in order to the island 92 that connects IC chip 90.Solder bump 76U is via via hole 160 and via hole 60 and be connected with through hole 36.On the other hand, set solder bump 76D below on the side in order to the island 96 that connects daughter board 94.This solder bump 76D is via via hole 160 and via hole 60 and be connected with through hole 36.
The D-D section of Figure 17, that is on the surface of core base 30 plane of formed flatness layer 34U, as shown in figure 18: the E-E section of Figure 18 is equivalent to Figure 17.Shown in Figure 18 (A), on flatness layer 34U, the netted hole 35a of diameter 250 μ m is formed with the interval of spacing P (560 μ m) in the interlayer resin insulating layers in the zone of IC chip 90 in Figure 17 is installed and on the outside of zone C in opposite directions.On the other hand, on the inboard of chip installation area territory C, form the netted hole 35b of calabash shape.This netted hole 35b is amplified the back promptly shown in Figure 18 (B).In this netted hole 35b, set the island 36a and via hole (via bottom) 60a of through hole 36 with gap K across 5～50 μ m.This island 36a is connected by conductor circuit 34c with the welding zone in connecting path hole.
In the multilayer board 10 of the 2nd embodiment, owing to be on the C of the chip installation area territory of flatness layer 34U, to form netted hole 35b, the island 36a of through hole 36 and the welding zone 60a that is connected with via hole also in this netted hole 35b, have been set up simultaneously, so can make the interlayer resin insulating layers 50 that is equipped on flatness layer 34U upper strata directly contact by means of the gap K of the netted hole 36b that sets up in the periphery of this island 36a and the welding zone 60a that is connected with via hole, thereby can improve cementability with the resin molding core substrate 30 that is equipped on lower floor.In addition, because can exhale by the gap K of the netted hole 35b that sets up in the periphery of this island 36a and the welding zone 60a that is connected with via hole by the formed gases such as moisture content that in interlayer resin insulating layers 50 and core base 30, absorbed, so the insulating properties of interlayer resin insulating layers 50 and core base 30 is very high, in addition, also can prevent peeling off of interlayer resin insulating layers.Further, because the welding zone 60a that in the netted hole 35b of this chip installation area territory C, has formed island 36a and be connected with via hole, so can be not uneven, and can make this chip installation area territory C planarization.That is, if in the C of this chip installation area territory, also set the words of netted hole 35b, though can in the 2nd embodiment, reach the effect that makes its planarization because of there being depression residual and uneven in this hole by the welding zone 60a that in the hole, sets island 36a and be connected with via hole.In addition, shown in Figure 18 (C), can be calabash shape, tumbler type and tear type also with island 36a and the welding zone that is connected with via hole integral forming.
Then, just the manufacturing process of the multilayer build-up wiring board of the present invention the 2nd embodiment describes with reference to Figure 11～Figure 16.In the 2nd embodiment, multilayer build-up wiring board system utilizes semi-additive process to form.
(1) with the copper plate pressing plate 30A that become at the thickness 1mm shown in Figure 11 (A) and for the Copper Foil 32 of lamination 18 μ m on by the two sides of glass epoxy resin or BT (span come acid anhydrides the contract imines three azines) substrate 30 that resin was constituted as parent material.At first, this copper plate pressing plate 30A with bit bore, is bestowed electroless plating again and handles, and the according pattern shape is by means of etching formation through hole 36 and flatness layer 34U, 34D, to form the core base 30 shown in Figure 11 (B).With reference to Figure 18 (B) and as above-mentioned, on flatness layer 34U, 34D, form netted hole 35a, 35b, set island 36a, conductor circuit 34c as above-mentioned through hole 36 and the bottom 60a of via hole simultaneously among the netted hole 35b in the C of chip installation area territory.
(2) will form substrate 30 washing and drying of flatness layer 34 and through hole 36 after, by means of go up use NaOH (10g/l), NaC at oxidation bath (melanism baths) 1O 2(40g/l), Na 3PO 4(6g/l), on reducing bath, use NaOH (10g/l), NaBH 4OR (6g/l) is handled, and sets up roughened layer 38 (with reference to Figure 11 (C)) in the surface of flatness layer 34U, 34D and through hole 36.
The feedstock composition of resin filler modulation usefulness that (3) will be identical with the 1st embodiment carries out mixed milling and obtains the resin filler.
(4) by means of the two sides that resulting resin filler 40 in aforementioned (3) was coated on substrate 30 in modulation in back 24 hours with interior use cylinder spreader, within netted hole 35a, the 35b and through hole 36 that fill conductor circuit (flatness layer) 34, then following dry 20 minutes in 70 ℃, other face also utilizes the same mode and resin filler 40 is filled within netted hole 35a or the through hole 36, and in 70 ℃ of following heat dryings 20 minutes (with reference to Figure 11 (D)).
(5) will handle the substrate 30 of ending through above-mentioned (4) and implement grinding (with reference to Figure 12 (E)).Then, carry out heat treated again so that 40 sclerosis of resin filler.
(6) identical with the 1st embodiment acicular alloy coating and the roughened layer 42 (with reference to Figure 12 (F)) that is made of Cu-Ni-P is set on the surface of the bottom 60a of the island 36a of flatness layer 34U and 34D, through hole 36 and via hole.
Next, under the condition of boron tin fluoride 0.1mol/l, thio urea 1.0mol/l, 35 ℃ of temperature and pH=1.2, carry out the Cu-Sn displacement reaction, the Sn layer (not shown) that thickness is 0.3 μ m is set with surface in roughened layer.
The feedstock composition of interlayer insulation resin agent modulation usefulness that (7) will be identical with the 1st embodiment mixes, thereby obtains the interlayer insulation resin agent (lower floor uses) that viscosity is adjusted into 1.5Pas.
Then, electroless plating that will be identical with the 1st embodiment mixes with the feedstock composition of bonding agent modulation usefulness, and obtains the electroless plating adhesive solution (upper strata is used) that viscosity is adjusted into 7Pas.
(8) resulting interlayer insulation resin agent in the coating aforementioned (7) on the two sides of the substrate of aforementioned (6) (lower floor with) 44, then, coating is with resulting photosensitive adhesive agent solution in aforementioned (7) (upper strata is used) 46 again, and promptly forming thickness is bond layer 50 α (with reference to Figure 12 (G)) of 35 μ m.
(9) in above-mentioned (8), formed on the two sides of substrate 30 of bond layer, the photomask 51 (Figure 13 (H)) of the black round 51a that is printed with φ 85 μ m is closely bonded, and the interlayer resin insulating layers (2 layers of structure) 50 (Figure 13 (I)) of the thickness 35 μ m of (via hole forms and uses perforate) 48 of exposing, develop and form and have φ 85 μ m openings.In addition, at perforate 48 places tin electrodeposited coating (not shown) is exposed partially as via hole.
(10) impregnated in the chromic acid 19 minutes by means of the substrate 30 that will form opening 48, the epoxy resin particle dissolving that is present in interlayer resin insulating layers 50 surfaces can be removed, and the surface (with reference to Figure 13 (J)) of this interlayer resin insulating layers 50 of alligatoring simultaneously.Again resulting substrate impregnated in neutralization solution (シ プ レ イ society system) after again washing thereafter.
(11) and on the surface of the substrate 30 after the alligatoring, by means of giving of palladium catalyst (ア ト テ Star Network system), on the surface of catalyst core attached to interlayer resin insulating layers 50 through the operation of above-mentioned (10).Afterwards, substrate 30 is immersed in the electrolytic copper free electroplating aqueous solution with the 1st embodiment same composition, and forms the electroless plating film 52 that all thickness is 0.6 μ m (with reference to Figure 13 (K)).
(12) in above-mentioned (11), stick commercially available photosensitive dry film on the formed electrolytic copper free electroplating film 52, mask then is installed, again with 100mJ/cm 2Expose, and carry out development treatment, and the electroplating film 54 (with reference to Figure 13 (L)) of thickness 15 μ m is set with 0.8% sodium carbonate.
(13) then, electroplate at part execution that does not form diaphragm and the cathode copper under the 1st embodiment the same terms, and the cathode copper electroplating film 56 (with reference to Figure 14 (M)) of formation thickness 15 μ m.
(14) electroplating film 54 is peeled off removal with 5%KOH after; again the electrolytic copper free electroplating film 52 under this electroplating film being implemented etch processes and dissolved removal with the mixed liquor of sulfuric acid and hydrogen peroxide, is conductor circuit 58 and the via hole 60 (Figure 14 (N)) of 18 μ m and form the thickness that is made of electrolytic copper free electroplating film 52 and cathode copper electroplating film 56.
(15) carry out processing with (6) same steps as, and on the surface of conductor circuit 58 and via hole 60, form the alligatoring face 62 that constitutes by Cu-Ni-P, and further implement sn displacement (with reference to Figure 14 (O)) in its surface.
(16), and finish the manufacturing (with reference to Figure 14 (P)) of multilayer build-up wiring board by means of the process of repeatable operation (7)～(15) interlayer resin insulating layers 150, via hole 160 and conductor circuit 158 with further formation upper strata.In addition, in the process of the conductor circuit that forms this upper strata, do not carry out the Sn displacement.
(17) then, on above-mentioned multilayer build-up wiring board, form solder bump.In above-mentioned (16) on the two sides of resulting substrate 30, will be coated with (Figure 15 (Q)) with the thickness of 45 μ m with scolding tin diaphragm composition 70 α of the 1st embodiment same composition.Secondly, expose, development treatment, and partly (comprise via hole and island thereof partly) and form scolding tin protective film (thickness 20 μ m) 70 (with reference to Figure 15 (R)) of (the opening footpath 200 μ m) 71 that have opening at the scolding tin welding zone.
(18) secondly, form nickel electrodeposited coating 72.Further, by means of the golden electrodeposited coating 74 that on the nickel electrodeposited coating, forms thickness 0.03 μ m, and go up formation scolding tin welding zone 75 (with reference to Figure 15 (S)) in via hole 160 and conductor circuit (only diagram the inside side).
(19) then, carry out soft heat and form solder bump (scolding tin body) 76U, 76D, promptly finish the manufacturing (with reference to Figure 16) of multilayer board 10 by means of printed solder paste on the peristome 71 of scolding tin protective film 70 and with 200 ℃.
The corresponding welding zone 92 that IC chip 90 is installed on the solder bump 76U of completed multilayer board 10, and carry out soft heat to load onto IC chip 90.Afterwards, between IC chip 90 and multilayer board 10, fill bottom filler 88.Multilayer board 10 correspondences of loading onto this IC chip 90 are installed on the projection 96 of daughter board 94 sides, and carry out soft heat to be installed on the daughter board 94.Afterwards, between multilayer board 10 and daughter board 94, fill bottom filler 88 again.
Continue, describe with reference to Figure 19 and Figure 20 with regard to the 1st Change Example of the present invention.Shown in Figure 19 is the profile of the multilayer board 110 of the 1st Change Example.In the 2nd above-mentioned embodiment, lie on the two sides of core base 30 and set flatness layer 34U, 34D, and the multilayer board 110 of the 1st Change Example lies in and forms flatness layer 58U, 58D on the interlayer resin insulating layers 50.
That is in the multilayer build-up wiring board 110 of the 1st Change Example, the surface and the inside that lie in core base 30 form conductor circuit 34, form lower layer side interlayer resin insulating layers 50 again on conductor circuit 34.And on lower layer side interlayer resin insulating layers 50, form flatness layer 58U, 58D.Herein, the flatness layer 58 of face side (IC chip side) uses as bus plane, and the flatness layer 58 of the inside side (daughter board side) uses as ground plane.Upper side at this flatness layer 58U, 58D forms upper strata interlayer resin insulating layers 150, and sets via hole 160 and conductor circuit 158.
The F-F section of Figure 19, that is on the surface of interlayer resin insulating layers 50 plane of formed flatness layer 58U, as shown in Figure 20.The G-G section of Figure 20 (A) is equivalent to Figure 19.As shown in figure 20, the netted hole 59a that goes up diameter 200 μ m in flatness layer 58U is formed on the outside of chip installation area territory C.On the other hand, on the inboard of chip installation area territory C, form the netted hole 59b of calabash shape.This netted hole 59b is amplified the back promptly shown in Figure 20 (B).In this netted hole 59b be be provided in across the gap of tens of μ m K interlayer resin insulating layers 50 formed via holes 60 and with welding zone (bottom of the via hole) 160a that is connected at interlayer resin insulating layers 150 formed via holes.That is the island 60 of via hole and the welding zone 160a that is connected with via hole are integrally formed.
In the multilayer board 110 of the 1st Change Example, owing on the C of the chip installation area territory of flatness layer 58U, form netted hole 59b, also in this netted hole 59b, set up simultaneously the welding zone 160a in the island 60 and the connecting path hole of via hole, so can be by means of on the island 60 of this via hole and the gap K of the netted hole 59b that sets up of the periphery of the welding zone 160a in connecting path hole and make the interlayer resin insulating layers 150 that is equipped on flatness layer 58U upper strata directly contact, thereby can improve cementability with the interlayer resin insulating layers 50 that is equipped on lower floor.In addition, because by the formed gases such as moisture content that in interlayer resin insulating layers 150 and 50, absorbed can by on the island 60 of this via hole and the gap K of the netted hole 59b that sets up of the periphery of the welding zone 160a that is connected with via hole exhale, so the insulating properties of interlayer resin insulating layers 150 and 50 is very high, in addition, also can prevent peeling off of interlayer resin insulating layers.Further, owing in the netted hole 59b of this chip installation area territory C, formed the island 60 of via hole and the welding zone 160a that is connected with via hole, thus can be not uneven, and can make this chip installation area territory C planarization.In addition, shown in Figure 20 (C), also can not make the island 60 of via hole and the welding zone 160a that is connected with via hole between being connected partly and attenuating, and form the shape of tumbler type or tear type.
Then, the formation with regard to the multilayer board of the 2nd Change Example describes with reference to Figure 21.
Figure 21 is illustrated in the plane graph of formed flatness layer 34U on the face side of core base.Herein, in above-mentioned the 2nd embodiment with reference to Figure 18, being located in has island 36a that sets through hole and the netted hole 35b of the welding zone 60 that is connected with via hole in the C of chip installation area territory.At herein, in the 2nd Change Example, the netted hole 35b of this calabash shape is set in the C of chip installation area territory not only, circular netted hole 35c also is set, and is to be equipped with β shape conductor layer 34d in this netted hole 35c.In addition, shown in Figure 21 (B), β shape conductor layer 34d also can be with on every side flatness layer 34U the person of being connected more than at least 1 place.
In the multilayer board of the 2nd Change Example, owing on the C of the chip installation area territory of flatness layer 34U, form netted hole 35c, and in this netted hole 35c, set up β shape conductor layer 34d, so can make the interlayer resin insulating layers 50 that is equipped on flatness layer 34U upper strata directly contact by means of the gap of the netted hole 35c that sets up in the periphery of this β shape conductor layer 34d, thereby can improve cementability with the resin molding core substrate 30 that is equipped on lower floor.In addition, because can exhale by the gap of the netted hole 35c that sets up in the periphery of this β shape conductor layer 34d by the formed gases such as moisture content that in interlayer resin insulating layers 50 and core base 30, absorbed, so the insulating properties of interlayer resin insulating layers 50 and core base 30 is very high, in addition, also can prevent peeling off of interlayer resin insulating layers.Further, owing in the netted hole 35c of this chip installation area territory C, formed β shape conductor layer 34d, thus can be not uneven, and can make this chip installation area territory C planarization.
Then, the formation with regard to the multilayer board of the 3rd Change Example describes with reference to Figure 22.
Figure 22 (A) is the plane graph that is illustrated in formed flatness layer 34U on the face side of core base.Herein, in above-mentioned the 2nd embodiment with reference to Figure 18, being located in has island 36a that sets through hole and the netted hole 35b of the welding zone 60 that is connected with via hole in the C of chip installation area territory.At herein, in the 3rd Change Example, round netted hole 35d is set in the C of chip installation area territory, and in this netted hole 35d, only sets the island 36a of through hole.The interlayer resin insulating layers 50 of the 3rd Change Example and the section of core base 30 are shown in Figure 22 (B).In the 3rd Change Example, directly over the island 36a of core base 30 formed through holes 36, form via hole 60.
In the multilayer board of the 3rd Change Example, owing to be on the C of the chip installation area territory of flatness layer 34U, to form netted hole 35d, and in this netted hole 35d, set up island 36a, so can make the interlayer resin insulating layers 50 that is equipped on flatness layer 34U upper strata directly contact by means of the gap of the netted hole 35d that sets up in the periphery of this island 36a, thereby can improve cementability with the resin molding core substrate 30 that is equipped on lower floor.In addition, because can exhale by the gap of the netted hole 35d that sets up in the periphery of this island 36a by the formed gases such as moisture content that in interlayer resin insulating layers 50 and core base 30, absorbed, so the insulating properties of interlayer resin insulating layers 50 and core base 30 is very high, in addition, also can prevent peeling off of interlayer resin insulating layers.Further, owing in the netted hole 35d of this chip installation area territory C, formed island 36a, thus can be not uneven, and can make this chip installation area territory C planarization.In addition, shown in Figure 22 (C), be connected by conductor layer (cover and the electroplate) 36e that covers through hole between the island 36a that also can make through hole and the via hole 60.
[the 3rd embodiment]
Below, just multilayer build-up wiring board and the manufacture method thereof of the present invention the 3rd embodiment describe with reference to accompanying drawing.
At first, just the formation of the multilayer build-up wiring board 10 of the present invention the 3rd embodiment describes with reference to Figure 31, Figure 32 and Figure 33.Assembly shown in Figure 31 becomes the profile of the multilayer board (base plate for packaging) 10 before circuit chip 90 is installed.Shown in Figure 32 is the state profile that integrated circuit (IC) chip multilayer board 10 after 90s is installed.Shown in figure 32, at the upper face side of multilayer build-up wiring board 10 integrated circuit (IC) chip 90 is installed, and following side is connected with daughter board 94.
With reference to Figure 31 and be described in detail with regard to the formation of multilayer build-up wiring board.In this multilayer build-up wiring board 10, be to be formed with superimposed line layer 80A, 80B in the surface and the inside of multilayer film core substrate 30.This superimposed line layer 80A is by the interlayer resin insulating layers 50 that is formed with via hole 60 and conductor circuit 58a, 58b and be formed with via hole 160A, 160B and the interlayer resin insulating layers 150 of conductor circuit 158B is constituted.In addition, superimposed line layer 80B is by the interlayer resin insulating layers 50 that is formed with via hole 60 and conductor circuit 58a, 58b and be formed with via hole 160A, 160B and the interlayer resin insulating layers 150 of conductor circuit 158 is constituted.
Be equipped with solder bump 76UA, 76UB in the above on the side in order to the island 92 (with reference to Figure 32) that connects integrated circuit (IC) chip 90.On the other hand, be equipped with solder bump 76DA, 76DB below on the side in order to the island 96 (with reference to Figure 32) that connects daughter board 94.
Figure 33 (A) is the A-A cross section among Figure 31, that is the peristome plane graph of the via hole 60 that is set on the surface of interlayer resin insulating layers 50, and in addition, Figure 33 (B) is the stravismus key diagram of via hole 60.Figure 33 (C) then is the C-C cross section among Figure 31, that is the peristome plane graph of the through hole 36 that is set on the surface of core base 30, and in addition, Figure 33 (D) is the stravismus key diagram of through hole 36.In the multilayer build-up wiring board of present embodiment, via hole 60 is to be divided into 2 parts and form 2 line conductor 61a, 61b.On the other hand, through hole 36 also is divided into 2 parts and form 2 line conductor 37a, 37b, and line conductor 37a, 37b are connected with semicircular through hole island 39a, 39b respectively.This through hole island 39a, 39b then are connected in line conductor 61a, the 61b of above-mentioned via hole.
Herein, as shown in figure 31, solder bump 76UA is connected with the line conductor 37a of through hole 36 by the line conductor 61a of via hole 160A and via hole 60.Then, begin again to be connected with solder bump 76DA by this line conductor 37a by the line conductor 61a and the via hole 160A of via hole 60.Similarly, solder bump 76UB is connected with the line conductor 37b of through hole 36 by the line conductor 61b of via hole 160B and via hole 60.Then, begin again line conductor 61b by via hole 60 and via hole 160B by this line conductor 37b and be connected with solder bump 76DB.
In the 3rd embodiment, shown in Figure 33 (C), Figure 33 (D), form semicircle, and be connected with line conductor 61a, the 61b of via hole as shown in figure 31 in the formed island 39a of the opening part of through hole 36,39b.By means of such connection, can make does not have the dead angle when the internal layer welding zone is used as in the zone directly over the through hole 36.Its result can increase the number of through hole 36 by means of the raising of the configuration density that makes through hole set in multilayer film core substrate 30 36.Further, 2 line conductor 37a, 37b are set, so can on core base 30, pass through 2 times to the line conductor of through hole number because tie up on per 1 through hole 36.
In addition, owing to the via hole 60 that is set directly over this through hole 36 is made of 2 line conductor 61a and 61b, so 2 times of line conductors to via hole are passed through on interlayer resin insulating layers 50.Therefore, can seek the densification of its circuit of multilayer build-up wiring board.Further, because directly over through hole 36, be formed with via hole 60,, thereby can realize the high speed of multilayer build-up wiring board so line length shortens.
Herein, in multilayer build-up wiring board, one side will merge from the circuit of a plurality of projections in the inside, one side is connected with the projection of face side, but in the present embodiment, become 2 times by means of allowing by 1 resulting number of lines of through hole, under same pace, carry out the merging of circuit and make in table side and inboard formed superimposed line layer 90A, 90B.Therefore, can reduce in the number of plies of showing side and inboard formed superimposed line layer 90A, 90B.That is, in base plate for packaging, owing to be that one side will merge from the circuit of surface (IC chip side) a plurality of projections, one side is connected with the projection of the inside (motherboard) side, so the formed projection number of face side is more than the formed projection number of the inside side.Herein, in present embodiment, owing to can improve surface lines density, can identical (minimum) so be formed at the number of plies of table side and inboard superimposed line layer 90A, 90B.
Below other kenels of the present invention the 3rd embodiment just, do further explanation with reference to Figure 34 (A) and Figure 34 (B).
Figure 34 (A) and Figure 34 (B) are the situations that superimposed multilayer circuit board is set on single face.In Figure 34 (A), in through hole 36, insert conductor pins 230 and fixed with scolding tin 232.And inside side-line is equipped with scolding tin diaphragm 234.Conductor pins 230 utilizes insulator 230c to be divided into 2 parts in centre, and each face of conductor pins 230 is done being connected on electric with line conductor 37a, the 37b cut apart by through hole 36 respectively.This line conductor 37a, 37b are connected with line conductor 61a, the 61b of via hole 60 respectively, and this line conductor 61a, 61b then are connected with solder bump 76UA, 76UB by via hole 160A, 160B.
Figure 34 (B) forms the solder bump 76DB that connects usefulness, the example of 76DA on the opposition side of the side that superimposed multilayer line layer is set.Each solder bump 76DB, 76DA and line conductor 37a, the 37b cut apart by through hole 36 do being connected on electric.This line conductor 37a, 37b are connected with line conductor 61a, the 61b of via hole 60 respectively.This line conductor 61a, 61b then are connected with solder bump 76UA, 76UB by via hole 160A, 160B.
The holding wire of the superimposed line layer of being set up on the next comfortable core base single face can be pulled out same as before inside by means of line conductor 37a, the 37b cut apart by through hole 36, therefore the circuit degree of freedom of the inside can be improved.
Then, the manufacture method with regard to the multilayer build-up wiring board 10 of the 3rd embodiment describes with reference to Figure 24～Figure 31.
(1) the copper plate pressing plate 30A that is become with thickness 1mm and for the Copper Foil 32 by lamination 18 μ m on the two sides of glass epoxy resin or BT (span come acid anhydrides the contract imines three azines) substrate 30 that resin was constituted is as initiation material (with reference to Figure 24 (A)).At first, with this copper plate pressing plate 30A with bit bore, to form the through hole 16 (with reference to Figure 24 (B)) that through hole is used.Secondly, give the Pb catalyst and bestow the electroless plating processing afterwards again, on through hole 16, to form through hole 36 (with reference to Figure 24 (C)).
(2) will in above-mentioned (1), form substrate 30 washing and drying of the through hole 36 that is constituted by the electrolytic copper free electroplating film after, bestow redox and handle, and on the full surface of the conductor that comprises this through hole 36, set up roughened layer 20 (with reference to Figure 24 (D)).
Filler 22 (the non-conductive hole filling copper soldering paste of タ Star タ electric wire system, the trade name: the DD solder(ing) paste) utilize silk screen printing to be filled in the through hole 36, and make it dry, sclerosis (Figure 24 (E)) that (3) secondly, will contain the copper particle of average grain diameter 10 μ m.Then, to grind and remove by means of the banded sander that uses the banded pouncing paper of #600 (three are total to the physics and chemistry length of schooling) by the outstanding filler 22 in places such as roughened layer above the conductor 20 and through hole 36, and further carry out grinding the polishing grinding of caused scar in order to removal because of this band shape sander, and make the flattening surface (with reference to Figure 25 (F)) of substrate 30.
(4) and on the surface of the substrate 30 after the planarization, by means of giving palladium catalyst (ア ト テ Star Network system) and implementing electrolytic copper free electroplating and form the electroless plating film 23 that thickness is 0.6 μ m (with reference to Figure 25 (G)) through the process of above-mentioned (3).
(5) next, implementing cathode copper under the condition identical with the 1st embodiment electroplates, to form thickness is the cathode copper electroplating film 24 of 15 μ m, and forms conductor layer (as the semicircular through hole island) 26a (Figure 25 (H)) that covers on the filler 22 that is filled in the through hole 36.
(6) on the two sides that forms as the substrate 30 of the part of conductor layer 26a, stick commercially available photosensitive dry film, next mask is installed, again with 100mJ/cm 2Expose, and carry out development treatment, and form the etching protective film 25 (with reference to Figure 25 (I)) of thickness 15 μ m with 0.8% sodium carbonate.Herein, in order to cut apart this conductor layer 26a, so the slit of etching protective film 25 is set at the central part place of this conductor layer 26a.
(7) next; use the mixed liquor of sulfuric acid and hydrogen peroxide to remove the electroplating film 23 and 24 that does not form the part of etching protective film 25 with the etching dissolving; further etching protective film 25 is peeled off removal with 5%KOH again, the conductor layer 26a that covers filler 22 is cut apart to form through hole island 39a, 39b (with reference to Figure 33 (C)) and conductor circuit 34 (with reference to Figure 25 (J)).
(8) secondly, irradiation is with 2 * 10 -4The short pulse carbonic acid gas laser of second is to remove the some of the filler 22 in the through hole 36.Because through hole 36 is covered by conductor layer 26a, therefore this place promptly can be used as the mask of laser, does not cover filler 22 partly and only remove.By means of the removal of filler, the inwall of through hole conductor 36 is exposed (Figure 26 (K)).
(9) secondly, use sulfuric acid-aqueous hydrogen peroxide solution that through hole conductor 36 dissolvings of exposing are removed, and through hole 36 is divided into 2 parts, promptly obtain line conductor 37a, 37b (Figure 26 (L)).
(10) secondly, alligatoring (Figure 26 (M)) is handled by means of being implemented in employed oxidation (melanism) in (2)-reduction in the surface of through hole conductor 36 and conductor circuit 34.
(11) next, be placed in the metal mask that has formed opening in the through hole portion 36, and above-mentioned non-conductive metal welding tin cream 24 is filled in (Figure 26 (N)) within this through hole portion 36.
(12) resin filler that will be identical with the 1st embodiment is modulated the feedstock composition mixed milling of usefulness and is obtained the resin filler.After this resin filler 40 is on modulating the two sides that was coated on substrate 30 in back 24 hours with interior use cylinder spreader, the surface grinding of island 39a, the 39b of the surface of internal layer copper pattern 34 or through hole 36 there is not a resin filler 40 to remaining, then implements polishing again and grind (Figure 26 (O)).
(13) on the surface of island 39a, the 39b of conductor circuit 34 and through hole 36, be provided with identical with the 1st embodiment by acicular alloy coating and roughened layer 42 (with reference to Figure 27 (P)) that Cu-Ni-P constituted.
Further, implementing the Cu-Sn displacement reaction, is the Sn layer (not shown) of 0.3 μ m and set up thickness on the surface of roughened layer.
The feedstock composition of interlayer insulation resin agent modulation usefulness that (14) will be identical with the 1st embodiment mixes, and obtains the interlayer insulation resin agent (lower floor uses) that viscosity is adjusted into 1.5Pas.
Secondly, electroless plating that will be identical with the 1st embodiment mixes with the feedstock composition of bonding agent modulation usefulness, and obtains the electroless plating adhesive solution (upper strata is used) that viscosity is adjusted into 7Pas.
(15) on the two sides of the substrate of aforementioned (14), be coated on resulting interlayer insulation resin agent in aforementioned (7) (lower floor with) 44, next, be coated on resulting photosensitive adhesive agent solution in aforementioned (7) (upper strata is used) 46 again, carry out drying (prebake conditions), promptly forming thickness is bond layer 50 α (with reference to Figure 27 (Q)) of 35 μ m.
(16) in above-mentioned (15), formed on the two sides of substrate 30 of bond layer, the photomask (not shown) that is printed with black circle is closely bonded, and expose, develop and form the interlayer resin insulating layers (2 layers of structure) 50 (with reference to Figure 27 (R)) of the thickness 35 μ m of (the via hole formation perforate) 48 that have opening.In addition, at perforate 48 places tin electrodeposited coating (not shown) is exposed partially as via hole.
(17) impregnated in the chromic acid 19 minutes by means of the substrate 30 that will form out 48, the epoxy resin particle dissolving that is present in interlayer resin insulating layers 50 surfaces can be removed, thereby the surface of this interlayer resin insulating layers 50 of alligatoring (with reference to Figure 27 (S)).Again resulting substrate impregnated in neutralization solution (シ プ レ イ society system) after again washing thereafter.
(18) secondly, stick commercially available photosensitive dry film, load onto the mask that forms predetermined pattern, again with 100mJ/cm 2Expose, and carry out development treatment, and the electroplating film 51 (Figure 28 (T)) that opening 48 is divided into 2 parts is set with 0.8% sodium carbonate.
Further, on the surface of this substrate after the asperities processing (the alligatoring degree of depth 6 μ m), by means of giving of palladium catalyst (ア ト テ Star Network system), catalyst core is attached on the surface of interlayer resin insulating layers 50 and via hole with opening on 48 the internal face.
(19) substrate being immersed in the electrolytic copper free electroplating aqueous solution with the 1st embodiment same composition, is the electroless plating film 52 (Figure 28 (U)) of 0.6 μ m and form thickness on asperities is all.
(20) in above-mentioned (19), stick commercially available photosensitive dry film on the formed electrolytic copper free electroplating film 52, load onto the mask (not shown) that forms predetermined pattern, again with 100mJ/cm 2Expose, and carry out development treatment, and the electroplating film 54 (with reference to Figure 28 (V)) of thickness 15 μ m is set with 0.8% sodium carbonate.
(21) then, electroplate at part execution that does not form diaphragm and the cathode copper under the 1st embodiment the same terms, and the cathode copper electroplating film 56 (with reference to Figure 29 (W)) of formation thickness 15 μ m.
(22) electroplating film 51,54 is peeled off removal with 5%KOH after; again the electrolytic copper free electroplating film 52 under the electroplating film 54 is implemented etch processes and dissolved removal with the mixed liquor of sulfuric acid and hydrogen peroxide; formation is conductor circuit 58,58a, the 58b of 18 μ m and the via hole 60 that is made of 2 line conductors 61a, 61b by the thickness that electrolytic copper free electroplating film 52 and cathode copper electroplating film 56 are constituted, and also has not divided via hole 60 ' (Figure 29 (X)) of formation.
(23) carry out processing with (13) same steps as, and in conductor circuit 58,58a, 58b and via hole 60,60 ' the surface on form the alligatoring face 62 that constitutes by Cu-Ni-P, and further implement Sn displacement (with reference to Figure 29 (Y)) in its surface.
(24), further after the interlayer resin insulating layers 150 that forms the upper strata, forming conductor circuit 158 and via hole 160A, 160B again, and obtain Mulitilayer circuit board (with reference to Figure 30 (ZA)) by means of the process of repeatable operation above-mentioned (14)～(23).Yet formed alligatoring face 62 does not carry out the Sn displacement on the surface of this conductor circuit 158 and via hole 160A, 160B.
(25) in above-mentioned (24) on the two sides of resulting substrate 30, the scolding tin diaphragm composition that is illustrated among the above-mentioned D. is coated with the thickness of 20 μ m.Expose, development treatment, and partly (comprise via hole and island thereof partly) and form scolding tin protective film (thickness 20 μ m) 70 (with reference to Figure 30 (ZB)) of (the opening footpath 200 μ m) 71 that have opening at the scolding tin welding zone.Further, form reinforced layer 78 on the upper strata of scolding tin protective film 70.
(26) secondly, forming thickness on the peristome 71 of scolding tin protective film 70 is the nickel electrodeposited coating 72 of 5 μ m.Further, by means of the golden electrodeposited coating 74 that on nickel electrodeposited coating 72, forms thickness 0.03 μ m, and on via hole 160A, 160B and conductor circuit 158, form scolding tin welding zone 75 (with reference to Figure 30 (ZC)).
(27) then, carry out melting welding again and form solder bump (scolding tin body) 76UA, 76UB, 76DA, 76DB, promptly finish the manufacturing (with reference to Figure 31) of multilayer board 10 by means of printed solder paste on the peristome 71 of scolding tin protective film 70 and with 200 ℃.
Continue, just installation I C chip and the operation that is installed on daughter board 94 describe with reference to Figure 32 on this multilayer board 10.Mode with the scolding tin welding zone 92 of corresponding IC chip 90 on solder bump 76UA, the 76UB of completed multilayer board 10 is installed IC chip 90, and carries out melting welding again to load onto IC chip 90.Similarly, by means of melting welding again and daughter board 94 is loaded onto in solder bump 76DA, the 76DB place of multilayer build-up wiring board 10.
Then, just the multilayer build-up wiring board of the 1st Change Example of the present invention the 3rd embodiment describes with reference to Figure 35.Be the formation profile of the multilayer build-up wiring board of the 1st Change Example shown in Figure 35 (A), and Figure 35 (B) is the plane graph in order to the shape on through hole 139 that this multilayer build-up wiring board is described and island 260.
Shown in Figure 35 (B), the through hole island 139 of through hole 136 is to form with circle, and additional respectively welding zone 137A, the 137B that has via hole to connect usefulness.On this welding zone 137A, 137B line conductor 260a, the 260b that is equipped with the via hole 260 that is divided into 2 parts respectively.Then, this line conductor 260a is connected with the welding zone 258A that is used for being connected with the via hole 360 on upper strata by conductor circuit 258.Similarly, line conductor 260b is connected with the welding zone 258B that is used for being connected with the via hole 360 on upper strata by conductor circuit 258.
In the formation of the 1st Change Example, improve the line density that is positioned at interlayer resin insulating layers 350 places that are equipped with this via hole 260 by means of cutting apart via hole 260.
In addition, the via hole of multilayer build-up wiring board and through hole are divided into 2 parts and set up the example of line conductor, then can further improve line density if can be divided into more than 3 parts though in the 3rd above-mentioned embodiment, disclosed.
In the multilayer build-up wiring board of the 3rd embodiment as described above, because 1 via hole is made of a plurality of line conductor, therefore the line conductor that is several times as much as via hole is passed through on interlayer resin insulating layers, so can seek the densification of multilayer build-up wiring board circuit.
[the 4th embodiment]
Figure 36 is an embodiment mode sectional drawing of the circuit substrate of the 4th embodiment.
In the circuit substrate of the 4th embodiment, on insulated substrate 221, form first metal film 222 that constitutes by thick film, and on this first metal film 222, form second metal film 223 thinner than first metal film 222, and the side of this second metal film 223 is more side-prominent more outward than the side of above-mentioned first metal film 222.In addition, as shown in figure 36, when forming the resin insulating barrier 224 of conductor layer covering that will two layers of above-mentioned structure, the effect of the 4th embodiment just can be brought into play.
Material with insulated substrate 221 is not limited especially, and the substrate that inorganic material constituted of the pottery of can serving as reasons etc. also can be the substrate that organic material constituted by resin etc.
In addition, also can under the conductor layer of two layers of above-mentioned structure or on form other metal film, and in order to improve the closely bonding property with the insulation resin interlayer, also can utilize and wait the form that material covers and form the roughened layer that constitutes by other metal films above-mentioned.
Further, also the conductor layer and the wherein one deck among the resin insulating barrier of constructing as shown in figure 36 can be repeated to form.
Formation method with two layers of above-mentioned structure conductor layer is not limited especially, for example, can enumerate method shown below.
(1) first method
On the substrate that constitutes by pottery etc. or implementing form electroplating film on the resin insulating barrier etc. of roughening treatment after, partly go up in the not formation of electroplating film and to form first metal film 222 and second metal film 223.
Then; after removing electroplating film; but, can form by two layers of conductor layer that structure is constituted of shape as shown in figure 36 by means of using the etching solution to be easier to etch away second metal film 223 that first metal film 222 can etch into hardly to carry out etching.
For example, use the material of copper, use the material of nickel as second metal film 223 as first metal film 222, and by means of the mixed liquor that uses sulfuric acid and hydrogen peroxide as etching solution, can form the film of above-mentioned structure.
This method is an employed method in the manufacture method of the multilayer build-up wiring board of following the 4th embodiment.
(2) second methods
As shown in figure 37, at first on insulated substrate 231 grades, form first electroplating film 232 (with reference to Figure 37 (A)).
The formation of first electroplating film 232 can use general photoetching method to carry out.
Secondly, in the not formation portion of first electroplating film 232, form first metal film 233 (with reference to Figure 37 (B)).The person is preferable because this first metal film 233 thinks the thick film, so so that form preferable with metallide.In addition, its thickness is preferable with the rough identical person of the thickness of first electroplating film 232.
Then; after bestowing the processing (absorption of roughening treatment or catalyst core) that metal can form at an easy rate on the surface of first electroplating film 232, second electroplating film 234 is formed (with reference to Figure 37 (C)) with the little area in formation zone than first electroplating film 232.
Afterwards, second metal film 235 is formed (with reference to Figure 37 (D)) to be filled in by the mode in 234 depressed parts that form of second electroplating film.
Because second metal film 235 must form on first electroplating film 232 under the situation that does not cover second electroplating film 234, so to use electroless plating preferable.
Afterwards, by means of electroplating film is removed, can form the conductor layer (with reference to Figure 37 (E)) of two layers of structure that constituted by first metal film 233 and second metal film 235.
Secondly, the multilayer build-up wiring board with regard to the 4th embodiment describes.
The multilayer build-up wiring board of the 4th embodiment, be a kind ofly to have the multilayer build-up wiring board of formed structure more than 1 layer by resin insulating barrier and conductor circuit respectively on the resin substrate, it is characterized in that: at least 1 series of strata of above-mentioned conductor circuit are to be included in two layers of structure conductor layer that the second thin metal film of above-mentioned first metal film of the first metal film upper strata pressure ratio constitutes, and it is more side-prominent more outward than the side of above-mentioned first metal film to constitute the side of second metal film of above-mentioned conductor layer.
If words according to the formation of the 4th embodiment, because the side of formed second metal film is more side-prominent more outward than the side of above-mentioned first metal film on above-mentioned first metal film, even so under situation such as caused that because of the structure of this overhang temperature changes, stress also can not concentrate on the bight of above-mentioned conductor layer, and the result can prevent to produce the crack on above-mentioned resin insulating barrier.
In the multilayer build-up wiring board of the 4th embodiment, be to use the substrate that on resin substrate, directly forms conductor circuit to be used as resin substrate, 1 layer resin insulating barrier and conductor circuit can be set individually thereon, also can be provided with more than 2 layers.Further, above-mentioned resin insulating barrier and above-mentioned conductor circuit can be arranged on the single face of resin substrate, also can be arranged on the two sides.
Below, the manufacture method of the multilayer build-up wiring board of the 4th embodiment is described as one of multilayer build-up wiring board example.
(1) at first, be produced on the circuit substrate that has lower floor's conductor circuit on the surface of resin substrate.
At this moment, after forming etching protective film on the Copper Foil, use mixed liquor or the etching solutions that the aqueous solution constituted such as sodium peroxydisulfate, ammonium persulfate to carry out etching, and form lower floor's conductor circuit by sulfuric acid and hydrogen peroxide.
In addition, on this resin substrate, utilize drill bit to wear through hole, and on the wall of this through hole and copper foil surface, bestow electroless plating and form through hole.Electroless plating is then electroplated preferable with copper.
Further, also can implement the energising plating in order to make Copper Foil can produce thick lining.This energising is electroplated and is electroplated preferable with copper.
In addition, after energising is electroplated, also through hole inwall and energising electroplating film surface can be implemented roughening treatment.With coarsing processing method, can give an example and handle as: melanism (oxidation); Use the hydro-peening of the organic acid and the second copper complex formazan mixed aqueous solution to handle; And with the processing of electroplating by the Cu-Ni-P acicular alloy etc.
In addition, in case of necessity can be corresponding in through hole the filled conductive solder(ing) paste, the conductor layer that covers this conduction solder(ing) paste then can utilize electroless plating or energising plating to form.
(3) secondly, be provided with on the established interlayer resin insulating layers in order to guarantee with the lower floor conductor circuit between the electric via hole perforate that is connected.
When stating electroless plating in the use and using bonding agent, can set up the via hole perforate by means of the execution thermmohardening in exposure, after developing.
In addition, when using thermosetting resin, after thermmohardening, can on above-mentioned interlayer resin insulating layers, set up the via hole perforate by means of laser processing.
(4) secondly, with above-mentioned interlayer resin insulating layers alligatoring.When stating electroless plating in the use and using bonding agent, can will be present in acid or oxidant, removing of above-mentioned interlayer resin insulating layers surface, and finish the alligatoring of electroless plating with adhesive surface for the resin particle utilization acid of solubility or oxidant dissolving.
(5) next, give catalyst core through on the circuit substrate of alligatoring on the interlayer resin insulating layers surface.
In the giving of catalyst core,, generally speaking use palladium bichloride or palladium colloid etc. to use precious metal ion or precious metal colloid etc. preferable.In addition, be preferable for fixed catalyst nuclear and to implement heat treated.With above-mentioned catalyst core, then preferable with palladium.
(6) next, on the surface of the interlayer resin insulating layers of giving catalyst core, bestow electroless plating, on alligatoring face is comprehensive, to form the electroless plating film.The thickness of electroless plating film is preferable with 0.5～5 μ m courage.
Secondly, on the electroless plating film, form electroplating film.
(7) secondly, in the not formation portion of electroplating film, bestow the energising of 5～20 μ m thickness and electroplate, and form top conductor circuit and via hole.
After energising is electroplated, electroplate and formation nickel electroplating film by means of no electrolytic nickel more again.On above-mentioned nickel electroplating film, can be easy to separate out by the alloy plating that Cu-Ni-P constituted.In addition because the nickel electroplating film has the effect that can be used as metal protective film, so can prevent after etching work procedure in overetched situation generation is arranged.
Herein, with regard to above-mentioned energising is electroplated, preferable to use copper to electroplate.
(8) secondly; after removing electroplating film; to remove the substrate of electroplating film by means of implementing etching in the mixed liquor that impregnated in sulfuric acid and hydrogen peroxide or the aqueous solution such as sodium peroxydisulfate, ammonium persulfate; remove with the electroless plating film that will be present under this electroplating film, and become independently top conductor circuit.
At this moment, particularly when using the mixed liquor of sulfuric acid and hydrogen peroxide, because no electrolytic nickel electroplating film can be not etched, the copper electroplating film then can be etched a little, so can form the conductor layer of two layers of side-prominent outward structure of the side of the side ratio energising copper electroplating film with no electrolytic nickel electroplating film.
(9) next, the substrate of removing oxide-film be impregnated in the electroplate liquid, on above-mentioned top conductor circuit, form the Cu-Ni-P alloy roughened layer of porous matter.At this moment because Cu-Ni-P alloy roughened layer is easy to separate out on the nickel electroplating film, so the bight become near curved surface, so even expand at conductor layer, stress also is difficult for concentrated when shrinking.
(10) secondly, on this substrate, form electroless plating for example with the layer of bonding agent to be used as interlayer resin insulating layers.
(11) further, the operation of repeatable operation above-mentioned (3)～(9) and set up on the upper strata layer conductor circuit is to obtain 6 layers of two sides multilayer build-up wiring board of 3 layers of single faces for example.
Below, describe with reference to accompanying drawing with regard to the 4th embodiment.
B. the manufacture method of multilayer build-up wiring board
(1) the copper plate pressing plate that is become with thickness 1mm and for the Copper Foil 32 by lamination 18 μ m on the two sides of glass epoxy resin or BT (span come acid anhydrides the contract imines three azines) substrate 30 that resin was constituted is as parent material (with reference to Figure 38 (A)).At first; with this copper plate pressing plate with bit bore; continue to form after the electroplating film; on this substrate, form through hole 36 by means of bestowing the electroless plating processing; further,, the foundation conventional method on the two sides of substrate, forms inner conductor circuit 32 by means of carrying out etching according to pattern form.
Secondly, after forming the substrate washing and drying of inner conductor circuit 32, through implementing to use NaOH (10g/l), NaC 1O 2(40g/l) and Na 3PO 4The aqueous solution (6g/l) is handled as the oxidation bath of oxidation bath (melanism bath), and forms alligatoring face 38 (with reference to Figure 38 (B)) on the full surface of the inner conductor circuit 34 that comprises this through hole 36.
(2), being filled in resin filler 40 between the inner conductor circuit 34 or within the through hole 36, and carry out heat drying by means of will utilizing printing machine to be coated on the two sides of substrate as the resin filler 40 of principal component with epoxy resin.That is, make resin filler 40 be filled between the inner conductor circuit 34 or (with reference to Figure 38 (C)) within the through hole 36 by means of this operation.
(3) will implement grinding through the substrate 30 that above-mentioned (2) dispose, and then polish research.Then, make resin filler 40 heat hardenings (with reference to Figure 38 (D)) of filling.
(4) further again, on the island of inner conductor circuit 34 that exposes and through hole 36, similarly form the porous matter alloy roughened layer 42 that constitutes by Cu-Ni-P that thickness is 2 μ m, and the Sn layer (with reference to Figure 39 (A)) of thickness 0.05 μ m further is set on the surface of this roughened layer 42 with the 1st embodiment.But the Sn layer is not shown.
(5) electroless plating that will be identical with the 1st embodiment on the two sides of substrate uses cylinder spreader coating 2 times with bonding agent, and after under level, placing 20 minutes, in 60 ℃ of down dry 30 minutes (with reference to Figure 39 (B)).
(6) implement exposure on the substrate of the layer of bonding agent, develop and form and have perforate (via hole with perforate 48) and thickness is the interlayer resin insulating layers 50 (50a, 50b) (with reference to Figure 39 (C)) of 18 μ m having formed electroless plating among above-mentioned (5).
(7) will form via hole and use the substrate of perforate 48 in chromic acid aqueous solution (700g/l), to flood 20 minutes down, remove and alligatoring its surface and the alligatoring face of obtaining with the epoxy resin particle dissolving that will be present in interlayer resin insulating layers 50 the insides in 73 ℃.Again resulting substrate impregnated in neutralization solution (シ プ レ イ society system) after again washing (with reference to Figure 39 (D)) thereafter.
Further, on this substrate surface after the asperities processing, by means of giving of palladium catalyst (ア ト テ Star Network system), catalyst core is attached on the surface of layer insulation material layer 50 or via hole with on the internal face of perforate 48.
(8) next, substrate being immersed in the electrolytic copper free electroplating aqueous solution of composition as shown below, is the electroless plating film 52 (with reference to Figure 40 (A)) of 0.8 μ m and form thickness on asperities is all.
[the electroless plating aqueous solution]
EDTA 60g/l
Copper sulphate 10g/l
HCHO 6ml/l
NaOH 10g/l
α, α '-bipyridyl 80mg/l
Poly-diethanol (PEG) 0.1g/l
[electroless plating condition]
Following 20 minutes of the liquid that temperature is 60 ℃
(9) on electrolytic copper free electroplating film 52, stick commercially available photosensitive dry film, next mask is installed, again 100mJ/cm 2Expose, and carry out development treatment, and set up electroplating film 54 (with reference to Figure 40 (B)) with 0.8% sodium carbonate.
(10) next, under the condition identical, implement energising copper and electroplate with the 1st embodiment, and the energising copper electroplating film 56 of formation thickness 13 μ m.
(11) secondly, this substrate 30 be impregnated in the no electrolytic nickel electroplating bath that is made of the aqueous solution (90 ℃) of nickel chloride (30g/l), inferior sodium phosphate (10g/l) and natrium citricum (10g/l), and on energising copper electroplating film, form the nickel electrodeposited coating 57 (with reference to Figure 40 (C)) of thickness 1.2 μ m.
(12) electroplating film 54 is peeled off removal with 5%KOH after; again this substrate be impregnated in by in the etching solution that mixed liquor constituted of sulfuric acid and hydrogen peroxide so that electrolytic copper free electroplating film 52 etchings under the electroplating film are removed, and form the top conductor circuit 58 (comprising via hole 60) (with reference to Figure 40 (D)) that the L/S=28/28 that is made of electrolytic copper free electroplating film 52, cathode copper electroplating film 56 and nickel film 57 and thickness are 11 μ m.
(13) then, the oxide-film on the nickel film is used after the hydrochloric acid removal of 18 weight %, implement and above-mentioned (4) identical processing, on the surface of top conductor circuit 58, to form the Cu-Ni-P alloy roughened layer 42 of thickness 2 μ m.
(14) continue; operation by means of repeatable operation above-mentioned (5)～(13); with layer conductor circuit 158, via hole 160 and roughened layer 42 on the further formation upper strata; and in the end carry out after the formation of scolding tin protective film 70, nickel electroplating film 72 and golden electroplating film 74 that complete has opening; form solder bump 76 again, and obtain having the multilayer build-up wiring board (with reference to Figure 41 (A)～Figure 42 (C)) of solder bump 18.
(the 2nd comparative example)
Do not implement the operation of (11) among above-mentioned the 4th embodiment, promptly except not forming the nickel film, all the other steps are all identical with the 4th embodiment and make a multilayer build-up wiring board.
At resulting multilayer build-up wiring board in above-mentioned the 4th embodiment and the 2nd comparative example, it is cooled to repeatedly be heated to again after-55 ℃ 125 ℃ thermal cycling test 1000 times, and after test, utilize fret saw to cut off multilayer build-up wiring board, the section of conductor circuit and interlayer resin insulating layers is observed with light microscope.
As a result, the crack does not take place fully in the resulting multilayer build-up wiring board in the 4th embodiment, resulting multilayer build-up wiring board then produces the crack that is derived from bights such as conductor circuit 58 in interlayer resin insulating layers in the 2nd comparative example.
At its optical microscope photograph of section of resulting multilayer build-up wiring board among the 4th embodiment as Figure 43 (A) and (B).
Section by the conductor circuit shown in Figure 43 can obviously be found out, the side of the energising electroplating film 56 of formation top conductor circuit 58 is more side-prominent more outward than the side of nickel film 57, therefore result from the structure of this top conductor circuit 58 if infer, stress also can not concentrate on the bight of conductor circuit 58, and the result can prevent to produce the crack on interlayer resin insulating layers 50.
As discussed above, if the words of the circuit substrate of foundation the 4th embodiment, because it is more side-prominent more outward than the side of above-mentioned first metal film to be used for constituting the side of second metal film of conductor layer of two layers of structure, thereby when being to form resin insulating barrier on the conductor layer such as above-mentioned, even under situation such as caused that because of the structure of this overhang temperature changes, stress also can not concentrate on the bight of above-mentioned conductor layer, and the result can prevent to produce the crack on above-mentioned resin insulating barrier.
In addition, if the words of the multilayer build-up wiring board of foundation the 4th embodiment, because it is more side-prominent more outward than the side of above-mentioned first metal film to be used for constituting the side of second metal film of conductor layer of two layers of structure, thereby in situation such as the structure owing to this overhang has caused that temperature changes following time, stress also can not concentrate on the bight of above-mentioned conductor layer, and the result can prevent to produce the crack on above-mentioned resin insulating barrier.

Claims (6)

1. multilayer build-up wiring board, this circuit board system is interlayer resin insulating layers and conductor layer lamination alternatively, and the multilayer line layer that is connected with the via hole that the end is arranged between each conductor layer is formed on the core base constituted, and it is characterized in that:
The peristome system of above-mentioned 1 via hole utilizes a plurality of line conductor to form,
Above-mentioned a plurality of line conductor is electrically connected with other line conductor respectively.
2. multilayer build-up wiring board, this circuit board system is interlayer resin insulating layers and conductor layer lamination alternatively, and the multilayer line layer that is connected with the via hole that the end is arranged between each conductor layer is formed on the core base, it is characterized in that:
The peristome system of above-mentioned 1 via hole utilizes 2 line conductors to form,
Above-mentioned 2 line conductors are electrically connected with other line conductor respectively.
3. multilayer build-up wiring board, this circuit board system is with interlayer resin insulating layers and conductor layer lamination alternatively, and the multilayer line layer that is connected with the via hole that the end is arranged between each conductor layer is formed on the core base, above-mentioned conductor layer is done electric being connected by means of formed through hole on core base with the conductor layer of this core base the inside side, it is characterized in that:
On 1 through hole of above-mentioned core base, set a plurality of line conductors; And
On setting directly over 1 through hole of above-mentioned a plurality of line conductors, set the peristome that is connected with above-mentioned each line conductor respectively by the via hole that a plurality of line conductor constituted,
Above-mentioned peristome is by a plurality of line conductors in the via hole that a plurality of line conductor constituted, and the line conductor with other is electrically connected respectively.
4. multilayer build-up wiring board, this circuit board system is with interlayer resin insulating layers and conductor layer lamination alternatively, and the multilayer line layer that is connected with the via hole that the end is arranged between each conductor layer is formed on the two sides of core base, the conductor layer on above-mentioned core base two sides is done electric connection by means of formed through hole on core base to each other, it is characterized in that:
On 1 through hole of above-mentioned core base, set a plurality of line conductors; And
On setting directly over 1 through hole of above-mentioned a plurality of line conductors, set the peristome that is connected with above-mentioned each line conductor respectively by the via hole that a plurality of line conductor constituted,
Above-mentioned peristome is by a plurality of line conductors in the via hole that a plurality of line conductor constituted, and the line conductor with other is electrically connected respectively.
5. multilayer build-up wiring board, this circuit board system is with interlayer resin insulating layers and conductor layer lamination alternatively, and the multilayer line layer that is connected with the via hole that the end is arranged between each conductor layer is formed on the two sides of core base, the conductor layer on above-mentioned core base two sides is to do electric connection by means of formed through hole on core base to each other, it is characterized in that:
In 1 through hole of above-mentioned core base, filled, formed the conductor layer that exposes face that has covered from this filler through hole simultaneously with filler;
This through hole and this conductor series of strata are repeatedly cut apart; And
On directly over 1 through hole that is covered by above-mentioned divided conductor layer, set the peristome that is connected with this divided conductor layer respectively by the via hole that a plurality of line conductor constituted,
Above-mentioned peristome is by a plurality of line conductors in the via hole that a plurality of line conductor constituted, and the line conductor with other is electrically connected respectively.
6. the described multilayer build-up wiring board of claim 5 is characterized in that:
The above-mentioned conductor layer of cutting apart forms by partially-etched processing.
CN2008100810380A 1998-09-17 1999-09-08 Multilayer build-up wiring board Expired - Lifetime CN101267717B (en)

Applications Claiming Priority (8)

Application Number Priority Date Filing Date Title
JP283437/1998 1998-09-17
JP28343798A JP4127433B2 (en) 1998-09-17 1998-09-17 Multilayer buildup wiring board and method for manufacturing multilayer buildup wiring board
JP324535/1998 1998-10-28
JP32453598A JP2000133941A (en) 1998-10-28 1998-10-28 Multilayer build-up wiring board
JP362961/1998 1998-12-21
JP36296198A JP2000188447A (en) 1998-12-21 1998-12-21 Wiring board and printed wiring board
JP00031599A JP4127440B2 (en) 1999-01-05 1999-01-05 Multilayer build-up wiring board
JP315/1999 1999-01-05

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
CN99811085A Division CN1318274A (en) 1998-09-17 1999-09-08 Multilayer build-up wiring board

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CN101267717A CN101267717A (en) 2008-09-17
CN101267717B true CN101267717B (en) 2011-03-30

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CN2008100810361A Expired - Lifetime CN101267715B (en) 1998-09-17 1999-09-08 Multilayer build-up wiring board
CN2008100810376A Expired - Lifetime CN101267716B (en) 1998-09-17 1999-09-08 Multilayer build-up wiring board

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CN2008100810376A Expired - Lifetime CN101267716B (en) 1998-09-17 1999-09-08 Multilayer build-up wiring board

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CN101267715B (en) 2010-10-13
CN101267717A (en) 2008-09-17
JP2000101247A (en) 2000-04-07
CN101267716B (en) 2010-08-25
CN101267716A (en) 2008-09-17
JP4127433B2 (en) 2008-07-30

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