CN101266966B - Multi-chip package module and manufacturing method thereof - Google Patents

Abstract

A multi-chip package module includes a first substrate, a first chip, a first semiconductor element, a first sealant, and a second semiconductor element. The first chip is disposed on the first substrate. A first semiconductor element that is flipped is disposed over the first chip. The first encapsulant encapsulates the first chip and the first semiconductor element, and the first encapsulant has an opening to expose a portion of the first semiconductor element. The bottom surface of the second semiconductor element is provided with a plurality of first conductive bumps, the second semiconductor element is arranged on the first semiconductor element and positioned in the opening, and the second semiconductor element is electrically connected with the first semiconductor element through the first conductive bumps.

Description

Multi-chip package module and manufacturing method thereof

technical field

The invention relates to a packaging module and a manufacturing method thereof, in particular to a multi-chip packaging module and a manufacturing method thereof.

Background technique

The goals of the current computer industry include higher performance, lower cost, smaller body, and greater packaging density of integrated circuits (IC). With the advent of a new generation of integrated circuit products, the functions of the new products are more powerful but the number of components required is reduced.

Semiconductor devices are constructed from silicon or gallium arsenide wafers through a series of procedures such as deposition, lithography, diffusion, etching, and implantation. Often many individual devices are fabricated from the same wafer. When these devices are cut into individual rectangular units, each becomes an integrated circuit die (IC die). To form an interface between the chip and other circuitry, the chip is typically placed on a lead frame or a substrate surrounded by many pins. Each chip has pads for bonding, which allow very thin gold or aluminum wires to be connected to the pins of the lead frame during the wire-bonding process, or for flip-chip Chip bonding.

Flip chip attachment (flipped chip attachment) is to connect a flip chip (hereinafter referred to as flip chip) to a circuit board or another substrate. A flip chip has a bonding surface consisting of a surrounding wiring pattern or array of terminals for flip chipping onto a substrate. In general, the bonding surface of a flip chip usually has one of the following electrical connectors: a ball grid array (BGA) or a carrier slightly larger than the chip (SLICC). A ball gate array (BGA) is an electrical connection structure with an array of tiny solder balls disposed on the bonding surface of a flip chip for bonding to a substrate. A slightly larger chip carrier (SLICC) is similar to a ball gate array, but with smaller ball diameters and pitches.

In the case of a ball gate array (BGA) or a carrier slightly larger than a chip (SLICC), the configuration of solder balls or other conductive balls must be the mirror image of the pads connected to them on the circuit board, so that the solder balls Only then can it be accurately connected to the pad. By reflowing solder balls, the flip chip and the circuit board can be connected together. Solder balls can also be replaced with conductive polymer or gold bumps.

In the initial stage of wire bonding and TAB attachment, the semiconductor chip is usually pasted on the surface of the small circuit board with a suitable adhesive (such as epoxy resin). In the case of wire bonding, the conductors are then extended one at a time from the respective bonding pads on the semiconductor chip to corresponding metal pins or wire ends on the circuit board. In the case of flexible tape bonding, the two ends of the metal pins carried on the insulating flexible tape are respectively bonded to the bonding pads on the semiconductor chip and the corresponding metal pins or wire ends on the circuit board. Finally, sealant is used to cover the wires and the metal pins on the soft tape to prevent injury and contamination.

However, under the requirements of limited pin count, thinner body, lighter weight and lower cost, portable electronic products such as mobile phones, laptop computers or other consumer products require more semiconductors features and better performance. Such demands force the industry to actively integrate semiconductor chips with individual functions in order to meet the above-mentioned requirements.

Contents of the invention

The purpose of the present invention is to provide a multi-chip packaging module and its manufacturing method, in which a plurality of chips can be arranged, so that the function of the module is powerful and complete, and an optimized system can be created in the module.

To achieve the above object, the present invention provides a multi-chip package module including a first substrate, a first chip, a first semiconductor element, a first encapsulant, and a second semiconductor element. The first chip is arranged on the first substrate. The flip-chip first semiconductor element is arranged above the first chip. The first encapsulant covers the first chip and the first semiconductor element, and the first encapsulant has an opening to expose part of the first semiconductor element. The bottom surface of the second semiconductor element is provided with a plurality of first conductive bumps, the second semiconductor element is arranged on the first semiconductor element and is located in the opening, and the second semiconductor element passes through these first conductive bumps and the first semiconductor element electrical connection.

According to the purpose of the present invention, a method for manufacturing a multi-chip package module is proposed, comprising the following steps: (a) providing a first substrate; (b) setting the first chip on the first substrate; (c) placing the first The semiconductor element is flip-chip mounted on the first chip; (d) electrically connecting the first chip and the first semiconductor element to the first substrate; (e) sealing the first chip and the first semiconductor element with a sealant , but forming an opening on the first semiconductor element to expose part of the first semiconductor element; and (f) soldering a plurality of first conductive bumps of the second semiconductor element to the first semiconductor element, so that the second semiconductor element is set on the first semiconductor element and in the opening.

Compared with the prior art, the multi-chip packaging module and its manufacturing method of the present invention have several advantages. Since more chips can be arranged in the package module, the volume of the package can be further reduced, and the package has better performance. The second semiconductor device with multiple functions can be combined into a multi-chip package module to expand and diversify its functions. In addition, since the second semiconductor element with specific functions can be assembled on the pre-assembled semi-finished package with basic functions as soon as the customer places an order, multi-chip package modules with specific functions can be manufactured more quickly come out. In this way, traditionally, a large and complex circuit design must be used to implement a fully functional module. The present invention only needs to use flexible design and combine different functional chips to make the packaged module have complete functions and better performance. The manufacturing process can be accelerated and simplified at the same time.

The present invention will be further described below in conjunction with the accompanying drawings and embodiments.

Description of drawings

FIG. 1 is a cross-sectional view of a multi-chip package module according to a first embodiment of the present invention.

2A-2E are schematic views of the manufacturing method of the multi-chip packaging module of FIG. 1 .

3 is a cross-sectional view of a multi-chip package module according to a second embodiment of the present invention.

4A-4E are schematic views of the manufacturing method of the multi-chip packaging module shown in FIG. 3 .

FIG. 5 is a cross-sectional view of a multi-chip package module according to a third embodiment of the present invention.

6A-6D are schematic diagrams of the manufacturing method of the multi-chip packaging module shown in FIG. 5 .

Detailed ways

The top surface of the multi-chip packaging module of the present invention includes a flip-chip semiconductor element, and part of the substrate is exposed for another semiconductor element to be disposed on. The present invention utilizes such a method to gather multiple chips in a single packaging module.

Relevant detailed description and technical contents of the present invention are as follows now in conjunction with the accompanying drawings:

first embodiment

FIG. 1 is a cross-sectional view of a multi-chip package module according to a first embodiment of the present invention. The multi-chip packaging module 100 of this embodiment includes a substrate 110 , a chip 120 , a first semiconductor element 140 , a sealant 150 and a second semiconductor element 160 . The chip 120 is disposed on the substrate 110 . Preferably, a plurality of conductive bumps 122 of the chip 120 are soldered to the substrate 110 for electrically connecting the chip 120 and the substrate 110 . The flip-chip first semiconductor element 140 is disposed above the chip 120 . The encapsulant 150 covers the chip 120 and the first semiconductor element 140 , and the encapsulant 150 has an opening 155 exposing part of the first semiconductor element 140 . Several conductive bumps 168 are disposed on the bottom surface of the second semiconductor element 160 , and the second semiconductor element 160 is disposed on the first semiconductor element 140 and located in the opening 155 . The second semiconductor device 160 is electrically connected to the first semiconductor device 140 through a plurality of conductive bumps 168 .

The semiconductor device may be a subpackage, that is, including at least one chip disposed on a substrate. For example, the first semiconductor device 140 is a sub-package, at least including a substrate 142 , a chip 144 and an encapsulant 148 . The substrate 142 is disposed over the chip 120 . The chip 144 is disposed on the substrate 142 and is electrically connected to the substrate 142 , for example, by wire bonding. The encapsulant 148 covers the chip 144 and the substrate 142 . The first semiconductor element 140 is disposed on the chip 120 with its bottom facing up, and the opening 155 of the encapsulant 150 exposes part of the substrate 142 . As shown in FIG. 1 , the first semiconductor device 140 preferably carries another chip 146 or more chips to extend the function of the package 100 . In addition, the second semiconductor element 160 is also preferably a sub-package, which at least includes a substrate 162 , a chip 164 and an encapsulant 166 . A plurality of conductive bumps 168 are disposed on the bottom surface of the substrate 162 . The chip 164 is disposed on the top surface of the substrate 162 and is electrically connected to the substrate 162 by, for example, wire bonding. The encapsulant 166 covers the chip 164 and the substrate 162 . Although the detailed structure of the first semiconductor device 140 and the second semiconductor device 160 is clearly disclosed in FIG. 1 , the structure of the semiconductor device in the multi-chip package module 100 is not limited thereto. For example, the first semiconductor device 140 may only include a single chip, while the second semiconductor device 160 may include two chips.

Furthermore, another chip can be disposed on the chip 120 and wire-bonded to the substrate 110 . Therefore, more chips can be arranged in the multi-chip packaging module 100, so that the system functions in the module are more powerful and complete.

The space between the first semiconductor element 140 and the second semiconductor element 160 is preferably filled with an underfill material 169 . A plurality of solder balls 105 are disposed on the bottom surface of the substrate 110 for electrically connecting another substrate or circuit board.

2A-2E are schematic views of the manufacturing method of the multi-chip package module according to FIG. 1 . The manufacturing method of the chip package module in this embodiment includes the following steps: firstly, a substrate 110 is provided, and the chip 120 is disposed on the substrate 110 by soldering conductive bumps 122 , as shown in FIG. 2A . Then, the first semiconductor element 140 is flipped and disposed on the chip 120, as shown in FIG. 2B. The chip 120 and the first semiconductor element 140 are electrically connected to the substrate 110 through the conductive bump 122 and the wire 149 respectively. Next, the chip 120 and the first semiconductor element 140 are sealed with an encapsulant 150 , but an opening 155 is formed on the first semiconductor element 140 to expose part of the first semiconductor element 140 , as shown in FIG. 2C . Afterwards, the plurality of conductive bumps 168 of the second semiconductor element 160 are soldered to the first semiconductor element 10 , so that the second semiconductor element 160 is disposed on the first semiconductor element 140 and located in the opening 155 , as shown in FIG. 2D . Finally, the underfill material 169 is filled between the first semiconductor element 140 and the second semiconductor element 160 , and several solder balls 105 are disposed on the bottom surface of the substrate 110 , as shown in FIG. 2E . The second semiconductor device with multiple functions can be combined into the multi-chip package module 100 to expand and diversify its functions. In addition, since the second semiconductor element with a specific function can be assembled on the pre-assembled semi-finished package with basic functions as soon as the customer places an order, multi-chip package modules with specific functions can be manufactured more quickly come out.

second embodiment

3 is a cross-sectional view of a multi-chip package module according to a second embodiment of the present invention. The only difference between this embodiment and the above-mentioned embodiments lies in the chip 120, the substrate 110 and their connection methods. These differences will be described in detail in the following paragraphs, and the same components retain the original reference numbers, so they will not be described again.

Please refer to FIG. 3 , the multi-chip packaging module 200 of this embodiment includes a substrate 110 , a chip 120 , a first semiconductor element 140 , a sealant 150 and a second semiconductor element 160 . The chip 120 is disposed on the substrate 110 , preferably a plurality of wires 222 of the chip 120 are electrically connected to the chip 120 and the substrate 110 . The flip-chip first semiconductor element 140 is disposed above the chip 120 . The multi-chip packaging module 200 further includes a spacer 230 disposed between the chip 120 and the first semiconductor element 140 . The spacer 230 is preferably a silicon spacer or a polyimide film. The spacer 230 separates the chip 120 from the first semiconductor device 140 , creating a space for the wire 222 to extend from the chip 120 to the substrate 110 . The encapsulant 150 covers the chip 120 , the spacer 230 and the first semiconductor element 140 , and the encapsulant 150 has an opening 155 exposing part of the first semiconductor element 140 . The second semiconductor element 160 is disposed on the first semiconductor element 140 and located in the opening 155 .

The semiconductor device may be a subpackage, that is, including at least one chip disposed on a substrate. Although FIG. 3 clearly discloses that the two chips 144 and 146 are disposed in the first semiconductor device 140 and the single chip 164 is disposed in the second semiconductor device 160 , the structure of the semiconductor device in the multi-chip package module 200 is not limited thereto. For example, the first semiconductor device 140 may only include a single chip, while the second semiconductor device 160 may include two chips.

4A-4E are schematic views of the manufacturing method of the multi-chip package module according to FIG. 3 . The manufacturing method of the chip packaging module 200 of this embodiment includes the following steps: firstly, a substrate 110 is provided, and a chip 120 is disposed on the substrate 110 , as shown in FIG. 4A . Then, the chip 120 is electrically connected to the substrate 110 by bonding wires 222 , as shown in FIG. 4B . Next, the spacer 230 is disposed on the chip 120, as shown in FIG. 4C. Afterwards, the first semiconductor element 140 is flip-chip disposed on the chip 120 and electrically connected to the substrate 110 by wire bonding, as shown in FIG. 4D . The chip 120 and the first semiconductor device 140 are electrically connected to the substrate 110 through the wires 222 and 149 respectively. Next, in the manner described in the first embodiment, the encapsulant 150 is sequentially sealed and the second semiconductor element 160 is disposed to complete the multi-chip package module 200 shown in FIG. 4E .

third embodiment

5 is a cross-sectional view of a multi-chip package module according to a third embodiment of the present invention. The difference between this embodiment and the above-mentioned embodiments lies in the chip 120 , the substrate 110 and the connection between the chip 120 and the first semiconductor element 140 . These differences will be described in detail in the following paragraphs, and the same components retain the original reference numbers, so they will not be described again.

Please refer to FIG. 5 , the multi-chip packaging module 300 of this embodiment includes a substrate 110 , a chip 120 , a first semiconductor element 140 , a first encapsulant 330 , a second encapsulant 150 and a second semiconductor element 160 . The chip 120 is disposed on the substrate 110 , preferably a plurality of wires 222 of the chip 120 are electrically connected to the chip 120 and the substrate 110 . The first encapsulant 330 covers the chip 120 and the wires 222 . The flip-chip first semiconductor element 140 is disposed above the chip 120 , preferably stacked on the first encapsulant 330 . The second encapsulant 150 covers the chip 120 , the first encapsulant 330 and the first semiconductor element 140 , and the second encapsulant 150 has an opening 155 exposing part of the first semiconductor element 140 . The second semiconductor element 160 is disposed on the first semiconductor element 140 and located in the opening 155 .

6A-6D are schematic views of the manufacturing method of the multi-chip package module according to FIG. 5 . The manufacturing method of the chip packaging module 300 of this embodiment includes the following steps: firstly, a substrate 110 is provided, a chip 120 is disposed on the substrate 110, and is electrically connected to the substrate 110 through wire 222 bonding, as shown in FIG. 6A . Then, the first encapsulant 330 covers the chip 120 and the wires 222 , as shown in FIG. 6B . Next, the first semiconductor element 140 is flipped and placed on the chip 120, preferably on the first sealant 330, and electrically connected to the substrate 110 by wire bonding, as shown in FIG. 6C . The chip 120 and the first semiconductor device 140 are electrically connected to the substrate 110 through the wires 222 and 149 respectively. Finally, in the manner described in the first embodiment, the second sealing compound 150 is used to seal and arrange the second semiconductor element 160 in order to complete the multi-chip package module 300 in FIG. 6D .

Compared with the prior art, the multi-chip package module disclosed in the above embodiments of the present invention and its manufacturing method have many advantages. Since more chips can be arranged in the package module, the volume of the package can be further reduced, and the package has better performance. The second semiconductor device with multiple functions can be combined into a multi-chip package module to expand and diversify its functions. In addition, since the second semiconductor element with specific functions can be assembled on the pre-assembled semi-finished package with basic functions as soon as the customer places an order, multi-chip package modules with specific functions can be manufactured more quickly come out. In this way, traditionally, a large and complex circuit design must be used to implement a fully functional module. The present invention only needs to use flexible design and combine different functional chips to make the packaged module have complete functions and better performance. The manufacturing process can be accelerated and simplified at the same time.

Claims (16)

1. A multi-chip packaging module, comprising: first substrate; a first chip disposed on the first substrate; a first semiconductor element disposed above the first chip; a first encapsulant, covering the first chip and the first semiconductor element; and a second semiconductor element, the bottom surface of which is provided with several first conductive bumps, and the second semiconductor element is arranged on the first semiconductor element; It is characterized in that: the first semiconductor element is arranged above the first chip in a flip-chip manner, the first sealant has an opening to expose part of the first semiconductor element, and the second semiconductor The element is located in the opening and is electrically connected with the first semiconductor element through the first conductive bump. 2. The multi-chip package module according to claim 1, wherein the multi-chip package module further comprises a plurality of second conductive bumps for electrically connecting the first chip and the first substrate. 3. The multi-chip package module according to claim 1, wherein the multi-chip package module further comprises a plurality of wires for electrically connecting the first chip and the first substrate. 4. The multi-chip package module according to claim 3, wherein the multi-chip package module further comprises a second encapsulant encapsulating the first chip. 5. The multi-chip package module according to claim 3, wherein the multi-chip package module further comprises a spacer disposed between the first chip and the first semiconductor element. 6. The multi-chip package module according to claim 1, wherein the first semiconductor element is a primary package, and the first semiconductor element comprises at least: second substrate; a second chip disposed on the second substrate; and a second sealant, covering the second chip and the second substrate; It is characterized in that: the first semiconductor element is arranged on the first chip in a flip-chip manner with the bottom of the second substrate facing up, and the opening of the first sealant exposes part of the second substrate. 7. The multi-chip package module according to claim 1, wherein the second semiconductor element is a primary package, and the second semiconductor element comprises at least: a second substrate, the first conductive bump is arranged on a bottom surface of the second substrate; a second chip disposed on a top surface of the second substrate; and The second encapsulant covers the second chip and the second substrate. 8 . The multi-chip package module according to claim 1 , wherein the multi-chip package module further comprises an underfill material filled between the first semiconductor element and the second semiconductor element. 9. A method for manufacturing a multi-chip packaged module, comprising the following steps: providing a first substrate; disposing a first chip on the first substrate; disposing a first semiconductor element over the first chip; electrically connecting the first chip and the first semiconductor element to the first substrate; sealing the first chip and the first semiconductor element with an encapsulant; and soldering a plurality of first conductive bumps of the second semiconductor element to the first semiconductor element; It is characterized in that: the first semiconductor element is arranged on the first chip in a flip-chip manner, and the sealing step further includes forming an opening on the first semiconductor element to expose part of the first chip. A semiconductor element, the second semiconductor element is disposed on the first semiconductor element and located in the opening. 10. The method of claim 9, further comprising disposing a plurality of second conductive bumps for electrically connecting the first chip and the first substrate. 11. The method as claimed in claim 9, further comprising disposing a plurality of wires for electrically connecting the first chip and the first substrate. 12. The method of claim 11, further comprising sealing the first chip with an encapsulant. 13. The method of claim 11, further comprising: providing a spacer and disposing it between the first chip and the first semiconductor device. 14. The method according to claim 11, wherein the first semiconductor element is a primary package, and the first semiconductor element comprises at least: a second substrate disposed on the first chip; a second chip disposed on the second substrate; and a second sealant, covering the second chip and the second substrate; It is characterized in that: the first semiconductor element is arranged on the first chip with its bottom facing up, and the opening of the first sealant exposes part of the second substrate. 15. The method according to claim 9, wherein the second semiconductor element is a primary package, and the second semiconductor element comprises at least: a second substrate, the first conductive bump is arranged on a bottom surface of the second substrate; a second chip disposed on a top surface of the second substrate; and The second encapsulant covers the second chip and the second substrate. 16. The method of claim 9, further comprising: filling an underfill material between the first semiconductor device and the second semiconductor device.

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