CN101241911A - Grid drive circuit integrated on display panel and manufacturing method thereof - Google Patents

Abstract

The invention provides a grid drive circuit integrated on a display panel and a manufacturing method thereof. The gate driving circuit structure is arranged in the peripheral area of the substrate and comprises a first layer of metal pattern, a second layer of metal pattern and an insulating layer arranged between the first layer of metal pattern and the second layer of metal pattern. The first-layer metal pattern includes a plurality of connection nodes. The insulating layer has a plurality of contact holes exposing the connection nodes of the first metal pattern. The second layer of metal pattern is filled into the contact hole and is directly lapped on the connection node of the first layer of metal pattern, thereby completing the electrical connection required by the grid driving circuit structure.

Description

Gate driving circuit integrated in display panel and manufacturing method thereof

technical field

The present invention relates to a gate driving circuit integrated in a display panel and a manufacturing method thereof, in particular to a gate driving circuit which does not need to use a transparent conductive layer to bridge a first-layer metal pattern and a second-layer metal pattern and a manufacturing method thereof.

Background technique

Display panels are currently widely used in daily life, such as Thin Film Transistor Liquid Crystal Display (TFT-LCD), Organic Light Emitting Diode Display (OLED), Low Temperature Polysilicon (LTPS) Display and Plasma Display (PDP). Please refer to Figure 1. FIG. 1 is a schematic diagram of a known thin film transistor liquid crystal display panel. As shown in FIG. 1 , the TFT display panel 10 includes a plurality of pixels 12 arranged in an array, and the pixels 12 are connected by a plurality of data lines D1, D2, . . . Gn control, wherein the data line is electrically connected to the data driving circuit 14 and is driven by it, and the gate line is electrically connected to the gate driving circuit 16 and is driven by it. In addition, the thin film transistor display panel 10 is also electrically connected to the printed circuit board 18, and the circuit on the printed circuit board 18 can convert the image signal into a voltage signal and transmit the voltage signal to the data driving circuit 14 and the data drive circuit 14 through the control bus (bus) 20. Gate drive circuit 16.

In recent years, the method of directly manufacturing the gate driving circuit structure on the display panel has gradually replaced the traditional method of using an external gate driver chip to drive pixels, thereby reducing the number of components and lowering the manufacturing cost. Please refer to Figure 2. FIG. 2 is a circuit diagram of a gate driver-on-array (GOA) integrated in a display panel. As shown in FIG. 2 , the function of the gate driving circuit is to generate pulses with a fixed time sequence, and the pulses will be sent to the TFT display panel 10 to control the TFTs in the pixels to be turned on. The gate driving circuit mainly includes a plurality of signal lines (such as L1, L2, L3 and L4), a plurality of thin film transistors (such as T1, T2, T3 and T4), a capacitor (such as C1), and a wire (such as W1). The signal line L1 is used to transmit a voltage signal Vss, the signal line L2 is used to transmit a start pulse signal Vst, the signal line L3 is used to transmit a clock signal Vck, and the signal line L4 is used to transmit a reverse To the clock (complementary clock) signal Vxck. The function of the wire W1 is to transmit the signal of the signal line, such as the signal line L4, to internal components, such as the thin film transistor T2. Please refer to Figure 3 again. FIG. 3 is a schematic diagram of a known gate driving circuit, which shows a schematic cross-sectional view along the section line A-A', section line B-B' and section line C-C' of FIG. 2 . As shown in FIG. 3 , the known gate drive circuit integrated in a display panel mainly consists of a first layer metal pattern 22, a gate insulating layer 24, a semiconductor layer 26, a heavily doped semiconductor layer 28, a second layer metal layer 30, and a protective layer. 32 and a transparent conductive layer (pixel electrode) 34 and other six-layer films are stacked. In the gate driving circuit structure, part of the first-layer metal pattern 22 must be electrically connected to the second-layer metal pattern 30 to perform required circuit functions. For example, the signal line L4 defined by the second-layer metal pattern 30 must be connected to the wire W1 defined by the first-layer metal pattern 22 , and the signal Vck can be transmitted to the drain of the TFT T2 through the wire W1 . In addition, the gate (first layer metal pattern 22 ) of the thin film transistor T1 must be electrically connected to its drain (second layer metal pattern 30 ).

As shown in FIG. 3 , in the known gate drive circuit structure, the electrical connection between the first-layer metal pattern 22 and the second-layer metal pattern 30 is in the protective layer 32 at the corresponding position and the gate insulation under the protective layer 32 A contact hole 32A is formed in the layer 24 , and the contact hole 32A is filled through the transparent conductive layer 34 to connect the first-layer metal pattern 22 and the second-layer metal pattern 30 in a bridging manner. However, the method of using the transparent conductive layer 34 to bridge the first-layer metal pattern 22 and the second-layer metal pattern 30 has the following disadvantages. First of all, the contact hole part is prone to subsequent through hole corrosion, and the bridge is prone to generate coupling capacitance. Moreover, the known practice often hides the bridging structure of the transparent conductive layer under the sealant, but such a method is likely to cause metal composition separation in the transparent conductive layer, resulting in poor contact between the first layer of metal patterns and the second layer of metal patterns, and Make the output waveform abnormal. In addition, using a transparent conductive layer to connect the first-layer metal pattern and the second-layer metal pattern also increases the layout area of the gate driving circuit.

Contents of the invention

One of the objects of the present invention is to provide a gate drive circuit integrated in a display panel (such as a thin-film transistor liquid crystal display, an organic light-emitting diode display, a low-temperature polysilicon display, and a plasma display, etc.) The layout area of the electrode driving circuit is reduced, its electrical reliability is increased, and its process is simplified.

To achieve the above purpose, a preferred embodiment of the present invention provides a gate driving circuit integrated in a display panel, including a substrate and a gate driving circuit structure. The substrate includes a peripheral area. The gate driving circuit structure is disposed on the peripheral area of the substrate, and includes a first layer metal pattern, a second layer metal pattern, an insulating layer, and a semiconductor layer. The first layer metal pattern includes a plurality of connection nodes. The insulating layer is disposed between the first-layer metal pattern and the second-layer metal pattern, and the insulating layer has a plurality of contact holes exposing the connection nodes. The second-layer metal pattern fills the contact holes and directly overlaps the connection nodes of the first-layer metal pattern, so as to complete the electrical connection required by the gate driving circuit structure.

To achieve the above object, another embodiment of the present invention provides a method for manufacturing a gate driving circuit integrated in a display panel, the method includes the following steps. Firstly, a substrate is provided, and a peripheral area is defined on the substrate. Then a first layer metal pattern is formed on the peripheral area of the substrate, wherein the first layer metal pattern includes a plurality of connection nodes. Then an insulating layer and a semiconductor layer are formed on the substrate and the first metal pattern, and a plurality of contact holes are formed on the insulating layer, respectively corresponding to the connection nodes to expose the connections of the first layer metal pattern nodes, and together form the channel pattern of the transistor element. Then a second layer metal pattern is formed on the insulating layer, and the second layer metal pattern is filled into the contact holes.

The gate drive circuit structure of the present invention is made by directly overlapping the metal pattern of the second layer with the metal pattern of the first layer, and there is no need to form a contact hole in the protective layer and use a transparent conductive layer for connection, so the layout of the gate drive circuit can be reduced area, improve its circuit reliability, and reduce process steps, and the present invention is not limited to liquid crystal displays, and can also be widely applied to other types of displays.

Description of drawings

FIG. 1 is a schematic diagram of a known thin film transistor liquid crystal display panel.

FIG. 2 illustrates a circuit diagram of a gate driving circuit integrated in a display panel.

FIG. 3 is a schematic diagram of a conventional gate driving circuit structure.

FIG. 4 is a schematic diagram of a preferred embodiment of a gate driving circuit integrated in a display panel of the present invention.

5 to 9 are schematic diagrams of a preferred embodiment of a method for fabricating a gate driving circuit integrated in a display panel according to the present invention.

10 and 11 are schematic diagrams of another preferred embodiment of the method for fabricating the gate driving circuit structure integrated in the display panel of the present invention.

Wherein, the reference signs are explained as follows:

10 Thin Film Transistor Display Panel 12 Pixels

14 Data drive circuit 16 Gate drive circuit

18 printed circuit board 20 bus

22 The first metal pattern 24 Gate insulation layer

26 Semiconductor layer 28 Heavily doped semiconductor

30 Second metal layer 32 Protective layer

32A Contact hole 34 Transparent conductive layer

50 Gate drive circuit structure 52 Substrate

54 Peripheral area 54A Signal line connection area

54B Thin Film Transistor Area 54C Capacitor Area

56 Gate drive circuit structure 58 The first metal pattern

58A Connection node 60 Insulation layer

60A contact hole 62 semiconductor layer

64 Heavily doped semiconductor layer 66 Second layer metal pattern

68 protective layer 70 substrate

72 Peripheral area 72A Signal line connection area

72B Thin Film Transistor Area 72C Capacitor Area

74 The first metal pattern 74A Connection node

76 insulation layer 76A contact hole

78 Semiconductor layer 80 Heavily doped semiconductor layer

81 photoresist layer 81A opening

82 Second layer metal pattern 84 Protective layer

Detailed ways

Several preferred embodiments of the present invention will be listed below, together with the accompanying drawings, element symbols, etc., to describe in detail the composition and desired effects of the present invention.

Please refer to FIG. 4 and also refer to the circuit diagram of the gate driving circuit in FIG. 2 . 4 is a schematic diagram of a preferred embodiment of the gate drive circuit integrated in the display panel of the present invention, which shows the gate drive circuit of the present invention along the section line AA', section line BB' and section in FIG. 2 Schematic cross-sectional view of line CC'. As shown in FIG. 4 , a gate driver-on-array (GOA) 50 integrated in a display panel includes a substrate 52 and a gate driver circuit structure 56 . The substrate 52 is an array substrate of a liquid crystal display panel, which includes a peripheral area 54 and a pixel area (not shown), and the gate driving circuit structure 56 is disposed in the peripheral area 54 of the substrate 52 . The peripheral area 54 includes a signal line connecting area 54A, a TFT area 54B and a capacitor area 54C. The gate drive circuit structure 56 of the present invention includes a first metal pattern 58, an insulating layer 60, a semiconductor 62, a heavily doped semiconductor layer 64, a second metal pattern 66, and a protective layer 68 from bottom to top. And the above-mentioned thin film constitutes each element of the gate driving circuit structure 56 . For example, in the signal line connection area 54A, the first layer metal pattern 58 is used as the wire W1, and the second layer metal pattern 66 is used as the signal line L1, L2, L3, L4; in the thin film transistor area 54B, the first layer metal pattern 58 as the gate of the thin film transistor T1, T2, T3, T4, the insulating layer 60 as the gate insulating layer, the semiconductor layer 62 as its channel, the heavily doped semiconductor layer 64 as the ohmic contact layer, and the second layer metal pattern 66 as Its source and drain; in the capacitor region 54C, the first layer of metal pattern 58 constitutes its lower electrode, the insulating layer 60 acts as its capacitor dielectric layer, and the second layer of metal pattern 66 constitutes its upper electrode.

The first metal pattern 58 includes a plurality of connection nodes 58A, which are used to electrically connect with the second metal pattern 66 . The insulation layer 60 is disposed between the first-layer metal pattern 58 and the second-layer metal pattern 66 , and the insulation layer 60 has a plurality of contact holes 60A exposing the connection nodes 58A of the first-layer metal pattern 58 . The second-layer metal pattern 66 is located on the insulating layer 60 and filled into the contact hole 60A of the insulating layer 60, so that the second-layer metal pattern 66 can directly overlap the connection node 58A of the first-layer metal pattern 58, Complete the electrical connections required by the gate drive circuit structure. The protective layer 68 covers the second-layer metal pattern 66 and the insulating layer 60 to prevent the second-layer metal pattern 60 from being exposed.

The connection node 58A of the first-layer metal pattern 58 can be located at any position of the first-layer metal pattern 58 integrated in the gate driving circuit 50 of the display panel that needs to be electrically connected with the second-layer metal pattern 66 . For example, the connection node 58A of the first layer metal pattern 58 can be an end point of a wire (such as the wire W1 in FIG. 2 ), and the second layer metal pattern 66 overlapping the connection node 58A can be a signal line ( For example, the signal line L4 ), in other words, the signal line L4 is directly lapped on the wire W1 to achieve electrical connection, instead of being electrically connected to the wire W1 through another conductive structure. In addition, the connecting node 58A can also be the gate of a thin film transistor (such as the thin film transistor T1 in FIG. The gate of the thin film transistor T1 is directly connected to its source or drain to be electrically connected without being electrically connected through other conductive structures. The application of the present invention is not limited to the above-mentioned position and display form. In addition to the above-mentioned position and display form, any needs of the first-layer metal pattern 58 integrated in the gate drive circuit structure 50 of the display panel and the second-layer metal pattern The position of the electrical connection of 66 can be achieved by using the second-layer metal pattern 66 to directly overlap the connection node 58A of the first-layer metal pattern 58 .

Different from the conventional gate drive circuit structure shown in FIG. 3 in which the transparent conductive layer 34 is used to connect the first layer metal pattern 22 and the second layer metal pattern 30, the gate drive circuit structure of the present invention (as shown in FIG. 4 ) The two are electrically connected by directly overlapping the second layer metal pattern 66 on the first layer metal pattern 58, so there is no need to form a contact hole in the protection layer 68, so that the protection layer 68 can make the second layer The metal pattern 66 is not exposed, avoiding the subsequent corrosion of the contact holes, and effectively reducing the layout area of the gate driving circuit.

Please refer to FIG. 5 to FIG. 9 again, and refer to FIG. 2 together. 5 to 9 are schematic diagrams of the preferred embodiment of the method for fabricating the gate drive circuit structure integrated in the display panel of the present invention, wherein this embodiment uses the liquid crystal display panel as an example to illustrate the method of the present invention, but the present invention The method is not limited to be applied to liquid crystal display panels, but can be applied to various types of display panels. As shown in FIG. 5, a substrate 70 is provided first. The substrate 70 is an array substrate of a liquid crystal display panel, and a peripheral area 72 is defined on the substrate 70 for forming peripheral circuits, and the peripheral area 72 includes a signal line connection area 72A, a thin film transistor area 72B, and a capacitor area 72C. The figure of this embodiment only shows the signal line connection area 72A, the thin film transistor area 72B and the capacitor area 72C to highlight the features of the present invention, but the application of the method of the present invention is not limited thereto. Next, a metal layer (not shown) is formed in the peripheral region 72 of the substrate 70, and part of the metal layer is removed by photolithography and etching techniques to form a first layer of metal patterns 74, wherein the first layer of metal patterns 74 are respectively connected to the signal lines The area 72A defines a wire, defines the gate of the thin film transistor in the thin film transistor area 72B, and defines structures such as electrodes under the capacitor in the capacitor area 72C, and the first layer metal pattern 74 includes a plurality of connection nodes 74A, as a follow-up It is used for the second layer metal pattern (not shown). As mentioned above, the position of the contact 74A shown in FIG. 5 is only for illustration, and those skilled in the art of the present invention can select an appropriate contact position on the first metal pattern 74 according to actual needs.

As shown in FIG. 6, an insulating layer 76 is then formed on the substrate 70 and the first metal pattern 74, and part of the insulating layer 76 is removed by photolithography and etching techniques to form a plurality of contact holes 76A corresponding to the connection nodes 74A, so as to Connection node 74A is exposed. The insulating layer 76 functions as an insulating layer in the signal line connection area 72A to prevent short circuits, serves as a gate insulating layer in the TFT area 72B, and serves as a capacitor dielectric layer in the capacitor area 72C. As shown in FIG. 7 , a semiconductor layer 78 and a heavily doped semiconductor layer 80 are sequentially formed on the insulating layer 76 of the TFT region 72B, wherein the semiconductor layer 78 serves as a channel, and the heavily doped semiconductor layer 80 serves as an ohmic contact layer.

As shown in FIG. 8, another metal layer (not shown) is formed on the insulating layer 76 and the heavily doped semiconductor layer 80, and part of the metal layer is removed by photolithography and etching techniques to form a second layer of metal pattern 82. , and finally use the second metal pattern 82 as a hard mask to form the pattern of the heavily doped semiconductor layer 80 as an ohmic contact layer. The second layer metal pattern 82 defines the signal line in the signal line connection area 72A, defines the source and drain of the thin film transistor in the thin film transistor area 72B, and defines structures such as the upper electrode of the capacitor in the capacitor area 72C, and in the Where the first layer metal pattern 74 needs to be electrically connected, such as the source or drain of the signal line or the thin film transistor, the second layer metal pattern 82 fills in the contact hole 76A of the insulating layer 76 and directly overlaps the first layer. It is worth noting that because the first layer metal pattern 74 is directly electrically connected to the second metal pattern 82 through the contact hole 76A, there is no need to use other conductive layers to bridge, so The layout area of the gate drive circuit can be reduced.

As shown in FIG. 9, a protective layer 84 is finally formed on the second-layer metal pattern 82, and the protective layer 84 is covered on the second-layer metal pattern 82 to ensure that the second-layer metal pattern 82 is not exposed, that is, the formation of the present invention. The gate driving circuit structure integrated in the display panel.

In the foregoing embodiments, although the insulating layer and the semiconductor layer are defined in different steps using two different masks, the method of the present invention is not limited thereto. Please refer to FIG. 10 and FIG. 11 , and refer to FIG. 5 and FIG. 8 to FIG. 9 together. FIG. 10 and FIG. 11 are schematic diagrams of another preferred embodiment of the method for fabricating a gate drive circuit structure integrated in a display panel according to the present invention. Steps and methods for doping a semiconductor layer, and for the convenience of comparison between this embodiment and the previous embodiments, the same symbols are used to label the same components. As shown in FIG. 10 , according to the method of this embodiment, after the first layer of metal pattern 74 is formed on the substrate 70, an insulating layer 76, a semiconductor layer 78 and a heavily doped layer are successively deposited on the substrate 70 and the first layer of metal pattern 74. The hetero-semiconductor layer 80 is then formed on the heavily doped semiconductor layer 80 with a photoresist layer 81 having different thicknesses in different regions. The fabrication of the photoresist layer 81 can be achieved by exposing a half-tone mask, wherein the half-tone mask has an opaque area, a transparent area, and a semi-transparent area, wherein the mask The opaque area of the mask corresponds to the region of the thicker first thickness T1 of the photoresist layer 81, the light-transmissive area of the mask corresponds to the region of the opening 81A of the photoresist layer 81, and half of the mask The light-transmitting region corresponds to the region of the second thickness T2 of the photoresist layer 81, so that a thicker first thickness T1 and a thinner thickness T1 can be formed on the photoresist layer 81 after exposure. The second thickness T2 and the opening 81A. As shown in FIG. 11 , etching is then carried out through different thicknesses of the photoresist layer 81 to form contact holes 76A in the insulating layer 76 corresponding to the positions of the connection nodes 74A, and to form contact holes 76A in the insulating layer 76 of the thin film transistor region 72B. A portion of the semiconductor layer 78 remains on the top as a channel, and a portion of the heavily doped semiconductor layer 80 remains as an ohmic contact layer. As can be seen from the above, the method of this embodiment only uses one mask to define the contact hole 76A of the insulating layer 76 and the pattern of the semiconductor layer 78, so one mask can be saved, and the subsequent process is similar to the previous embodiment, so it can be continued as shown in FIG. 8 and FIG. 9 will not be repeated here.

The gate drive circuit structure of the present invention is manufactured by using the second layer metal pattern directly overlapping the first layer metal pattern, without forming a contact hole in the protective layer and using a transparent conductive layer or an additional conductive layer for bridging, so it can be used The process steps are reduced, and the metal pattern of the second layer is covered and protected by the protection layer without being exposed, so that the structure of the gate driving circuit can be prevented from being exposed and damaged, thereby improving the reliability of the gate driving circuit. In addition, compared with the known bridging method of using a transparent conductive layer, the gate driving circuit structure of the present invention can reduce the layout area of the gate driving circuit, thereby simplifying the layout outside the panel (slim border).

Although the present invention has been disclosed above with the embodiments, it is not intended to limit the present invention. Any person with ordinary skill in the technical field of the present invention can make various changes and modifications without departing from the spirit and scope of the present invention. , and can refer to other different embodiments, so the protection scope of the present invention should be determined by the scope defined in the appended claims.

Claims (11)

1. gate driver circuit that is integrated in display floater comprises:

One substrate comprises a surrounding zone; And

One grid electrode drive circuit structure, be arranged at this surrounding zone of this substrate, this grid electrode drive circuit structure comprises ground floor metal pattern, second layer metal pattern and an insulating barrier, this insulating barrier is arranged between this ground floor metal pattern and this second layer metal pattern, wherein this ground floor metal pattern comprises a plurality of connected nodes, this insulating barrier has a plurality of contacts hole, described contact hole exposes described connected node, and this second layer metal pattern is inserted described contact hole and directly being overlapped on the described connected node of this ground floor metal pattern.

2. grid electrode drive circuit structure as claimed in claim 1 also comprises a protective layer, is covered on this second layer metal pattern.

3. grid electrode drive circuit structure as claimed in claim 1, wherein respectively this connected node of this ground floor metal pattern is an end points of a lead, and is overlapped in respectively that this second layer metal pattern of this connected node is a holding wire.

4. grid electrode drive circuit structure as claimed in claim 1, also comprise a thin-film transistor, this thin-film transistor comprises a grid, one source pole and a drain electrode, and respectively this connected node of this ground floor metal pattern is this grid, and this second layer metal pattern that is overlapped in this connected node respectively is maybe this drain electrode of this source electrode.

5. grid electrode drive circuit structure as claimed in claim 1, wherein this thin-film transistor also comprises a semi-conductor layer and a heavily doped semiconductor layer, between this insulating barrier and this source electrode and this drain electrode of this thin-film transistor.

6. a making is integrated in the method for the gate driver circuit of display floater, comprising:

One substrate is provided, and on this substrate, defines a surrounding zone;

This surrounding zone in this substrate forms the ground floor metal pattern, and wherein this ground floor metal pattern comprises a plurality of connected nodes;

On this substrate and this ground floor metal pattern, form an insulating barrier, and on this insulating barrier, form a plurality of contacts hole, respectively to should connected node to expose described connected node; And

On this insulating barrier, form the second layer metal pattern, and make this second layer metal pattern insert described contact hole.

7. method as claimed in claim 6 also is included in and forms a protective layer on this second layer metal pattern.

8. method as claimed in claim 6, wherein respectively this connected node of this ground floor metal pattern is an end points of a lead, and is overlapped in respectively that this second layer metal pattern of this connected node is a holding wire.

9. method as claimed in claim 6, also comprise a thin-film transistor, this thin-film transistor comprises a grid, one source pole and a drain electrode, and respectively this connected node of this ground floor metal pattern is this grid, and is overlapped in respectively that this second layer metal pattern of this connected node is maybe this drain electrode of this source electrode.

10. method as claimed in claim 6 also is included in and forms a semi-conductor layer and a heavily doped semiconductor layer between this insulating barrier of this thin-film transistor and this source electrode and this drain electrode.

11. method as claimed in claim 10, wherein this insulating barrier and this semiconductor layer are defined by a photoresist layer with different-thickness.

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