CN101241911A - Grid driving circuit integrated on display panel and its making method - Google Patents
Grid driving circuit integrated on display panel and its making method Download PDFInfo
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- CN101241911A CN101241911A CNA2008100873356A CN200810087335A CN101241911A CN 101241911 A CN101241911 A CN 101241911A CN A2008100873356 A CNA2008100873356 A CN A2008100873356A CN 200810087335 A CN200810087335 A CN 200810087335A CN 101241911 A CN101241911 A CN 101241911A
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Abstract
The invention provides a grid driving circuit integrating into the display panel and manufacturing method thereof comprising base plate and grid driving circuit structure arranging thereon. The grid driving circuit structure arranges around the perimeter zone of the base plate comprising a first layer metal pattern, a second layer metal pattern and a insulating layer arranging therebetween. The first layer metal pattern includes a plurality of connected nodes. The insulating layer has a plurality of contact holes exposing the connected nodes of the first metal pattern. The second layer metal pattern fills into the contact holes and directly connects to connected nodes of the first metal pattern so as to accomplish the needed electrically connecting of the grid driving circuit.
Description
Technical field
The present invention relates to a kind of gate driver circuit that is integrated in display floater and preparation method thereof, relate in particular to a kind of gate driver circuit of utilizing by transparency conducting layer bridge joint ground floor metal pattern and second layer metal pattern and preparation method thereof that need not.
Background technology
Display floater is applied in the life, for example at present widely: Thin Film Transistor-LCD (TFT-LCD), organic light emitting diode display (OLED), low temperature polycrystalline silicon (LTPS) display and plasma scope (PDP) etc.Please refer to Fig. 1.Fig. 1 illustrates the schematic diagram of known liquid crystal display panel of thin film transistor.As shown in Figure 1, film transistor display panel 10 includes a plurality of pixels that are in array-like arrangement 12, pixel 12 be by many data wire D1, D2 ..., Dn and many gate lines G 1, G2 ..., Gn control, wherein data wire is electrically connected to data drive circuit 14 and accepts its driving, and gate line is electrically connected to gate driver circuit 16 and accept its driving.In addition, film transistor display panel 10 also is electrically connected with printed circuit board (PCB) 18, and the circuit on the printed circuit board (PCB) 18 can be converted to signal of video signal voltage signal and voltage signal is sent to data drive circuit 14 and gate driver circuit 16 by control bus (bus) 20.
In recent years, the practice that grid electrode drive circuit structure directly is made on the display floater replaces the practice that tradition is utilized external gate driving wafer driving pixel gradually, thereby reduces component number and reduce manufacturing cost.Please refer to Fig. 2.Fig. 2 illustrates gate driver circuit (gatedriver-on-array, circuit diagram GOA) that is integrated in display floater.As shown in Figure 2, the effect of gate driver circuit is to produce the pulse of fixed time sequence, and this pulse meeting is sent to film transistor display panel 10, with the unlatching of thin-film transistor in the control pixel.Gate driver circuit mainly comprises many signal line (for example L1, L2, L3 and L4), a plurality of thin-film transistor (for example T1, T2, T3 and T4), electric capacity (for example C1), and lead (for example W1).Holding wire L1 is used to transmit an initial pulse (start pulse) signal Vst, holding wire L3 in order to transmitting a clock (clock) signal Vck in order to transmit a voltage signal Vss, holding wire L2, and holding wire L4 is in order to transmit reverse clock (complementary clock) signal Vxck.The effect of lead W1 be with holding wire for example the signal of holding wire L4 be passed to inner member, thin-film transistor T2 for example.Refer again to Fig. 3.Fig. 3 is the schematic diagram of known gate driver circuit, and it illustrates the generalized section of hatching A-A ', hatching B-B ' and hatching C-C ' along Fig. 2.As shown in Figure 3, the known gate driver circuit that is integrated in display floater is mainly piled up with six layer films such as heavily-doped semiconductor 28, second layer metal layer 30, protective layer 32 and transparency conducting layers (pixel electrode) 34 by ground floor metal pattern 22, gate insulator 24, semiconductor layer 26 and forms.In grid electrode drive circuit structure, part ground floor metal pattern 22 must electrically connect with second layer metal pattern 30, to bring into play required circuit function.For instance, the holding wire L4 that is defined by second layer metal pattern 30 must be connected to the lead W1 that is defined by ground floor metal pattern 22, and signal Vck can be sent to the drain electrode of thin-film transistor T2 by lead W1.In addition, the grid of thin-film transistor T1 (ground floor metal pattern 22) must electrically connect with its drain electrode (second layer metal pattern 30).
As shown in Figure 3; in known grid electrode drive circuit structure; ground floor metal pattern 22 forms in the protective layer 32 of correspondence position and in the gate insulator 24 of protective layer 32 belows with the electric connection mode of second layer metal pattern 30 and contacts hole 32A, and inserts contact hole 32A by transparency conducting layer 34 and connect ground floor metal pattern 22 and second layer metal pattern 30 in the bridge joint mode.Yet, utilize the transparency conducting layer 34 bridge joint ground floor metal patterns 22 and the practice of second layer metal pattern 30 can produce following shortcoming.At first, the contact cavity portion is easily in follow-up generation etching problem (through hole corrosion), and the bridge joint place is easy to generate coupling capacitance.Moreover, the known practice often is hidden in the transparency conducting layer bridging structure under the frame glue, but so the practice causes transparency conducting layer to produce metal ingredient easily and separates out phenomenon, causes ground floor metal pattern and the loose contact of second layer metal pattern, and makes output waveform unusual.In addition, use the practice of transparency conducting layer connection ground floor metal pattern and second layer metal pattern, also can increase the layout area of gate driver circuit.
Summary of the invention
One of purpose of the present invention is to provide a kind of gate driver circuit that is integrated in display floater (for example Thin Film Transistor-LCD, organic light emitting diode display, low temperature polycrystalline silicon display and plasma scope etc.) and preparation method thereof, with the layout area of reduction gate driver circuit, increase its electrical reliability, and simplify its technology.
For reaching above-mentioned purpose, a preferred embodiment of the present invention provides a kind of gate driver circuit that is integrated in display floater, comprises a substrate and a grid electrode drive circuit structure.Substrate comprises a surrounding zone.Grid electrode drive circuit structure is arranged at this surrounding zone of this substrate, and it comprises ground floor metal pattern, second layer metal pattern, an insulating barrier, and semi-conductor layer.The ground floor metal pattern comprises a plurality of connected nodes.Insulating barrier is provided with between this ground floor metal pattern and this second layer metal pattern, and this insulating barrier has a plurality of contacts hole and exposes these connected nodes.The second layer metal pattern is inserted these contact holes and directly is overlapped on these connected nodes of this ground floor metal pattern, thereby finishes the required electric connection of this grid electrode drive circuit structure.
For reaching above-mentioned purpose, another embodiment of the present invention provides a kind of making to be integrated in the method for the gate driver circuit of display floater, and said method comprises the following steps.One substrate at first is provided, and on this substrate, defines a surrounding zone.Then form a ground floor metal pattern in this surrounding zone of this substrate, wherein this ground floor metal pattern comprises a plurality of connected nodes.On this substrate and this ground floor metal pattern, form an insulating barrier and semi-conductor layer subsequently, and on this insulating barrier, form a plurality of contacts hole, respectively to should connected node exposing these connected nodes of this ground floor metal pattern, and form the channel pattern of transistor unit in the lump.Then on this insulating barrier, form a second layer metal pattern, and make this second layer metal pattern insert these contact holes.
The mode that grid electrode drive circuit structure of the present invention utilizes the second layer metal pattern directly to overlap the ground floor metal pattern is made; not needing to form the contact hole in protective layer utilizes transparency conducting layer to connect; so can reduce gate driver circuit layout area, improve its circuit reliability; and minimizing processing step; and the present invention is not limited to LCD, also can be widely used on the display of other types.
Description of drawings
Fig. 1 illustrates the schematic diagram of known liquid crystal display panel of thin film transistor.
Fig. 2 has illustrated the circuit diagram of the gate driver circuit that is integrated in display floater.
Fig. 3 is the schematic diagram of known grid electrode drive circuit structure.
Fig. 4 is integrated in the schematic diagram of preferred embodiment of the gate driver circuit of display floater for the present invention.
Fig. 5 to Fig. 9 makes the method schematic diagram of the preferred embodiment of the gate driver circuit that is integrated in display floater for the present invention.
Figure 10 and Figure 11 make the method schematic diagram of another preferred embodiment of the grid electrode drive circuit structure that is integrated in display floater for the present invention.
Wherein, description of reference numerals is as follows:
10 film transistor display panels, 12 pixels
14 data drive circuits, 16 gate driver circuits
18 printed circuit board (PCB)s, 20 buses
22 ground floor metal patterns, 24 gate insulators
26 semiconductor layers, 28 heavily-doped semiconductors
30 second layer metal layers, 32 protective layer
50 grid electrode drive circuit structures, 52 substrates
54A holding wire bonding pad, 54 surrounding zone
54B thin film transistor region 54C capacitive region
56 grid electrode drive circuit structures, 58 ground floor metal patterns
58A connected node 60 insulating barriers
64 heavily doped semiconductor layers, 66 second layer metal patterns
68 protective layers, 70 substrates
72A holding wire bonding pad, 72 surrounding zone
72B thin film transistor region 72C capacitive region
74 ground floor metal pattern 74A connected nodes
76 insulating barrier 76A contact the hole
78 semiconductor layers, 80 heavily doped semiconductor layers
81 photoresist layer 81A openings
82 second layer metal patterns, 84 protective layers
Embodiment
Hereinafter will enumerate several preferred embodiments of the present invention, and cooperate appended accompanying drawing, component symbol etc., describe in detail constitution content of the present invention and the effect desiring to reach.
Please refer to Fig. 4, and in the lump with reference to the circuit diagram of the gate driver circuit of figure 2.Fig. 4 is integrated in the schematic diagram of preferred embodiment of the gate driver circuit of display floater for the present invention, it illustrates the generalized section of gate driver circuit of the present invention along hatching A-A ', hatching B-B ' Yu the hatching C-C ' of Fig. 2.As shown in Figure 4, (gate driver-on-array, GOA) 50 comprise substrate 52 and grid electrode drive circuit structure 56 to be integrated in the gate driver circuit of display floater.Substrate 52 is the array base palte of display panels, and it comprises surrounding zone 54 and pixel region (figure does not show), and grid electrode drive circuit structure 56 is arranged in the surrounding zone 54 of substrate 52.Surrounding zone 54 includes holding wire bonding pad 54A, thin film transistor region 54B and capacitive region 54C.Grid electrode drive circuit structure 56 of the present invention comprises in regular turn that from bottom to top ground floor metal pattern 58, insulating barrier 60, semiconductor 62, heavily doped semiconductor layer 64, second belong to films such as metal pattern 66 and protective layer 68, and above-mentioned film is formed each element of grid electrode drive circuit structure 56.For example in the 54A of holding wire bonding pad, ground floor metal pattern 58 is as lead W1, and second layer metal pattern 66 is then as holding wire L1, L2, L3, L4; In thin film transistor region 54B, ground floor metal pattern 58 as the grid of thin-film transistor T1, T2, T3, T4, insulating barrier 60 as gate insulator, semiconductor layer 62 as its passage, heavily doped semiconductor layer 64 as ohmic contact layer, and second layer metal pattern 66 is as its source electrode and drain electrode; In capacitive region 54C, ground floor metal pattern 58 constitutes its bottom electrode, insulating barrier 60 constitutes its top electrode as its capacitance dielectric layer, second layer metal pattern 66.
Ground floor metal pattern 58 comprises a plurality of connected nodes (connection node) 58A, its role is to electrically connect with second layer metal pattern 66.Insulating barrier 60 is provided with between ground floor metal pattern 58 and the second layer metal pattern 66, and insulating barrier 60 has the connected node 58A that a plurality of contacts hole 60A exposes ground floor metal pattern 58.Second layer metal pattern 66 is positioned on the insulating barrier 60, and insert within the contact hole 60A of insulating barrier 60, second layer metal pattern 66 can directly be overlapped on the connected node 58A of ground floor metal pattern 58 thus, finishes the required electric connection of grid electrode drive circuit structure.68 of protective layers are covered on second layer metal pattern 66 and the insulating barrier 60, make outside second layer metal pattern 60 unlikely being exposed to.
The connected node 58A of ground floor metal pattern 58 can be positioned at any position that need electrically connect with second layer metal pattern 66 of the ground floor metal pattern 58 of the gate driver circuit 50 that is integrated in display floater.For instance, the connected node 58A of ground floor metal pattern 58 can be lead one end points of (example adds the lead W1 of Fig. 2), and the second layer metal pattern 66 that is overlapped on the connected node 58A can be holding wire (for example holding wire L4), in other words holding wire L4 directly is overlapped on the lead W1 and reaches electric connection, but not electrically connects by other conductive structure and lead W1.In addition, connected node 58A also can be the grid of thin-film transistor (for example thin-film transistor T1 of Fig. 2), and the second layer metal pattern 66 that is overlapped in connected node 58A can be source electrode or the drain electrode of thin-film transistor T1, therefore the grid of thin-film transistor T1 directly is overlapped in its source electrode or the drain electrode and reaches electric connection, and does not electrically connect by other conductive structure.The not above rheme of application of the present invention is put and the display form is exceeded, except above-mentioned position and display form, be integrated in any position that need electrically connect with second layer metal pattern 66 of ground floor metal pattern 58 of the grid electrode drive circuit structure 50 of display floater, all can utilize second layer metal pattern 66 directly the modes of the connected node 58A of overlap joint ground floor metal patterns 58 reach.
Being different from known grid electrode drive circuit structure shown in Figure 3 utilizes transparency conducting layer 34 to connect the mode of ground floor metal pattern 22 and second layer metal pattern 30; grid electrode drive circuit structure of the present invention (as shown in Figure 4) utilization electrically connects the mode that second layer metal pattern 66 directly is overlapped in ground floor metal pattern 58 with both; therefore do not need in protective layer 68, to form the contact hole; protective layer 68 can make outside second layer metal pattern 66 can not be exposed to thus; avoid contacting cavity portion easily in follow-up generation etching problem, more can effectively reduce the layout area of gate driver circuit.
Refer again to Fig. 5 to Fig. 9, and in the lump with reference to figure 2.Fig. 5 to Fig. 9 has illustrated the method schematic diagram that the present invention makes the preferred embodiment of the grid electrode drive circuit structure that is integrated in display floater, wherein present embodiment is to be that example illustrates method of the present invention with the display panels, but method of the present invention is not limited to be applied to display panels, and can be applicable to all types of display floaters.As shown in Figure 5, at first provide substrate 70.Substrate 70 is the array base palte of display panels, and definition has surrounding zone 72 on the substrate 70, and in order to the formation peripheral circuit, and surrounding zone 72 includes holding wire bonding pad 72A, thin film transistor region 72B and capacitive region 72C.The accompanying drawing of present embodiment only shows holding wire bonding pad 72A, thin film transistor region 72B and capacitive region 72C so that highlight feature of the present invention, but the application of method of the present invention is not as limit.Then in the surrounding zone 72 of substrate 70, form metal level (figure does not show), and utilize photoetching and etching technique to remove the part metals layer to form ground floor metal pattern 74, wherein ground floor metal pattern 74 defines lead, defines the grid of thin-film transistor in thin film transistor region 72B respectively at holding wire bonding pad 72A, and define structure such as electrode under the electric capacity in capacitive region 72C, and ground floor metal pattern 74 includes a plurality of connected node 74A, as usefulness follow-up and second layer metal pattern (scheming not show).As previously mentioned, the general technical staff of the technical field of the invention is familiar with when selecting suitable connecting point position on ground floor metal pattern 74 according to actual demand only for illustrating in the position of the contact 74A that illustrates among Fig. 5.
As shown in Figure 6, then on substrate 70 and ground floor metal pattern 74, form insulating barrier 76, and utilize photoetching and etching technique to remove partial insulative layer 76, form a plurality of contact hole 76A, to expose connected node 74A corresponding to connected node 74A.Insulating barrier 76 in holding wire bonding pad 72A performance insulating effect with avoid short circuit, in the usefulness of thin film transistor region 72B, and in the usefulness of capacitive region 72C as capacitance dielectric layer as gate insulator.As shown in Figure 7, form semiconductor layer 78 and heavily doped semiconductor layer 80 subsequently on the insulating barrier 76 of thin film transistor region 72B in regular turn, wherein semiconductor layer 78 is as passage, and heavily doped semiconductor layer 80 is as ohmic contact layer.
As shown in Figure 8, on insulating barrier 76 and heavily doped semiconductor layer 80, form another metal level (figure does not show) afterwards, and utilize photoetching and etching technique to remove the part metals layer, to form second layer metal pattern 82, make hard mask (hard mask) with second layer metal pattern 82 at last, to form pattern as the heavily doped semiconductor layer 80 of ohmic contact layer.Second layer metal pattern 82 defines holding wire, defines the source electrode and the drain electrode of thin-film transistor in thin film transistor region 72B respectively at holding wire bonding pad 72A, and define structure such as electrode on the electric capacity in capacitive region 72C, and in the position that need electrically connect with ground floor metal pattern 74, the for example source electrode of holding wire or thin-film transistor or drain electrode, second layer metal pattern 82 are inserted in the contact hole 76A of insulating barrier 76 and directly are overlapped on the connected node 74A of ground floor metal pattern 74; It should be noted that because ground floor metal pattern 74 is to utilize contact hole 76A directly to electrically connect with second metal pattern 82, do not need additionally to utilize other conductive layer to come bridge joint, so can reduce the layout area of gate driver circuit.
As shown in Figure 9; on second layer metal pattern 82, form protective layer 84 at last; and make protective layer 84 be covered in second layer metal pattern 82 to guarantee promptly to form the grid electrode drive circuit structure that is integrated in display floater of the present invention outside second layer metal pattern 82 unlikely being exposed to.
In the aforementioned embodiment, though insulating barrier utilizes different being masked in the different step of twice to be defined respectively with semiconductor layer, yet method of the present invention is not as limit.Please refer to Figure 10 and Figure 11, and in the lump with reference to figure 5 and Fig. 8 to Fig. 9.Figure 10 and Figure 11 have illustrated the method schematic diagram that the present invention makes another preferred embodiment of the grid electrode drive circuit structure that is integrated in display floater, wherein the difference of present embodiment and previous embodiment is the step method of making insulating barrier, semiconductor layer, heavily doped semiconductor layer, and for ease of relatively present embodiment and previous embodiment are used same numeral mark similar elements.As shown in figure 10, method according to present embodiment, after forming ground floor metal pattern 74 on the substrate 70, successive sedimentation goes out insulating barrier 76, semiconductor layer 78 and heavily doped semiconductor layer 80 on substrate 70 and ground floor metal pattern 74, then is formed at the photoresist layer 81 that zones of different has different-thickness again on heavily doped semiconductor layer 80.The mode that the making of photoresist layer 81 can utilize gray-tone mask (half-tone mask) to expose is reached, wherein gray-tone mask has light tight district, transparent area and semi-opaque region, wherein the light tight district of mask corresponds to the zone of the first thicker thickness T 1 of photoresist floor 81, the transparent area of mask corresponds to the zone of the opening 81A of photoresist layer 81, the semi-opaque region of mask then corresponds to the zone of the second thin thickness T 2 of photoresist layer 81, can form the first thicker thickness T 1 in photoresist layer 81 thus after exposure, thin second thickness T 2 and opening 81A.As shown in figure 11, then carry out carrying out etching by the different-thickness of photoresist layer 81, form contact hole 76A with position respectively at corresponding connection node 74A in the insulating barrier 76, and reserve part semiconductor layer 78 is as passage on the insulating barrier 76 of thin film transistor region 72B, and reserve part heavily doped semiconductor layer 80 is as ohmic contact layer.From the above, the method of present embodiment is only used the contact hole 76A of one mask definition insulating barrier 76 and the pattern of semiconductor layer 78, therefore can save mask one, and follow-up technology is then similar to previous embodiment, so but the practice of hookup 8 and Fig. 9 does not repeat them here.
The mode that grid electrode drive circuit structure of the present invention utilizes the second layer metal pattern directly to overlap the ground floor metal pattern is made; do not need to form the contact hole and utilize transparency conducting layer or extra conductive layer carries out bridge joint in protective layer; therefore can reduce processing step; and the second layer metal pattern is protective layer institute's covering protection and not exposing; therefore can avoid grid electrode drive circuit structure to expose and impaired, so can improve the reliability of gate driver circuit.In addition, grid electrode drive circuit structure of the present invention can reduce the layout area of gate driver circuit compared to the known transparency conducting layer bridge joint mode of utilizing, and then simplifies panels outside layout (slimborder).
Though the present invention discloses as above with embodiment; right its is not in order to limit the present invention; any have a general technical staff of the technical field of the invention; without departing from the spirit and scope of the present invention; when doing various changes and retouching; and can be with reference to other different embodiment, so protection scope of the present invention should be looked accompanying Claim book institute restricted portion and is as the criterion.
Claims (11)
1. gate driver circuit that is integrated in display floater comprises:
One substrate comprises a surrounding zone; And
One grid electrode drive circuit structure, be arranged at this surrounding zone of this substrate, this grid electrode drive circuit structure comprises ground floor metal pattern, second layer metal pattern and an insulating barrier, this insulating barrier is arranged between this ground floor metal pattern and this second layer metal pattern, wherein this ground floor metal pattern comprises a plurality of connected nodes, this insulating barrier has a plurality of contacts hole, described contact hole exposes described connected node, and this second layer metal pattern is inserted described contact hole and directly being overlapped on the described connected node of this ground floor metal pattern.
2. grid electrode drive circuit structure as claimed in claim 1 also comprises a protective layer, is covered on this second layer metal pattern.
3. grid electrode drive circuit structure as claimed in claim 1, wherein respectively this connected node of this ground floor metal pattern is an end points of a lead, and is overlapped in respectively that this second layer metal pattern of this connected node is a holding wire.
4. grid electrode drive circuit structure as claimed in claim 1, also comprise a thin-film transistor, this thin-film transistor comprises a grid, one source pole and a drain electrode, and respectively this connected node of this ground floor metal pattern is this grid, and this second layer metal pattern that is overlapped in this connected node respectively is maybe this drain electrode of this source electrode.
5. grid electrode drive circuit structure as claimed in claim 1, wherein this thin-film transistor also comprises a semi-conductor layer and a heavily doped semiconductor layer, between this insulating barrier and this source electrode and this drain electrode of this thin-film transistor.
6. a making is integrated in the method for the gate driver circuit of display floater, comprising:
One substrate is provided, and on this substrate, defines a surrounding zone;
This surrounding zone in this substrate forms the ground floor metal pattern, and wherein this ground floor metal pattern comprises a plurality of connected nodes;
On this substrate and this ground floor metal pattern, form an insulating barrier, and on this insulating barrier, form a plurality of contacts hole, respectively to should connected node to expose described connected node; And
On this insulating barrier, form the second layer metal pattern, and make this second layer metal pattern insert described contact hole.
7. method as claimed in claim 6 also is included in and forms a protective layer on this second layer metal pattern.
8. method as claimed in claim 6, wherein respectively this connected node of this ground floor metal pattern is an end points of a lead, and is overlapped in respectively that this second layer metal pattern of this connected node is a holding wire.
9. method as claimed in claim 6, also comprise a thin-film transistor, this thin-film transistor comprises a grid, one source pole and a drain electrode, and respectively this connected node of this ground floor metal pattern is this grid, and is overlapped in respectively that this second layer metal pattern of this connected node is maybe this drain electrode of this source electrode.
10. method as claimed in claim 6 also is included in and forms a semi-conductor layer and a heavily doped semiconductor layer between this insulating barrier of this thin-film transistor and this source electrode and this drain electrode.
11. method as claimed in claim 10, wherein this insulating barrier and this semiconductor layer are defined by a photoresist layer with different-thickness.
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| CNB2008100873356A CN100559587C (en) | 2008-03-21 | 2008-03-21 | Be integrated in gate driver circuit of display floater and preparation method thereof |
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| CNB2008100873356A CN100559587C (en) | 2008-03-21 | 2008-03-21 | Be integrated in gate driver circuit of display floater and preparation method thereof |
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| CN101241911A true CN101241911A (en) | 2008-08-13 |
| CN100559587C CN100559587C (en) | 2009-11-11 |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103698954A (en) * | 2013-12-31 | 2014-04-02 | 合肥京东方光电科技有限公司 | Liquid crystal panel and liquid crystal display device |
| CN104867940A (en) * | 2015-04-22 | 2015-08-26 | 合肥鑫晟光电科技有限公司 | Array substrate and preparation method thereof, display panel, and display apparatus |
| CN105355604A (en) * | 2015-10-12 | 2016-02-24 | 深超光电（深圳）有限公司 | Thin-film transistor array substrate |
| CN111584512A (en) * | 2020-05-14 | 2020-08-25 | Tcl华星光电技术有限公司 | Array substrate, manufacturing method thereof and display device |
| CN112068367A (en) * | 2019-06-10 | 2020-12-11 | 群创光电股份有限公司 | Electronic device and splicing type electronic device |
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2008
- 2008-03-21 CN CNB2008100873356A patent/CN100559587C/en active Active
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103698954A (en) * | 2013-12-31 | 2014-04-02 | 合肥京东方光电科技有限公司 | Liquid crystal panel and liquid crystal display device |
| WO2015100988A1 (en) * | 2013-12-31 | 2015-07-09 | 京东方科技集团股份有限公司 | Liquid crystal panel and liquid crystal display device |
| CN103698954B (en) * | 2013-12-31 | 2016-03-02 | 合肥京东方光电科技有限公司 | A kind of liquid crystal panel and liquid crystal indicator |
| US9366914B2 (en) | 2013-12-31 | 2016-06-14 | Boe Technology Group Co., Ltd. | Liquid crystal panel and liquid crystal display device |
| CN104867940A (en) * | 2015-04-22 | 2015-08-26 | 合肥鑫晟光电科技有限公司 | Array substrate and preparation method thereof, display panel, and display apparatus |
| WO2016169169A1 (en) * | 2015-04-22 | 2016-10-27 | 京东方科技集团股份有限公司 | Array substrate and preparation method therefor, display panel, and display device |
| CN104867940B (en) * | 2015-04-22 | 2019-03-15 | 合肥鑫晟光电科技有限公司 | A kind of array substrate and preparation method thereof, display panel, display device |
| CN105355604A (en) * | 2015-10-12 | 2016-02-24 | 深超光电（深圳）有限公司 | Thin-film transistor array substrate |
| CN105355604B (en) * | 2015-10-12 | 2018-04-20 | 深超光电（深圳）有限公司 | Thin-film transistor array base-plate |
| CN112068367A (en) * | 2019-06-10 | 2020-12-11 | 群创光电股份有限公司 | Electronic device and splicing type electronic device |
| CN111584512A (en) * | 2020-05-14 | 2020-08-25 | Tcl华星光电技术有限公司 | Array substrate, manufacturing method thereof and display device |
| CN111584512B (en) * | 2020-05-14 | 2024-01-05 | Tcl华星光电技术有限公司 | Array substrate, manufacturing method thereof and display device |
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|---|---|
| CN100559587C (en) | 2009-11-11 |
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