CN101192647B - Nonvolatile memory device including amorphous alloy metal oxide layer - Google Patents
Nonvolatile memory device including amorphous alloy metal oxide layer Download PDFInfo
- Publication number
- CN101192647B CN101192647B CN2006101636363A CN200610163636A CN101192647B CN 101192647 B CN101192647 B CN 101192647B CN 2006101636363 A CN2006101636363 A CN 2006101636363A CN 200610163636 A CN200610163636 A CN 200610163636A CN 101192647 B CN101192647 B CN 101192647B
- Authority
- CN
- China
- Prior art keywords
- nonvolatile memory
- coating
- amorphous alloy
- memory devices
- metal oxide
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 229910000808 amorphous metal alloy Inorganic materials 0.000 title claims abstract description 26
- 229910044991 metal oxide Inorganic materials 0.000 title claims abstract description 25
- 150000004706 metal oxides Chemical class 0.000 title claims abstract description 25
- 239000011248 coating agent Substances 0.000 claims description 40
- 238000000576 coating method Methods 0.000 claims description 40
- 229910052723 transition metal Inorganic materials 0.000 claims description 10
- 150000003624 transition metals Chemical class 0.000 claims description 10
- 229910052751 metal Inorganic materials 0.000 claims description 9
- 239000002184 metal Substances 0.000 claims description 9
- 239000013078 crystal Substances 0.000 claims description 8
- 230000015572 biosynthetic process Effects 0.000 claims description 7
- 229910052741 iridium Inorganic materials 0.000 claims description 6
- 229910052697 platinum Inorganic materials 0.000 claims description 6
- 229910052707 ruthenium Inorganic materials 0.000 claims description 6
- 229910052719 titanium Inorganic materials 0.000 claims description 4
- 229910052725 zinc Inorganic materials 0.000 claims description 4
- 229910052735 hafnium Inorganic materials 0.000 claims description 3
- 229910052759 nickel Inorganic materials 0.000 claims description 3
- 229910052721 tungsten Inorganic materials 0.000 claims description 3
- 229910052726 zirconium Inorganic materials 0.000 claims description 3
- 238000004519 manufacturing process Methods 0.000 abstract description 2
- 238000003860 storage Methods 0.000 description 18
- 229910000314 transition metal oxide Inorganic materials 0.000 description 14
- 239000010408 film Substances 0.000 description 12
- 238000002425 crystallisation Methods 0.000 description 11
- 230000008025 crystallization Effects 0.000 description 11
- 238000010586 diagram Methods 0.000 description 8
- 239000000463 material Substances 0.000 description 8
- VRIVJOXICYMTAG-IYEMJOQQSA-L iron(ii) gluconate Chemical compound [Fe+2].OC[C@@H](O)[C@@H](O)[C@H](O)[C@@H](O)C([O-])=O.OC[C@@H](O)[C@@H](O)[C@H](O)[C@@H](O)C([O-])=O VRIVJOXICYMTAG-IYEMJOQQSA-L 0.000 description 6
- 239000000758 substrate Substances 0.000 description 6
- 238000004626 scanning electron microscopy Methods 0.000 description 5
- 239000004065 semiconductor Substances 0.000 description 5
- 238000002441 X-ray diffraction Methods 0.000 description 4
- 230000008859 change Effects 0.000 description 4
- 230000014759 maintenance of location Effects 0.000 description 4
- 238000000034 method Methods 0.000 description 4
- 230000008901 benefit Effects 0.000 description 3
- 230000010354 integration Effects 0.000 description 3
- 150000002739 metals Chemical class 0.000 description 3
- 229910010413 TiO 2 Inorganic materials 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 238000002360 preparation method Methods 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910002367 SrTiO Inorganic materials 0.000 description 1
- 238000005275 alloying Methods 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- 238000012423 maintenance Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 229910052758 niobium Inorganic materials 0.000 description 1
- 230000008520 organization Effects 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 238000005036 potential barrier Methods 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
- H01L21/02197—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides the material having a perovskite structure, e.g. BaTiO3
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/314—Inorganic layers
- H01L21/316—Inorganic layers composed of oxides or glassy oxides or oxide based glass
- H01L21/31691—Inorganic layers composed of oxides or glassy oxides or oxide based glass with perovskite structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/47—Schottky barrier electrodes
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
- H10B63/20—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having two electrodes, e.g. diodes
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/20—Multistable switching devices, e.g. memristors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
- H10N70/821—Device geometry
- H10N70/826—Device geometry adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
- H10N70/881—Switching materials
- H10N70/883—Oxides or nitrides
- H10N70/8833—Binary metal oxides, e.g. TaOx
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Semiconductor Memories (AREA)
Abstract
Nonvolatile memory device including amorphous alloy metal oxide layer and method of manufacturing the same are provided. A nonvolatile memory device may include a lower electrode, an oxide layer including an amorphous alloy metal oxide disposed on the lower electrode, and a diode structure disposed on the oxide layer.
Description
Technical field
The present invention relates to Nonvolatile memory devices; More particularly; Relate to the Nonvolatile memory devices that comprises amorphous alloy metal oxide layer, have the material of different crystal structure and form amorphous thin film through combination, it can and have the high speed of service by the low-power driving.
Background technology
In recent years, for the number of memory cells (being integration density (integrationdensity)) that increases unit are, improve the speed of service and can have been carried out big quantity research by the semiconductor storage that low-power drives.
Normally, semiconductor storage comprises a plurality of memory cell that connect through circuit.In representing the dynamic random access memory of semiconductor storage (DRAM), unit storage unit typically comprises a switch and a capacitor.This DRAM has the advantage of the high density of integration and the high speed of service.Yet when cutting off the electricity supply, DRAM has lost all storage data.
Even Nonvolatile memory devices such as flash memory device also can keep the data of being stored when power supply interrupts suddenly.Flash memory device has permanent characteristics, but has the lower integration density and the slower speed of service than volatile memory device.
Now, further investigate over against Nonvolatile memory devices such as magnetic random access storage (MRAM) device, ferroelectric random access memory (FRAM) device, phase-change random access storage (PRAM) device and resistance random storage (RRAM) device.
The characteristic (variable resistance characteristics) that the RRAM device uses the resistance of transition metal oxide (TMO) to change according to voltage.
Figure 1A example use the structure of the RRAM device of resistance variation material (resistence variationmaterial) with conventional structure.With reference to Figure 1A, but said RRAM device comprises substrate 10, hearth electrode 12, oxide skin(coating) 14 and the top electrode 16 of sequential cascade.Said hearth electrode 12 is formed by conventional electric conducting material with top electrode 16.Said oxide skin(coating) 14 is formed by the TMO with resistance variations (variable resistor) characteristic.Particularly, said oxide skin(coating) 14 can be by ZnO, TiO
2, Nb
2O
5, ZrO
2Or NiO forms.
Perovskite-RRAM device uses perovskite oxide as switching material group (switchingmaterial group), use PCMO (PrCaMnO
3) or Cr-STO (SrTiO
3) as oxide skin(coating), and use Schottky potential barrier strain (barrier deformation) principle, realized according to the storage characteristics that is applied to the polarity on the memory node (memory node).
The said RRAM device of use TMO has makes its switching characteristic as storage device.Yet, use the crystal film storage device of TMO to be confined to little-node (micro-node).
Fig. 2 A is to use the crystallization of the ZnO that X-ray diffraction (XRD) example forms (it is TMO) in the Si substrate.Referring to Fig. 2 A, Si (100) peak, ZnO (0002) peak and ZnO (10-12) peak have shown the crystallization process of ZnO.
Fig. 2 B is scanning electron microscopy (SEM) photo on ZnO surface, in Fig. 2 A instance its crystallization diagram.Referring to Fig. 2 B, when oxide skin(coating) 14 crystallizations of RRAM device, because particle is very big, so be difficult to realize having the storage device of uniform properties.
Summary of the invention
The invention provides the Nonvolatile memory devices that comprises as the amorphous alloy metal oxide layer of transition metal oxide (TMO) layer, thereby when using crystal film, overcome the limitation of little-node as resistive memory devices.
According to an aspect of the present invention, the Nonvolatile memory devices that comprises amorphous alloy metal oxide layer is provided, it comprises: hearth electrode; Be arranged in the oxide skin(coating) that comprises the amorphous alloy metal oxide on the said hearth electrode; With the diode structure body that is arranged on the said oxide skin(coating).
Said oxide skin(coating) can comprise first transition metal and second metal that has with the said first transition metal crystals with different characteristic.
Said first transition metal can be and is selected from a kind of among Ni, Ti, Hf, Zr, Zn, W, Co and the Nb.
Said second metal can be a kind of among Al and the In.
In said hearth electrode and the top electrode at least one can form Schottky-with said oxide skin(coating) be connected (Schottky-junction).
When said oxide skin(coating) was formed by n-type oxide, in hearth electrode and the top electrode one can be by being selected from Pt, Ir, Ru, and a kind of formation in the oxide of Pt, Ir and Ru.
When said oxide skin(coating) was formed by p-type oxide, one in said hearth electrode and the top electrode can be by a kind of formation the among Ti and the Ag.
Description of drawings
With reference to accompanying drawing, through describing its illustrative embodiments in detail, above-mentioned and other characteristics of the present invention and advantage will be more obvious, wherein:
Figure 1A diagram use the structure of resistance random storage (RRAM) device of variable-resistance material with conventional structure.
Fig. 2 A is to use the crystallization diagram of the ZnO that X-ray diffraction (XRD) forms (it is transition metal oxide (TMO)) on silicon base;
Fig. 2 B is scanning electron microscopy (SEM) photo on ZnO surface, and its crystallization chart has been described in Fig. 2 A;
Fig. 3 example according to the structure of the Nonvolatile memory devices that comprises amorphous alloy metal oxide layer of embodiment of the present invention;
Fig. 4 A is the oxide skin(coating) sample that forms for by InZnOx (0.5<x<1.5), the In that uses XRD to characterize
2O
3The crystallization diagram of-ZnO (IZO) film;
Fig. 4 B is the cross section of said IZO film and the SEM photo on surface, in Fig. 4 A example its crystallization diagram;
Fig. 5 illustrates the switching characteristic according to the Nonvolatile memory devices that comprises amorphous alloy metal oxide layer of embodiment of the present invention;
Fig. 6 A illustrates the wear properties according to the Nonvolatile memory devices that comprises amorphous alloy metal oxide layer of embodiment of the present invention; With
Fig. 6 B illustrates the retention characteristic according to the Nonvolatile memory devices that comprises amorphous alloy metal oxide layer of embodiment of the present invention.
Embodiment
Be described in greater detail with reference to the attached drawings the Nonvolatile memory devices that comprises according to amorphous alloy metal oxide layer of the present invention below, wherein shown illustrative embodiments of the present invention.In the accompanying drawings, for clarity, amplified the thickness of layer with the zone.
Fig. 3 diagram comprise structure according to the Nonvolatile memory devices of the amorphous alloy metal oxide layer of embodiment of the present invention.
Referring to Fig. 3, oxide skin(coating) 34 and top electrode 36 that said storage device comprises the substrate 30, hearth electrode 32 of sequential cascade, formed by amorphous substance.
For the said substrate 30 of optional component can be formed unrestrictedly by the material of the substrate that is used for common semiconductor device.Substrate 30 can be by Si, SiO
2, formation such as SiC.
Said amorphous oxide layer 34 can be formed by variable-resistance material, and is formed by the alloying metal oxide that comprises at least two kinds of metals with different crystal characteristic basically.At least a transition metal that can be in said two kinds of metals.Said transition metal is Ni, Ti, Hf, Zr, Zn, W, Co or Nb, and said transition metal oxide is NiO, TiO
2, HfO, ZrO, ZnO, WO
3, CoO or Nb
2O
5Other metals are the Al (Al that have the different crystal characteristic with said transition metal
2O
3) or In (In
2O
3).
Said hearth electrode and top electrode 32 and 36 are formed by electric conducting material.In said hearth electrode and the top electrode 32 and 36 at least one can form Schottky-with said oxide skin(coating) 34 and be connected.For example, when said oxide skin(coating) 34 is when being formed by n-type oxide such as InZnOx etc., at least one in said hearth electrode and top electrode 32 and 36 can be by a kind of formation the in the oxide that is selected from Pt, Ir, Ru and Pt, Ir and Ru.When said oxide skin(coating) 34 is when being formed by p-type oxide such as NiO etc., at least a can the formation in said hearth electrode and top electrode 32 and 36 by the material with low work content such as Ti or Ag.
As stated, the Nonvolatile memory devices that comprises amorphous alloy metal oxide layer of current execution mode comprises the said oxide skin(coating) 34 that is formed by the amorphous alloy metal oxide.
Fig. 4 A is the sample about the oxide skin(coating) 34 that is formed by InZnOx (0.5<x<1.5), the In that uses X-ray diffraction (XRD) to characterize
2O
3The crystallization diagram of-ZnO (IZO) film.Fig. 4 B is the cross section of said IZO film and the SEM photo on surface, in Fig. 4 A example its crystallization diagram.
Referring to Fig. 4 A, said IZO film is not complete crystallization, and it shows that the IZO film as said oxide skin(coating) 34 depositions is unbodied fully.Referring to the said SEM photo of Fig. 4 B, the cross section of said IZO film shows not to be to be completed into crystal grain with the material characteristics on surface, because said IZO film is unbodied.
Known IZO film does not have amorphous character in the ratio of whole compositions of In and Zn, but in the scope that consists of about 45at%-80at% of In, has amorphous character.Therefore, the IZO film can be used as the amorphous transition metal oxide that in the scope that consists of about 45at%-80at% of In, has amorphous character.
Fig. 5 illustrates the graph according to the switching characteristic of the Nonvolatile memory devices that comprises amorphous alloy metal oxide layer of embodiment of the present invention.Referring to Fig. 5; In test; The sample of the top electrode 36 that forms through the oxide skin(coating) 34 that forms to the hearth electrode 32 that forms by IrOx, by InZnOx with by IrOx; Little by little apply from-3V to+3V and turn back to-voltage of 3V ten times from+3V once more, the unit of measuring said oxide skin(coating) 34 is the current value of mA.
When sample is applied cumulatively-3V is during to the voltage of 0V, the unit of said oxide skin(coating) 34 is that the current value of mA increases, like first curve.When sample being applied cumulatively 0V to the voltage of+3V, the unit of said oxide skin(coating) 34 is that the current value of mA increases, like second curve.When sample is applied decreasingly+3V is during to the voltage of 0V, the unit of said oxide skin(coating) 34 is that the current value of mA reduces, like the 3rd curve.When sample being applied decreasingly 0V to the voltage of-3V, the unit of said oxide skin(coating) 34 is that the current value of mA reduces, like the 4th curve.
-2V is in the voltage range of 0V, and said oxide skin(coating) 34 has the different electric flow valuve in the first and the 4th curve.In the voltage range of 1V, said oxide skin(coating) 34 has the different electric flow valuve in the second and the 3rd curve at 0V.For example, when sample is applied-during 1V voltage, said oxide skin(coating) 34 has according to the resistance states of first curve or the 4th curve (resistance state).Said first and second curves are in low resistance state (LRS), and said third and fourth curve is in high resistance state (HRS).
Through repeating this test ten times, obtained consistent results, be satisfied therefore through the switching characteristic of using storage device.
Fig. 6 A illustrates the wear properties according to the Nonvolatile memory devices that comprises the amorphous alloy layer of embodiment of the present invention.The sample of the hearth electrode 32 that use is formed by IrOx, the oxide skin(coating) 34 that is formed by InZnOx and the top electrode 36 that formed by IrOx is tested.Referring to Fig. 6 A, when said oxide skin(coating) 34 is in LRS and HRS,, measure the resistance value of each sample through sample being applied pact-3V to+3V with turn back to-scanning method of the voltage of 3V 100 times from+3V once more.
Although this chart shows repeated scanning method, the resistance value of each sample under LRS and HRS is consistent.Use said amorphous transition metal oxide, the Nonvolatile memory devices of current execution mode has excellent reproducibility.
Fig. 6 B illustrates the retention characteristic that comprises according to the Nonvolatile memory devices of the amorphous alloy metal oxide layer of embodiment of the present invention.The sample of the hearth electrode 32 that use is formed by IrOx, the oxide skin(coating) 34 that is formed by InZnOx and the top electrode 36 that formed by IrOx is used for like Fig. 5 and the graphic test of 6A.Referring to Fig. 6 B,, reach 10 hours in about 100 ℃ of sample resistance values of measuring under LRS and HRS down in order to detect the retention characteristic of the Nonvolatile memory devices that comprises said amorphous alloy metal oxide layer.As a result, the resistance value of sample is consistent under LRS.The resistance value of sample has slight change under HRS, therefore is different from the resistance value of the sample under LRS.Therefore, the retention characteristic maintenance that comprises the Nonvolatile memory devices of said amorphous alloy metal oxide layer is stablized.
The oxide skin(coating) 34 that the Nonvolatile memory devices that comprises amorphous alloy metal oxide layer of current execution mode comprises hearth electrode 32, formed by amorphous alloy metal; With top electrode 36, and for using metal-insulator-metal type (MIM) storage device comprise as the oxide skin(coating) 34 of the transition metal of memory node.In said hearth electrode and the top electrode 32 and 36 at least one can form Schottky-with oxide skin(coating) 34 and be connected.
Said storage organization can be 1T (transistor)-1R (resistance) structure in the source electrode (source) that is connected to transistor arrangement or the drain electrode (drain), is connected to 1D (the diode)-1R structure on the diode structure or is the array structure of crosspoint form.
Use conventional DRAM preparation method can easily form the Nonvolatile memory devices that comprises amorphous alloy metal oxide layer of current execution mode.
The present invention has following advantage.
At first, because Nonvolatile memory devices has simple structure, so when Nonvolatile memory devices has array structure, use semiconductor fabrication method (like conventional DRAM preparation method) can easily form said Nonvolatile memory devices.
Secondly; Said memory node is formed by amorphous transition metal oxide; Owing to said memory node size reduce have high density, and have steady change (resistance variations) aspect the current value with respect to applying voltage, therefore can realize that said memory node is as reliable storage device.
Although reference example property execution mode shows especially and described the present invention, those skilled in the art are appreciated that the spirit and scope of the present invention that can make multiple change in form and details and not break away from claims and limited.
Claims (6)
1. comprise the Nonvolatile memory devices of amorphous alloy metal oxide layer, it comprises:
Hearth electrode;
Be arranged in the oxide skin(coating) that forms by the amorphous alloy metal oxide on the said hearth electrode; With
Be arranged in the diode structure body on the said oxide skin(coating),
Second metal that wherein said oxide skin(coating) comprises first transition metal and has the different crystal characteristic with said first transition metal.
2. the Nonvolatile memory devices of claim 1, wherein said first transition metal are to be selected from a kind of among Ni, Ti, Hf, Zr, Zn, W, Co and the Nb.
3. the Nonvolatile memory devices of claim 1, wherein said second metal are a kind of among Al and the In.
4. the Nonvolatile memory devices of claim 1, wherein at least one in hearth electrode and the top electrode forms Schottky-with said oxide skin(coating) and is connected.
5. the Nonvolatile memory devices of claim 4, wherein when said oxide skin(coating) is formed by n-type oxide, in hearth electrode and the top electrode one by being selected from Pt, Ir, Ru, and a kind of formation in the oxide of Pt, Ir and Ru.
6. claim 4 Nonvolatile memory devices, wherein when said oxide skin(coating) was formed by p-type oxide, one in said hearth electrode and the top electrode by a kind of formation the among Ti and the Ag.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR16224/06 | 2006-02-20 | ||
KR1020060016224A KR100723420B1 (en) | 2006-02-20 | 2006-02-20 | Non volatile memory device comprising amorphous alloy metal oxide layer |
Publications (2)
Publication Number | Publication Date |
---|---|
CN101192647A CN101192647A (en) | 2008-06-04 |
CN101192647B true CN101192647B (en) | 2012-05-02 |
Family
ID=38278732
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN2006101636363A Active CN101192647B (en) | 2006-02-20 | 2006-12-01 | Nonvolatile memory device including amorphous alloy metal oxide layer |
Country Status (4)
Country | Link |
---|---|
US (1) | US8455854B2 (en) |
JP (1) | JP4938489B2 (en) |
KR (1) | KR100723420B1 (en) |
CN (1) | CN101192647B (en) |
Families Citing this family (31)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4857014B2 (en) * | 2006-04-19 | 2012-01-18 | パナソニック株式会社 | Resistance change element and resistance change type memory using the same |
WO2008149605A1 (en) * | 2007-06-04 | 2008-12-11 | Nec Corporation | Variable resistance element and semiconductor device comprising the same |
KR101307253B1 (en) | 2007-06-29 | 2013-09-11 | 재단법인서울대학교산학협력재단 | Method for recording resistance switching element, method for manufacturing resistance switching element and resistance switching element having the same |
WO2009015298A2 (en) * | 2007-07-25 | 2009-01-29 | Intermolecular, Inc. | Nonvolatile memory elements |
WO2009057671A1 (en) * | 2007-10-30 | 2009-05-07 | National Institute Of Advanced Industrial Science And Technology | Rectifier and process for producing the rectifier |
JP5229892B2 (en) * | 2007-10-30 | 2013-07-03 | 独立行政法人産業技術総合研究所 | Rectifier element and manufacturing method thereof |
US7768812B2 (en) | 2008-01-15 | 2010-08-03 | Micron Technology, Inc. | Memory cells, memory cell programming methods, memory cell reading methods, memory cell operating methods, and memory devices |
US8034655B2 (en) | 2008-04-08 | 2011-10-11 | Micron Technology, Inc. | Non-volatile resistive oxide memory cells, non-volatile resistive oxide memory arrays, and methods of forming non-volatile resistive oxide memory cells and memory arrays |
US8211743B2 (en) | 2008-05-02 | 2012-07-03 | Micron Technology, Inc. | Methods of forming non-volatile memory cells having multi-resistive state material between conductive electrodes |
US8134137B2 (en) | 2008-06-18 | 2012-03-13 | Micron Technology, Inc. | Memory device constructions, memory cell forming methods, and semiconductor construction forming methods |
US9343665B2 (en) | 2008-07-02 | 2016-05-17 | Micron Technology, Inc. | Methods of forming a non-volatile resistive oxide memory cell and methods of forming a non-volatile resistive oxide memory array |
US8362454B2 (en) * | 2008-08-12 | 2013-01-29 | Industrial Technology Research Institute | Resistive random access memory having metal oxide layer with oxygen vacancies and method for fabricating the same |
US9385314B2 (en) | 2008-08-12 | 2016-07-05 | Industrial Technology Research Institute | Memory cell of resistive random access memory and manufacturing method thereof |
US8427859B2 (en) | 2010-04-22 | 2013-04-23 | Micron Technology, Inc. | Arrays of vertically stacked tiers of non-volatile cross point memory cells, methods of forming arrays of vertically stacked tiers of non-volatile cross point memory cells, and methods of reading a data value stored by an array of vertically stacked tiers of non-volatile cross point memory cells |
US8411477B2 (en) | 2010-04-22 | 2013-04-02 | Micron Technology, Inc. | Arrays of vertically stacked tiers of non-volatile cross point memory cells, methods of forming arrays of vertically stacked tiers of non-volatile cross point memory cells, and methods of reading a data value stored by an array of vertically stacked tiers of non-volatile cross point memory cells |
US8289763B2 (en) | 2010-06-07 | 2012-10-16 | Micron Technology, Inc. | Memory arrays |
US8351242B2 (en) | 2010-09-29 | 2013-01-08 | Micron Technology, Inc. | Electronic devices, memory devices and memory arrays |
US8759809B2 (en) | 2010-10-21 | 2014-06-24 | Micron Technology, Inc. | Integrated circuitry comprising nonvolatile memory cells having platelike electrode and ion conductive material layer |
US8526213B2 (en) | 2010-11-01 | 2013-09-03 | Micron Technology, Inc. | Memory cells, methods of programming memory cells, and methods of forming memory cells |
US8796661B2 (en) | 2010-11-01 | 2014-08-05 | Micron Technology, Inc. | Nonvolatile memory cells and methods of forming nonvolatile memory cell |
US9454997B2 (en) | 2010-12-02 | 2016-09-27 | Micron Technology, Inc. | Array of nonvolatile memory cells having at least five memory cells per unit cell, having a plurality of the unit cells which individually comprise three elevational regions of programmable material, and/or having a continuous volume having a combination of a plurality of vertically oriented memory cells and a plurality of horizontally oriented memory cells; array of vertically stacked tiers of nonvolatile memory cells |
US8431458B2 (en) | 2010-12-27 | 2013-04-30 | Micron Technology, Inc. | Methods of forming a nonvolatile memory cell and methods of forming an array of nonvolatile memory cells |
US8791447B2 (en) | 2011-01-20 | 2014-07-29 | Micron Technology, Inc. | Arrays of nonvolatile memory cells and methods of forming arrays of nonvolatile memory cells |
US8488365B2 (en) | 2011-02-24 | 2013-07-16 | Micron Technology, Inc. | Memory cells |
US8537592B2 (en) | 2011-04-15 | 2013-09-17 | Micron Technology, Inc. | Arrays of nonvolatile memory cells and methods of forming arrays of nonvolatile memory cells |
CN102214674B (en) * | 2011-06-10 | 2013-02-13 | 清华大学 | RRAM (resistive random access memory) with self-rectifying effect based on SOI (silicon on insulator) materials |
US8787066B2 (en) | 2011-10-26 | 2014-07-22 | Intermolecular, Inc. | Method for forming resistive switching memory elements with improved switching behavior |
US8866118B2 (en) | 2012-12-21 | 2014-10-21 | Intermolecular, Inc. | Morphology control of ultra-thin MeOx layer |
US9691910B2 (en) * | 2013-08-19 | 2017-06-27 | Idemitsu Kosan Co., Ltd. | Oxide semiconductor substrate and schottky barrier diode |
US9246094B2 (en) | 2013-12-26 | 2016-01-26 | Intermolecular, Inc. | Stacked bi-layer as the low power switchable RRAM |
US20160181517A1 (en) * | 2014-12-23 | 2016-06-23 | Silicon Storage Technology, Inc. | Geometrically Enhanced Resistive Random Access Memory (RRAM) Cell And Method Of Forming Same |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1641879A (en) * | 2004-01-14 | 2005-07-20 | 夏普株式会社 | Nonvolatile semiconductor memory device |
Family Cites Families (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3020681B2 (en) * | 1991-09-13 | 2000-03-15 | 三菱化学株式会社 | Die coating method and coating width adjusting jig used for the method |
JP3224604B2 (en) * | 1992-07-31 | 2001-11-05 | 三菱化学株式会社 | Die coater |
US5554564A (en) * | 1994-08-01 | 1996-09-10 | Texas Instruments Incorporated | Pre-oxidizing high-dielectric-constant material electrodes |
JP3850605B2 (en) * | 1999-10-29 | 2006-11-29 | 文雄 岡田 | Solid-phase excimer device and manufacturing method thereof |
JP3711539B2 (en) * | 2002-07-16 | 2005-11-02 | サミー株式会社 | Control device for gaming machine |
US6881351B2 (en) * | 2003-04-22 | 2005-04-19 | Freescale Semiconductor, Inc. | Methods for contacting conducting layers overlying magnetoelectronic elements of MRAM devices |
JP2005123361A (en) * | 2003-10-16 | 2005-05-12 | Sony Corp | Resistance change type nonvolatile memory and its manufacturing method, and method of forming resistance change layer |
JP2007536680A (en) * | 2004-05-03 | 2007-12-13 | ユニティ・セミコンダクター・コーポレーション | Nonvolatile programmable memory |
WO2006013819A1 (en) * | 2004-08-02 | 2006-02-09 | Matsushita Electric Industrial Co., Ltd. | Resistance change element and resistance change type memory using the same |
JP2006083071A (en) * | 2004-09-14 | 2006-03-30 | Takasago Internatl Corp | Solid preparation for fragrant cosmetic |
JP4516812B2 (en) * | 2004-09-15 | 2010-08-04 | 立川ブラインド工業株式会社 | Horizontal blind slat driving device and solar shading device lifting device |
US7863611B2 (en) * | 2004-11-10 | 2011-01-04 | Canon Kabushiki Kaisha | Integrated circuits utilizing amorphous oxides |
US7241631B2 (en) * | 2004-12-29 | 2007-07-10 | Grandis, Inc. | MTJ elements with high spin polarization layers configured for spin-transfer switching and spintronics devices using the magnetic elements |
-
2006
- 2006-02-20 KR KR1020060016224A patent/KR100723420B1/en active IP Right Grant
- 2006-12-01 CN CN2006101636363A patent/CN101192647B/en active Active
-
2007
- 2007-02-09 US US11/704,365 patent/US8455854B2/en active Active
- 2007-02-19 JP JP2007038209A patent/JP4938489B2/en active Active
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1641879A (en) * | 2004-01-14 | 2005-07-20 | 夏普株式会社 | Nonvolatile semiconductor memory device |
Also Published As
Publication number | Publication date |
---|---|
US20070257257A1 (en) | 2007-11-08 |
KR100723420B1 (en) | 2007-05-30 |
CN101192647A (en) | 2008-06-04 |
JP2007227922A (en) | 2007-09-06 |
JP4938489B2 (en) | 2012-05-23 |
US8455854B2 (en) | 2013-06-04 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN101192647B (en) | Nonvolatile memory device including amorphous alloy metal oxide layer | |
JP5154138B2 (en) | Variable resistance random access memory device with n + interface layer | |
JP4698630B2 (en) | Variable resistance memory device having buffer layer formed on lower electrode | |
CN101106171B (en) | Non-volatile memory device including variable resistance material | |
KR100718155B1 (en) | Non-volatile memory device using two oxide layer | |
KR101176542B1 (en) | Nonvolatile memory device and memory array | |
KR101275800B1 (en) | Non-volatile memory device comprising variable resistance material | |
Ielmini et al. | Thermochemical resistive switching: materials, mechanisms, and scaling projections | |
US7935953B2 (en) | Nonvolatile memory device, array of nonvolatile memory devices, and methods of making the same | |
KR100738116B1 (en) | Non-volatile memory device comprising variable resistance material | |
KR101783086B1 (en) | Composition of memory cell with resistance-switching layers | |
US8791444B2 (en) | Resistive random access memory (RRAM) using stacked dielectrics and method for manufacturing the same | |
JP5351363B1 (en) | Nonvolatile memory element and nonvolatile memory device | |
KR20130097139A (en) | Composition of memory cell with resistance-switching layers | |
KR102464065B1 (en) | switching device and method of fabricating the same, and resistive random access memory having the switching device as selection device | |
Ji | SiOx-based resistive switching memory integrated in nanopillar structure fabricated by nanosphere lithography |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
C14 | Grant of patent or utility model | ||
GR01 | Patent grant |