CN101194360B - 接插件及半导体装置 - Google Patents
接插件及半导体装置 Download PDFInfo
- Publication number
- CN101194360B CN101194360B CN2006800201220A CN200680020122A CN101194360B CN 101194360 B CN101194360 B CN 101194360B CN 2006800201220 A CN2006800201220 A CN 2006800201220A CN 200680020122 A CN200680020122 A CN 200680020122A CN 101194360 B CN101194360 B CN 101194360B
- Authority
- CN
- China
- Prior art keywords
- mentioned
- heat release
- insulating properties
- properties substrate
- island
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Landscapes
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
- Wire Bonding (AREA)
Abstract
Description
Claims (12)
Applications Claiming Priority (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005165801A JP4828164B2 (ja) | 2005-06-06 | 2005-06-06 | インタポーザおよび半導体装置 |
JP165801/2005 | 2005-06-06 | ||
JP240286/2005 | 2005-08-22 | ||
JP2005240286A JP5285204B2 (ja) | 2005-08-22 | 2005-08-22 | 半導体装置及び半導体装置製造用基板 |
PCT/JP2006/311099 WO2006132151A1 (ja) | 2005-06-06 | 2006-06-02 | インタポーザおよび半導体装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN101194360A CN101194360A (zh) | 2008-06-04 |
CN101194360B true CN101194360B (zh) | 2012-07-25 |
Family
ID=37559854
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN2006800201220A Active CN101194360B (zh) | 2005-06-06 | 2006-06-02 | 接插件及半导体装置 |
Country Status (2)
Country | Link |
---|---|
JP (1) | JP4828164B2 (zh) |
CN (1) | CN101194360B (zh) |
Families Citing this family (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2006132151A1 (ja) * | 2005-06-06 | 2006-12-14 | Rohm Co., Ltd. | インタポーザおよび半導体装置 |
JP4585416B2 (ja) * | 2005-09-22 | 2010-11-24 | 富士通株式会社 | 基板の反り低減構造および基板の反り低減方法 |
KR100839075B1 (ko) | 2007-01-03 | 2008-06-19 | 삼성전자주식회사 | 아이씨 패키지 및 그 제조방법 |
TW201029230A (en) | 2009-01-23 | 2010-08-01 | Everlight Electronics Co Ltd | Light emitting diode package |
US8897046B2 (en) | 2009-12-25 | 2014-11-25 | Rohm Co., Ltd. | DC voltage conversion module, semiconductor module, and method of making semiconductor module |
WO2011125546A1 (ja) | 2010-03-31 | 2011-10-13 | 京セラ株式会社 | インターポーザー及びそれを用いた電子装置 |
US8227840B2 (en) * | 2010-11-24 | 2012-07-24 | Nanya Technology Corp. | Integrated circuit device and method of forming the same |
KR20120082190A (ko) * | 2011-01-13 | 2012-07-23 | 삼성엘이디 주식회사 | 발광소자 패키지 |
US9554453B2 (en) | 2013-02-26 | 2017-01-24 | Mediatek Inc. | Printed circuit board structure with heat dissipation function |
TWI535346B (zh) * | 2014-12-10 | 2016-05-21 | 上海兆芯集成電路有限公司 | 線路基板和封裝結構 |
US9515017B2 (en) | 2014-12-18 | 2016-12-06 | Intel Corporation | Ground via clustering for crosstalk mitigation |
KR102486558B1 (ko) * | 2015-06-24 | 2023-01-10 | 삼성전자주식회사 | 회로 기판 및 이를 구비한 반도체 패키지 |
US9922920B1 (en) * | 2016-09-19 | 2018-03-20 | Nanya Technology Corporation | Semiconductor package and method for fabricating the same |
US9978731B1 (en) * | 2016-12-28 | 2018-05-22 | Samsung Electro-Mechanics Co., Ltd. | Fan-out semiconductor package module |
US10971461B2 (en) * | 2018-08-16 | 2021-04-06 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device and method of manufacture |
DE102019121191B4 (de) | 2018-08-16 | 2022-11-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | Halbleitervorrichtung und herstellungsverfahren |
CN111834329B (zh) * | 2020-06-30 | 2021-12-24 | 江苏长电科技股份有限公司 | 一种半导体封装结构及其制造方法 |
CN113224033A (zh) * | 2021-04-23 | 2021-08-06 | 中国电子科技集团公司第二十九研究所 | 一种基于bga封装的收发模块 |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH08139226A (ja) * | 1994-11-04 | 1996-05-31 | Sony Corp | 半導体回路装置及びその回路実装方法 |
JPH11121643A (ja) * | 1997-10-09 | 1999-04-30 | Hitachi Ltd | 半導体装置 |
JP2003297966A (ja) * | 2002-03-29 | 2003-10-17 | Mitsubishi Electric Corp | 半導体装置 |
JP2005057099A (ja) * | 2003-08-06 | 2005-03-03 | Renesas Technology Corp | 半導体装置およびその製造方法 |
JP2005101365A (ja) * | 2003-09-25 | 2005-04-14 | Kyocera Corp | 電子装置 |
JP2005101366A (ja) * | 2003-09-25 | 2005-04-14 | Kyocera Corp | 高周波モジュール |
-
2005
- 2005-06-06 JP JP2005165801A patent/JP4828164B2/ja active Active
-
2006
- 2006-06-02 CN CN2006800201220A patent/CN101194360B/zh active Active
Non-Patent Citations (2)
Title |
---|
JP特开2003-297966A 2003.10.17 |
JP特开平11-121643A 1999.04.30 |
Also Published As
Publication number | Publication date |
---|---|
CN101194360A (zh) | 2008-06-04 |
JP2006339596A (ja) | 2006-12-14 |
JP4828164B2 (ja) | 2011-11-30 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN101194360B (zh) | 接插件及半导体装置 | |
US8022532B2 (en) | Interposer and semiconductor device | |
US6201302B1 (en) | Semiconductor package having multi-dies | |
CN104064551B (zh) | 一种芯片堆叠封装结构和电子设备 | |
US10756075B2 (en) | Package-on-package type semiconductor package and method for manufacturing the same | |
US20030006494A1 (en) | Thin profile stackable semiconductor package and method for manufacturing | |
CN101582395B (zh) | 布线基板 | |
CN103620772A (zh) | 具有堆叠的面朝下连接的裸片的多芯片模块 | |
US7183652B2 (en) | Electronic component and electronic configuration | |
US20090039490A1 (en) | Mounting assembly of semiconductor packages prevent soldering defects caused by substrate warpage | |
US6335271B1 (en) | Method of forming semiconductor device bump electrodes | |
CN103811428A (zh) | 用于具有保护环的倒装芯片衬底的方法和装置 | |
US6441486B1 (en) | BGA substrate via structure | |
US6653219B2 (en) | Method of manufacturing bump electrodes and a method of manufacturing a semiconductor device | |
KR20100137183A (ko) | 반도체 패키지의 제조 방법 및 이에 의해 제조된 반도체 패키지 | |
JP5968713B2 (ja) | 半導体装置 | |
TWI397164B (zh) | 矽穿孔連通延伸之晶片封裝構造 | |
KR101037827B1 (ko) | 반도체 패키지 | |
KR20080051658A (ko) | 인쇄회로기판 및 그 제조 방법, 상기 인쇄회로기판을 갖는반도체 패키지 및 그 제조 방법 | |
KR101089647B1 (ko) | 단층 패키지 기판 및 그 제조방법 | |
JP4503611B2 (ja) | 半導体装置及びその製造方法 | |
JP2007059486A (ja) | 半導体装置及び半導体装置製造用基板 | |
CN221979451U (zh) | 存储器的芯片封装结构及存储装置 | |
KR101185857B1 (ko) | Bga 타입 스택 패키지 및 이를 이용한 멀티 패키지 | |
KR20100097845A (ko) | 범프 구조물 및 이를 갖는 반도체 패키지 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
C14 | Grant of patent or utility model | ||
GR01 | Patent grant | ||
TR01 | Transfer of patent right | ||
TR01 | Transfer of patent right |
Effective date of registration: 20200619 Address after: Rika Univ. Patentee after: Achilles technologies Address before: Kyoto Japan Patentee before: Rohm Co.,Ltd. |
|
TR01 | Transfer of patent right | ||
TR01 | Transfer of patent right |
Effective date of registration: 20201116 Address after: No.8, Lixing 6th Road, Xinzhu City, Xinzhu Science Industrial Park, Taiwan, China Patentee after: Taiwan Semiconductor Manufacturing Co.,Ltd. Address before: Rika Univ. Patentee before: Achilles technologies |