CN101083278A - Pressure resistant layer structure having dual-medium buried layer and SOI power device using the same - Google Patents
Pressure resistant layer structure having dual-medium buried layer and SOI power device using the same Download PDFInfo
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- CN101083278A CN101083278A CN 200610022120 CN200610022120A CN101083278A CN 101083278 A CN101083278 A CN 101083278A CN 200610022120 CN200610022120 CN 200610022120 CN 200610022120 A CN200610022120 A CN 200610022120A CN 101083278 A CN101083278 A CN 101083278A
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- 239000004065 semiconductor Substances 0.000 claims description 30
- 239000000758 substrate Substances 0.000 claims description 26
- 229910004298 SiO 2 Inorganic materials 0.000 claims description 6
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 claims description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 5
- 229920005591 polysilicon Polymers 0.000 claims description 5
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims 2
- 230000000694 effects Effects 0.000 abstract description 6
- 238000010438 heat treatment Methods 0.000 abstract description 5
- 230000005684 electric field Effects 0.000 description 20
- 238000010586 diagram Methods 0.000 description 11
- 230000015556 catabolic process Effects 0.000 description 9
- 238000002955 isolation Methods 0.000 description 7
- 239000000463 material Substances 0.000 description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- 239000011248 coating agent Substances 0.000 description 4
- 238000000576 coating method Methods 0.000 description 4
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 3
- 239000011810 insulating material Substances 0.000 description 3
- 239000012212 insulator Substances 0.000 description 3
- 229910052760 oxygen Inorganic materials 0.000 description 3
- 239000001301 oxygen Substances 0.000 description 3
- 238000013461 design Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 230000005855 radiation Effects 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 238000011982 device technology Methods 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 239000004576 sand Substances 0.000 description 1
- 238000005728 strengthening Methods 0.000 description 1
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Abstract
本发明提供了一种用于SOI功率器件的具有双介质埋层的耐压层结构，以及采用该耐压层结构的SOI功率器件，属于SOI功率器件耐压技术领域。本发明耐压层具有双介质埋层，两介质埋层之间设置中间层。本发明采用的耐压层及其采用该耐压层制作的功率器件，在相同介质埋层厚度的情况下可以提高耐压，而在相同的耐压情况下可以大幅度减小自热效应，从而制作高耐压的SOI功率器件。
The invention provides a pressure-resistant layer structure with double dielectric buried layers for SOI power devices, and an SOI power device adopting the voltage-resistant layer structure, belonging to the technical field of voltage-resistant SOI power devices. The pressure-resistant layer of the present invention has double dielectric buried layers, and an intermediate layer is arranged between the two dielectric buried layers. The pressure-resistant layer adopted in the present invention and the power device made of the voltage-resistant layer can improve the withstand voltage under the same thickness of the dielectric buried layer, and can greatly reduce the self-heating effect under the same withstand voltage, thereby Fabricate SOI power devices with high withstand voltage.
Description
Technical field
Have the SOI power device of two dielectric buried layers, belong to the semiconductor power device technology field, it is particularly related to SOI (Semiconductor On Insulator) the withstand voltage technical field of power device.
Background technology
Power device (be called for short SOI power device) with SOI (Silicon on Insulator) structure has higher operating rate and integrated level, better insulation property, stronger capability of resistance to radiation and do not have the controllable silicon self-locking effect, so the application of SOI power device in the VLSI field obtains extensive concern.The puncture voltage of SOI power device depends on the junior of lateral breakdown voltage and vertical puncture voltage.Ripe horizontal withstand voltage design principle of Si base device and technology are continued to use in the horizontal withstand voltage design of SOI power device, as RESURF principle and knot terminal technology.But, become a difficult point in the research of SOI lateral power because how the restriction of structure and technology improves the vertically withstand voltage of device.
The structure of typical conventional n type SOI LDMOS as shown in Figure 1,1 is substrate layer, 2 is dielectric layer (buried regions), 3 is active semiconductor layer (S layer), 4 is medium isolation, 5 is gate oxide, 6 is gate electrode, 7 is p (or n) trap, 8 is n
+(or p
+) source region, 9 is n
+(or p
+) drain region, 10 is drain electrode, 11 is the source electrode.Longitudinal electric field distributes as shown in Figure 2 under the N+, and vertical puncture voltage of conventional soi structure is mainly born by S layer and I layer, and according to Gauss theorem, the insulating barrier electric field when vertically puncturing is E
i=ε
sE
Cs/ ε
i≈ 3E
Cs, wherein, E
CsBe the critical breakdown electric field of S layer (Semiconductor layer), ε
sAnd ε
iBe respectively the dielectric constant of S layer and I layer (Insulator layer), thereby vertically withstand voltagely be
V
B0＝E
Cs(0.5t
s+3t
i) (1)
T wherein
iAnd t
sBe respectively the thickness of I layer and S layer.As seen, I layer electric field is subjected to the restriction of S layer breakdown electric field, and vertically withstand voltage increase with S layer thickness and I layer thickness improves, and the I layer of same thickness withstand voltage be 6 times of S layer, but be subjected to the restriction of device architecture and technology, S layer and I layer all can not be too thick.This is because the S layer is too thick, will bring difficulty for dielectric isolation; The I layer is too thick, and not only the process implementing difficulty is big, and is unfavorable for the device heat radiation.The visible list of references of the content of this respect: F.Udrea, D.Garner, K.Sheng, A.Popescu, H.T.Lim and W.I.Milne, " SOI power devices ", Electronics ﹠amp; Communication EngineeringJournal, pp27-40 (2000); Or, Warmerdan I.and Punt, W., " High-voltage SOI forsingle-chip power ", and Eur.Semicond., June 1999, pp19-20 (1999).Vertically withstand voltage in order to improve the SOI device, scholars have proposed a series of device architectures.As United States Patent (USP): Yasuhiro Uemoto, Katsushige Yamashlta, Takashi Miura, United states Patent, 6,531738, Mar.11,2003, as shown in Figure 3, between oxide layer 2 and top layer silicon 7, insert one deck p
+Withstand voltage layer 12 makes the drift region exhaust and p
+Layer not exclusively exhausts, and the p under the end of source
+Layer depletion region is than the p under the drain terminal
+Layer depletion region is wide, and this depletion layer that helps top layer silicon is expanded uniformly in the drift region, thereby improves device withstand voltage.This device architecture can be brought up to 400V from the 200V of conventional structure with puncture voltage.Document: N.Yasuhara, A.Nakagawa and K.Furukawa, " SOI device structures implementing 650V high voltage outputdevices on VLSIs ", IEDM Tech.Dig., pp141～144, (1991) then are to insert one deck n between oxide layer 2 and top layer silicon 3
+Withstand voltage layer 13, as shown in Figure 4, n
+Layer has shielded the influence of the high electric field of oxygen buried layer to the Si active layer when strengthening oxygen buried layer electric field strength, thereby avoids device to cross as far back as Si/SiO
2The Si flank attack at interface is worn, at t
s=20 μ m, t
iObtained the withstand voltage of 650V under the situation of=3 μ m.But withstand voltage in order effectively to improve, require p
+Layer and n
+Concentration height, the thin thickness of layer, and the drift region will satisfy the RESURF principle, so p
+Layer and n
+Layer thickness and concentration need accurately control, otherwise cause the surface to puncture in advance easily.Document: S.Merchant, E.Arnold, H.Baumgart, et al.Realization of high breakdown voltage (＞700V) in thin SOIdevice.In:Proc ISPSD, 1991,31-35 adopts ultra-thin drift region (t
s=0.1um) linear doping utilizes thin Si layer critical breakdown electric field significantly to increase and improves oxygen buried layer electric field and device withstand voltage, but end extremely low drift region concentration in source makes the source end form " focus ".Document: Luo Xiaorong etc., the voltage endurance of variable low k dielectric layer SOI high tension apparatus, semiconductor journal, 2006; 27 (5): 881-85 adopt low k dielectric to improve buried regions electric field and device withstand voltage as buried regions, but low k dielectric SOI and conventional cmos process compatible aspect runs into challenge.
Summary of the invention
The purpose of this invention provides a kind of pair of dielectric buried layer SOI pressure-resistance structure, makes power device on this structure, and it is withstand voltage to improve greatly than conventional structure SOI device withstand voltage; Simultaneously, under identical withstand voltage situation, self-heating effect is reduced.
For achieving the above object, the technical solution used in the present invention is as follows:
A kind of structure of voltage-sustaining layer with two dielectric buried layers, comprise substrate layer 1, dielectric buried layer 2,14, active semiconductor layer 3, it is characterized in that: dielectric buried layer has first dielectric layer 2 and second dielectric layer 14, be provided with intermediate layer 15 between described first dielectric layer 2 and second dielectric layer 14, the first dielectric layer opposite side links to each other with active semiconductor layer 3, and second dielectric layer, 14 opposite sides link to each other with substrate layer 1.
Described intermediate layer is polysilicon or germanium silicon.
Described two layer medium layer adopts SiO
2, Si
3N
4, also can adopt other insulating material.
Described two layer medium layer material adopts same material or foreign material.
A kind of SOI power device that adopts two dielectric buried layers, its Withstand voltage layer comprises substrate layer 1, dielectric layer 2,14, active semiconductor layer 3, it is characterized in that: dielectric layer has first dielectric layer 2 and second dielectric layer 14, be provided with intermediate layer 15 between described first dielectric layer 2 and second dielectric layer 14, the first dielectric layer opposite side links to each other with active semiconductor layer 3, and second dielectric layer, 14 opposite sides link to each other with substrate layer 1.
Described intermediate layer is polysilicon or germanium silicon.
Described two layer medium layer adopts SiO
2, Si
3N
4, also can adopt other insulating material.
Described two layer medium layer material adopts same material or foreign material.
A kind of described application with Withstand voltage layer of two dielectric buried layers at SOI LDMOS device.
A kind of described application with Withstand voltage layer of two dielectric buried layers at SOI IGBT device.
A kind of described application with Withstand voltage layer of two dielectric buried layers at SOI PN junction diode.
A kind of described application with Withstand voltage layer of two dielectric buried layers at the SOI lateral thyristor.
Beneficial effect of the present invention and operation principle
Be example with SOI LDMOS below, the working mechanism of above-mentioned Withstand voltage layer be elaborated:
Typical case shown in Figure 6 has the SOI LDMOS of two dielectric buried layers, thereby electric field action makes the intermediate layer upper and lower interface form electrostatic charge has improved dielectric layer, especially the electric field strength of second layer dielectric layer, thereby make it bear voltage to increase, thus improved device withstand voltage (as Fig. 7).And identical withstand voltage common SOI device just needs to increase the thickness of dielectric layer.Thereby the SOI power device with two dielectric buried layers that the present invention proposes not only improved withstand voltage properties, but also alleviated self-heating effect.
Description of drawings
Fig. 1 is conventional SOI LDMOS device architecture schematic diagram.
Wherein, 1 is substrate layer, and 2 is dielectric layer (buried regions), and 3 is active semiconductor layer (S layer), and 4 is medium isolation, and 5 is gate oxide, and 6 is gate electrode, and 7 is p (or n) trap, and 8 is n
+(or p
+) source region, 9 is n
+(or p
+) drain region, 10 is drain electrode, 11 is the source electrode.
Fig. 2 is the longitudinal electric field distribution schematic diagram of conventional SOI LDMOS device.
Fig. 3 has P
+The SOI LDMOS device architecture schematic diagram of resilient coating.
Wherein, 1 is substrate layer, and 2 is dielectric layer (buried regions), and 3 is active semiconductor layer (S layer), and 4 is medium isolation, and 5 is gate oxide, and 6 is gate electrode, and 7 is p (or n) trap, and 8 is n
+(or p
+) source region, 9 is n
+(or p
+) drain region, 10 is drain electrode, and 11 is the source electrode, and 12 is p
+Resilient coating.
Fig. 4 has n
+The SOI LDMOS device architecture schematic diagram of resilient coating.
Wherein, 1 is substrate layer, and 2 is dielectric layer (buried regions), and 3 is active semiconductor layer (S layer), and 4 is medium isolation, and 5 is gate oxide, and 6 is gate electrode, and 7 is p (or n) trap, and 8 is n
+(or p
+) source region, 9 is n
+(or p
+) drain region, 10 is drain electrode, and 11 is the source electrode, and 13 is n
+Resilient coating.
Fig. 5 is the soi structure with two dielectric buried layers of the present invention
1 is substrate layer, and 2 is first dielectric layer (buried regions), and 3 is active semiconductor layer (S layer), and 14 is second dielectric layer (buried regions), and 15 is the intermediate layer.
Fig. 6 is the SOI LDMOS device architecture schematic diagram with two dielectric buried layers of the present invention.
Wherein, 1 is substrate layer, and 2 is first dielectric layer (buried regions), and 3 is active semiconductor layer (S layer), and 4 is medium isolation, and 5 is gate oxide, and 6 is gate electrode, and 7 is p (or n) trap, and 8 is n
+(or p
+) source region, 9 is n
+(or p
+) drain region, 10 is drain electrode, and 11 is the source electrode, and 14 is second dielectric layer (buried regions), and 15 is the intermediate layer.
Fig. 7 is the longitudinal electric field distribution map with SOI LDMOS device of two dielectric buried layers of the present invention.
Two-dimentional isometric drawing when Fig. 8 a is conventional SOI LDMOS device breakdown.
Fig. 8 b is the two-dimentional isometric drawing when having the SOI LDMOS device breakdown of two dielectric buried layers of the present invention.
Among Fig. 8 between every adjacent two equipotential liness electrical potential difference be 15V.
Fig. 9 is the SOI IGBT device architecture schematic diagram with two dielectric buried layers of the present invention.
Wherein, 1 is substrate layer, and 2 is the ground floor dielectric layer, and 3 is active semiconductor layer (S layer), and 6 is gate electrode, and 7 is p (or n) trap, and 8 is n
+(or p
+) cathodic region, 9 is n
+(or p
+) anode region, 14 is second dielectric layer (buried regions), and 15 is the intermediate layer, and 17 is anode, and 18 is negative electrode, 19 is p (or n) trap.
Figure 10 is the SOI PN diode device structure schematic diagram with two dielectric buried layers of the present invention.
Wherein, 1 is substrate layer, and 2 is the ground floor dielectric layer, and 3 is active semiconductor layer (S layer), and 14 is second dielectric layer (buried regions), and 15 is the intermediate layer, and 20 is anode, and 21 is negative electrode, and 22 is p (or n) trap, and 23 is p
+(or n
+) anode region, 24 is n
+(or p
+) cathodic region.
Embodiment
The invention provides a kind of two dielectric buried layer SOI (Withstand voltage layer) structure that is used for power device, as shown in Figure 5, comprise substrate layer 1, dielectric buried layer 2,14, active semiconductor layer 3, it is characterized in that: dielectric buried layer has first dielectric layer 2 and second dielectric layer 14, be provided with intermediate layer 15 between described first dielectric layer 2 and second dielectric layer 14, the first dielectric layer opposite side links to each other with active semiconductor layer 3, and second dielectric layer, 14 opposite sides link to each other with substrate layer 1.
Its dielectric material of SOI power device with two dielectric buried layer layers can be SiO
2, Si
3N
4Or other insulating material; The material in intermediate layer can be polysilicon or germanium silicon.
SOI power device with two dielectric buried layers comprises the structure part of common power device it is characterized in that it also has above-mentioned pair of dielectric buried layer soi structure.Such power device comprises: two dielectric buried layer SOI LDMOS devices, two dielectric buried layer SOI IGBT, two dielectric buried layer SOI PN junction diode, two dielectric buried layer SOI PiN junction diode, two dielectric buried layer SOI lateral thyristor.
Be example with SOI LDMOS below, the working mechanism of above-mentioned Withstand voltage layer is elaborated.
Fig. 6 is the SOI LDMOS structural representation that a kind of typical case has two dielectric buried layers, the difference of it and conventional SOILDMOS (as Fig. 1) is to have increased by second dielectric layer 14, intermediate layer 15 is formed, thereby electric field action makes the intermediate layer upper and lower interface form electrostatic charge has improved the dielectric layer electric field, especially the electric field strength in the second layer medium, thereby make it bear the voltage increase, thereby improve device withstand voltage (as Fig. 7).And identical withstand voltage common SOI device just needs to increase the thickness of dielectric layer.Thereby the SOI power device with two dielectric buried layers that the present invention proposes has been alleviated self-heating effect.
Embodiment 1: the soi structure with two dielectric buried layers
Fig. 5 is the soi structure schematic diagram with two dielectric buried layers of the present invention.
As shown in Figure 5,1 is substrate layer, and 2 is first dielectric layer (buried regions), and 3 is active semiconductor layer (S layer), and 14 is second dielectric layer (buried regions), and 15 is the intermediate layer.Intermediate layer 15 is positioned between first dielectric layer (buried regions) 2 and second dielectric layer (buried regions) 14, and the first dielectric layer opposite side links to each other with active semiconductor layer 3, and second dielectric layer, 14 opposite sides link to each other with substrate layer 1.
Embodiment 2: the SOI LDMOS device architecture with two dielectric buried layers
Fig. 6 is the SOI LDMOS device architecture schematic diagram with two dielectric buried layers of the present invention, and Fig. 7 is the longitudinal electric field distribution map with 8OI LDMOS device of two dielectric buried layers of the present invention.As seen, the electric field on the dielectric layer 14 improves greatly than the electric field of conventional structure SOI LDMOS dielectric layer, thereby under the identical situation of dielectric buried layer thickness, the structure that the present invention proposes is withstand voltage to be improved greatly.Two-dimentional isopotential map when Fig. 8 a is conventional structure SOI LDMOS device breakdown.Fig. 8 b is the two-dimentional isopotential map when having the SOI LDMOS device breakdown of two dielectric buried layers of the present invention.Among Fig. 8 a and Fig. 8 b between two adjacent equipotential liness electromotive force differ 15V.And identical withstand voltage common SOI device just needs to increase the thickness of dielectric layer.Thereby the SOI power device with two dielectric buried layers that the present invention proposes not only improved withstand voltage properties, but also alleviated self-heating effect.
Shown in Fig. 6-8,1 is substrate layer, and 2 is first dielectric layer (buried regions), and 3 is active semiconductor layer (S layer), and 4 is medium isolation, and 5 is gate oxide, and 6 is gate electrode, and 7 is p (or n) trap, and 8 is n
+(or p
+) source region, 9 is n
+(or p
+) drain region, 10 is drain electrode, and 11 is the source electrode, and 14 is second dielectric layer (buried regions), and 15 is the intermediate layer.Intermediate layer 15 is positioned between first dielectric layer (buried regions) 2 and second dielectric layer (buried regions) 14, and the first dielectric layer opposite side links to each other with active semiconductor layer 3, and second dielectric layer, 14 opposite sides link to each other with substrate layer 1.
Embodiment 3: the SOI IGBT device architecture with two dielectric buried layers
Fig. 9 is the SOI IGBT device architecture schematic diagram with two dielectric buried layers of the present invention.As shown in Figure 9,1 is substrate layer, and 2 is the ground floor dielectric layer, and 3 is active semiconductor layer (S layer), and 6 is gate electrode, and 7 is p (or n) trap, and 8 is n
+(or p
+) cathodic region, 9 is n
+(or p
+) anode region, 14 is second dielectric layer (buried regions), and 15 is the intermediate layer, and 17 is anode, and 18 is negative electrode, 19 is p (or n) trap.Intermediate layer 15 is positioned between first dielectric layer (buried regions) 2 and second dielectric layer (buried regions) 14, and the first dielectric layer opposite side links to each other with active semiconductor layer 3, and second dielectric layer, 14 opposite sides link to each other with substrate layer 1.
Embodiment 4: the SOI PN diode device structure with two dielectric buried layers
Figure 10 is the SOI PN diode device structure schematic diagram with two dielectric buried layers of the present invention.As shown in figure 10,1 is substrate layer, and 2 is the ground floor dielectric layer, and 3 is active semiconductor layer (S layer), and 14 is second dielectric layer (buried regions), and 15 is the intermediate layer, and 20 is anode, and 21 is negative electrode, and 22 is p (or n) trap, and 23 is p
+(or n
+) anode region, 24 is n
+(or p
+) cathodic region.Intermediate layer 15 is positioned between first dielectric layer (buried regions) 2 and second dielectric layer (buried regions) 14, and the first dielectric layer opposite side links to each other with active semiconductor layer 3, and second dielectric layer, 14 opposite sides link to each other with substrate layer 1.
Claims (10)
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|---|---|---|---|
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|---|---|---|---|
| CN 200610022120 CN101083278A (en) | 2006-10-25 | 2006-10-25 | Pressure resistant layer structure having dual-medium buried layer and SOI power device using the same |
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|---|---|
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ID=38912677
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| CN103035728A (en) * | 2012-12-04 | 2013-04-10 | 上海华虹Nec电子有限公司 | Literally diffused metal oxide semiconductor (LDMOS) device applied to radio frequency field and manufacturing method thereof |
| CN103165678A (en) * | 2013-03-12 | 2013-06-19 | 电子科技大学 | Super junction lateral double-diffused metal-oxide semiconductor (LDMOS) device |
| CN104269441A (en) * | 2014-10-22 | 2015-01-07 | 桂林电子科技大学 | SOI voltage resistance structure with charge regions fixed at equal intervals and SOI power device |
| CN104659102A (en) * | 2015-02-12 | 2015-05-27 | 重庆大学 | SOI (silicon on insulator) voltage-resistant structure provided with partial composite buried layer |
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| CN103035728B (en) * | 2012-12-04 | 2015-10-14 | 上海华虹宏力半导体制造有限公司 | Be applied to LDMOS device and the manufacture method thereof of RF application |
| CN103035728A (en) * | 2012-12-04 | 2013-04-10 | 上海华虹Nec电子有限公司 | Literally diffused metal oxide semiconductor (LDMOS) device applied to radio frequency field and manufacturing method thereof |
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| CN103165678B (en) * | 2013-03-12 | 2015-04-15 | 电子科技大学 | Super junction lateral double-diffused metal-oxide semiconductor (LDMOS) device |
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| CN104269441A (en) * | 2014-10-22 | 2015-01-07 | 桂林电子科技大学 | SOI voltage resistance structure with charge regions fixed at equal intervals and SOI power device |
| CN104659102A (en) * | 2015-02-12 | 2015-05-27 | 重庆大学 | SOI (silicon on insulator) voltage-resistant structure provided with partial composite buried layer |
| CN105932062A (en) * | 2016-05-19 | 2016-09-07 | 杭州电子科技大学 | SOI LDMOS device with buried field plates |
| CN105932062B (en) * | 2016-05-19 | 2019-04-02 | 杭州电子科技大学 | It is a kind of with the SOI LDMOS device for burying oxygen field plate |
| CN111293163A (en) * | 2018-12-06 | 2020-06-16 | 上海新微技术研发中心有限公司 | Lateral diffusion metal oxide semiconductor field effect transistor |
| CN111293163B (en) * | 2018-12-06 | 2023-11-10 | 上海新微技术研发中心有限公司 | Laterally diffused metal oxide semiconductor field effect transistor |
| CN113270423A (en) * | 2021-05-08 | 2021-08-17 | 电子科技大学 | Radiation-resistant SOI device and manufacturing method thereof |
| CN113675274A (en) * | 2021-08-27 | 2021-11-19 | 电子科技大学 | Low Radiation Leakage High Voltage Double RESURF LDMOS Devices |
| CN113675274B (en) * | 2021-08-27 | 2023-04-25 | 电子科技大学 | Low-radiation leakage high-voltage Double RESURF LDMOS device |
| CN116525660A (en) * | 2023-07-03 | 2023-08-01 | 北京智芯微电子科技有限公司 | LDMOSFET device with vertical gate oxide structure and manufacturing method |
| CN116525660B (en) * | 2023-07-03 | 2023-09-12 | 北京智芯微电子科技有限公司 | LDMOSFET device with longitudinal gate oxide structure and manufacturing method |
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