CN101026412B - HS-SCCH channel coding device for high speed downlink packet access - Google Patents
HS-SCCH channel coding device for high speed downlink packet access Download PDFInfo
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Abstract
The encoding device for HS-SCCH channel makes the output data compact, reduces time delay, and raises circuit usage. The device includes first process circuit and second process circuit. The first process circuit includes the first convolutional coding unit (CCU), and first rate adaption unit (RAU). The first CCU encodes the input data; and RAU carries out rate matching or XOR process for the data, which are than outputted. Characters are that providing enable signal for the first process circuit to read next set of input data, the second process circuit includes following units: connected in sequence CRC16 circuit unit, second CCU, second RAU, counter monitoring unit, and time delay compensation unit located at one or several positions: in front of CRC16 circuit unit, between CRC16 circuit unit and second CCU, and between second CCU and second RAU.
Description
Technical field
The present invention relates to the third generation (3G) mobile communication system, relate in particular to the HS-SCCH channel coding device of the high speed downlink packet access of a kind of broadband CDMA system (WCDMA).
Background technology
Wideband CDMA (WCDMA) is one of main flow system of 3-G (Generation Three mobile communication system).Wherein the HSDPA of R5 version proposition (High Speed Downlink Packet Access, promptly high speed downlink packet inserts) technology has become current research focus.The HSDPA technology is to realize improving the of paramount importance technology of WCDMA network high-speed downlink message transmission rate, be that 3GPP puts forward in order to satisfy the asymmetric demand of up-downgoing data service in the R5 agreement, it can be on the basis that does not change the WCDMA system network architecture of having built, improve user's downstream data traffic speed greatly, can reach more than the 10Mbps, this technology is to improve a kind of important technology of downlink capacity and data service rate in the WCDMA networking.
In order to realize the functional characteristic of HSDPA, three down physical channel: HS-DSCH, HS-SCCH, HS-DPCCH in the 3GPP physical layer specification, have been introduced.The physical layer control signaling that wherein is used for decoding on HS-SCCH (Shared ControlChannel for HS-DSCH, i.e. shared control channel) the carrying HS-DSCH (High SpeedDownlink Shared Channel, high speed descending sharing channel).The control signaling is transmitted by the HS-SCCH message blocks, the duration of each HS-SCCH message blocks is 3 time slots, be divided into two parts, first's (the 1st time slot) carrying is to regularly responsive signaling, and these signalings are used for starting demodulating process to avoid the chip-level data buffering on time; Second portion (2 remaining time slots) carrying comprises the Cyclic Redundancy Check that detects HS-SCCH information and HARQ process information reliability to the insensitive signaling of timing.In order to protect the reliable transmission of signaling, this two parts signaling of HS-SCCH all uses the specific mask of terminal to carry out scrambling, so that whether the HS-SCCH channel that terminal judges receives is the message of issuing oneself.
The flow process of HS-SCCH chnnel coding is divided into: HS-SCCH chnnel coding time slot 1 process chart shown in Figure 1, HS-SCCH chnnel coding time slot 2,3 process charts shown in Figure 2, two separate processing of flow process.The input data are unit with UE (user equipment), be UE of single treatment, each UE input data comprises X1 (8bits bit wide), X2 (13bits bit wide), Xue (16bits bit wide), after parameter is finished encoding process, time slot 1 handling process is from 105 output 40bits bit streams, time slot 2,3 handling processes require the 40bits of 105 outputs to send out prior to 207 80bits that export from 207 output 80bits bit streams.Two paths of data should be able to be merged into a circuit-switched data on sequential, as shown in Figure 3.
101,103 branch roads and 102,104 branch roads are parallel processings.101 couples of input data X1 carry out 1/3 convolutional encoding to be handled; The 48bits data of 103 pairs 101 outputs are carried out rate-matched 1 and are handled; 102 couples of input data Xue carry out 1/2 convolutional encoding to be handled; The 48bits data of 104 pairs 102 outputs are carried out rate-matched 1 and are handled; 105 carry out XOR with the 40bits data of 103 40bits data of exporting and 104 outputs handles the last 40bits dateout that the back produces time slot 1 processing.
201 are merged into the 21bits data with X1 and X2 data, the X1 data preceding X2 data after; The 21bits data of 202 pairs of inputs are carried out CRC16 and are handled; The CRC16 result of 203 pairs of outputs carries out by turn inverted sequence and handles, as original data be C15, C14 ... C0}, become after the inverted sequence C0, C1 ... C15}; 204 carry out by turn XOR with the result after Xue data and the CRC16 inverted sequence handles; 205 outputs with data X2 and 204 are merged into the 29bits data, X2 preceding 204 output after; 206 pairs 205 dateout is carried out 1/3 convolutional encoding and is handled; 207 pairs 206 dateout is carried out rate-matched 2 and is handled the last 80bits dateout that the back produces time slot 2,3 processing.
Existing HS-SCCH channel-encoded data output timing as shown in Figure 4, because the requirement difference of Fig. 1, dateout bit number difference different with the processing time of each unit module among Fig. 2, output timing, therefore there is following defective in the HS-SCCH channel coding device according to the commonsense method design as can be seen:
1, because processing time+time slot 1 data transmitting time＞time slot 2,3 data processing time of time slot 1 data, so, in order to guarantee that time slot 1 data are sent completely earlier, after finishing, time slot 2,3 data processing need to wait for that time slot 1 data are sent completely, promptly need wait for the T1 time among Fig. 4;
2, do not have influence on the processing of second UE data for the result that guarantees previous UE data, the data that then need just begin to read next UE after previous UE finishes dealing with and is sent completely are handled, but present HS-SCCH channel coding device exists the data of sending at last to merge the back sequential problem is at interval arranged between different UEs, promptly the T2 sequential among Fig. 4 at interval.
Above-mentioned 2 defectives cause last dateout not compact, and total data are exported time-delay and become big, realize that the percentage of circuit utilization of the method is not high yet, and this can not meet the demands to the high occasion of data processing delay requirement.
Summary of the invention
Technical problem to be solved by this invention provides the HS-SCCH channel coding device that a kind of high speed downlink packet inserts, and makes dateout compactness, total data output time-delay reduce, improve the utilance of circuit.
In order to solve the problems of the technologies described above, the invention provides the HS-SCCH channel coding device that a kind of high speed downlink packet inserts, comprise first treatment circuit and second treatment circuit, described first treatment circuit comprises the first convolution coding unit and first rate matching unit, the input data are encoded through the first convolution coding unit, output after the first rate matching unit carries out rate-matched and XOR processing is characterized in that again
The duration of a data block is three time slots on the described HS-SCCH channel, and described first treatment circuit is used to finish the processing and the output of the first time slot data, and described second treatment circuit is used to finish the processing and the output of second and third time slot data;
Described second treatment circuit provides the enable signal that reads next group input data for described first treatment circuit, comprise the CRC16 circuit unit, the second convolutional encoding unit, the second rate-matched unit sum counter monitoring means that link to each other successively, and also be connected with the compensation of delay unit: before the described CRC16 circuit unit, between the CRC16 circuit unit and the second convolutional encoding unit, between the second convolutional encoding unit and the second rate-matched unit in one or several following position;
Described compensation of delay unit, be used to make second treatment circuit to processing time of input data equal first treatment circuit to the processing time of input data and first processing circuit processes after data output time sum;
Described counter monitoring means is used to monitor the output of the second treatment circuit data, control the reception of first treatment circuit and second treatment circuit input data, the input data that make the previous cycle are through first treatment circuit, when the output of second processing circuit processes is finished, and the data of first treatment circuit of following one-period are also just finished dealing with and begun output.
Further, said apparatus also can have following characteristics: described compensation of delay unit makes second treatment circuit, 5 clock cycle of time-delay processing time to the input data.
Further, said apparatus also can have following characteristics: described compensation of delay unit is a shift register.
Further, said apparatus also can have following characteristics: described counter monitoring means is used to monitor the output of the second treatment circuit data, the reception of controlling first treatment circuit and second treatment circuit input data is meant, described counter monitoring means is monitored the transmitting counter of the second treatment circuit dateout, when monitor value that this Counter Value equals to preset, described counter monitoring means sends the signal that reads of read next cycle input data, notifies described first treatment circuit and the second treatment circuit reading of data.
Further, said apparatus also can have following characteristics: if the transmitting counter of the described second treatment circuit dateout is a down counter, the default monitor value of then described counter monitoring means is 35; If the transmitting counter of the described second treatment circuit dateout is for adding counter, monitor value default in the then described counter monitoring means is 45.
Compared with prior art, the present invention has improved the HS-SCCH channel coding device.Under the prerequisite that does not increase circuit complexity, make whole coding output bit flow sequential compact more, the predictability of sequential strengthens, whole data output time-delay reaches minimum, has improved the utilance of circuit, makes that designing the strict more device of delay requirement according to the present invention becomes possibility.
Description of drawings
Fig. 1 is existing HS-SCCH chnnel coding time slot 1 process chart;
Fig. 2 is existing HS-SCCH chnnel coding time slot 2,3 process charts;
Fig. 3 is the sequential chart that the bit stream after time slot 1 and time slot 2,3 are handled is merged into the output of one road bit stream;
Fig. 4 handles sequential chart for existing HS-SCCH channel coding device;
Fig. 5 is used for the HS-SCCH channel coding device figure that high speed downlink packet inserts for present embodiment;
Fig. 6 is the cut-away view of present embodiment time slot 2,3 treatment circuits;
Fig. 7 is the data output timing diagram after present embodiment HS-SCCH channel coding device is optimized.
Embodiment
The present invention is further detailed explanation below in conjunction with the drawings and specific embodiments.
The HS-SCCH channel coding device that the high speed downlink packet that is used for present embodiment inserts as shown in Figure 5, comprise time slot 1 treatment circuit (hereinafter referred to as first treatment circuit) and time slot 2,3 treatment circuits (hereinafter referred to as second treatment circuit), second treatment circuit provides the enable signal that reads next group input data for first treatment circuit, wherein:
First treatment circuit 501 is used for finishing the HS-SCCH chnnel coding first time slot data and (comprises X1 and X
UE) processing and output, comprise the first convolution coding unit and first rate matching unit, the input data encodes through the first convolution coding unit, carry out exporting after rate-matched and XOR are handled through the first rate matching unit again;
Second treatment circuit 502 is used for finishing second and third time slot data of HS-SCCH chnnel coding and (comprises X1, X2 and X
UE) handle and output, and the reception of controlling first treatment circuit and the input data of self, comprise the CRC16 circuit unit, the second convolutional encoding unit, the second rate-matched unit, also comprise compensation of delay unit sum counter monitoring means, CRC16 circuit unit wherein, the second convolutional encoding unit, the second rate-matched unit sum counter monitoring means links to each other successively, described compensation of delay unit is before the CRC16 circuit unit or between the CRC16 circuit unit and the second convolutional encoding unit, perhaps between the second convolutional encoding unit and the second rate-matched unit; The second treatment circuit internal structure as shown in Figure 6, wherein said CRC16 circuit unit comprises CRC16 circuit, inverse sequential circuit, NOR gate circuit and merging circuit by turn, handling process is existing the description in background technology, repeats no more herein;
Described compensation of delay unit, be used to make second treatment circuit to processing time of input data equal first treatment circuit to the processing time of input data and first processing circuit processes after data output time sum;
Described counter monitoring means, be used to monitor the output of the second treatment circuit data, control the reception of first treatment circuit and second treatment circuit input data, the input data (as a UE) in previous cycle are exported after first treatment circuit, second processing circuit processes when finishing, and the input data of following one-period begin output after treatment;
Present embodiment HS-SCCH channel coding device also comprises an applications circuit 503, be used to this device provide first treatment circuit and second treatment circuit input signal, provide the outside enable signal of control first treatment circuit and the second treatment circuit work, and the dateout of receiving circuit after handling.
If the input data are unit with UE, be UE of single treatment, each UE input data comprises X1 (8bits bit wide), X2 (13bits bit wide), Xue (16bits bit wide), as shown in Figure 1, 2,101 need 16 clock cycle to finish processing, 103 add 1 clock cycle of 105 needs finishes processing, 102 need 24 clock cycle to finish processing, 104 add 1 clock cycle of 105 needs finishes processing, get the longest branch road 102,104 branch roads of processing time, the processing procedure of such first treatment circuit just needs 25 clock cycle; 201 processing times are very short, can ignore; 202 need 21 clock cycle to finish processing, 203 add 204 adds 1 clock cycle of 205 needs and finishes processing, 206 need 37 clock cycle to finish processing, and 207 need 1 clock cycle to finish processing, and such second processing circuit processes process needs 60 clock cycle altogether.This shows, the processing time of first treatment circuit (25 clock cycle) is compared with the processing time (60 clock cycle) of second treatment circuit with the first treatment circuit data transmitting time (40 clock cycle) sum, differ 5 clock cycle, therefore the compensation of delay that increases by 5 clock cycle in the processing procedure of second treatment circuit can make second treatment circuit that the processing time of input data is equaled first treatment circuit to the processing time of input data and the time sum of dateout, like this when the first treatment circuit output bit flow is sent completely, the second treatment circuit output bit flow just begins to send, thereby has eliminated the T1 stand-by period among Fig. 4.
Described compensation of delay unit can adopt the method for inserting 5 grades of shift registers to increase by 5 processing times clock cycle, promptly in as shown in Figure 6 position, carrying out compensation of delay before the CRC16 computing is because this position is the place that serial bit stream begins to import, deal with fairly simple, in other embodiments, also can be between merge cells 606 and 1/3 convolutional encoding unit 607, perhaps can be in Fig. 6 insert the compensation of delay unit between 1/3 convolutional encoding unit 607 and the rate-matched unit 608, as long as guarantee the operate as normal of circuit.Perhaps can also adopt a plurality of compensation of delay unit to realize, as adopt 2 compensation of delay unit, a compensation of delay unit is the two-stage shift register, another compensation of delay unit is three grades of shift registers, two compensation of delay unit can place above-mentioned position respectively, as long as guarantee to increase by 5 clock cycle on the data processing time of second treatment circuit.When this compensation of delay unit is between 1/3 convolutional encoding unit 607 and rate-matched unit 608,, therefore need 15 registers to realize the time-delay of 5 clock cycle because the rate-matched unit receives data in the mode of each clock cycle 3bits.
Described input data X1 is made up of 8 bits, wherein preceding 7 bits are the map information (Channelization-code-set information) of HS_PDSCH channel code set, and back 1 bit is modulation system information (Modulation scheme information); Described input data X2 is made up of 13 bits, wherein preceding 6 bits are transport block size information (Transport-block size information), 3 bits subsequently are for mixing automatic retransmission information (Hybrid-ARQ process information), 3 bits subsequently are redundant and constellation version information (Redundancy and constellation version) again, and last 1 bit is new data indication information (New data indicator); Described input data Xue is made up of 16 bits, is the wireless network identification information (UE identity) of subscriber equipment.Being defined in " 3GPP TS 25.212V5.9.0 (2004-06) " of above-mentioned data X1, X2 and Xue all can be found.
As previously mentioned, the processing time of first treatment circuit 501 is 25 clock cycle in the present embodiment, adding necessary hardware processing expenditure such as the needed handshake procedure of next UE parameter request is 10 clock cycle, therefore, 35 clock cycle are read next UE data before the second treatment circuit dateout is sent completely, can be so that the data of first treatment circuit of next UE be also just finished dealing with and are begun serial and send when data just have been sent completely after second processing circuit processes of previous UE, the data transmission procedure of previous like this UE just can well be connected with the data transmission procedure of a back UE, T2 sequential among Fig. 4 is eliminated at interval, becomes compact on the sequential.
When circuit is realized, increase a counter monitoring means in second treatment circuit 502, be used to monitor the second treatment circuit dateout transmitting counter, and the reception of controlling first treatment circuit and second treatment circuit input data, a default value M in the counting monitoring means, when the value of the second treatment circuit dateout transmitting counter equates with the M value, the counter monitoring means sends the signal that reads of read next UE parameter, controls the reception of first treatment circuit 501, second treatment circuit, 502 next UE data.
Described fixed value M is different and different according to the second treatment circuit dateout transmitting counter implementation, for example, if this counter is a down counter, the initial value of counter is 80 before sending first Bit data, this value of Bit data of later every transmission will subtract 1, when this value reduces to 0, the data of 80 bits just are sent completely, then the M value in the counter monitoring means can be made as 35, when the value that monitors counter when monitoring means equals 35, observation circuit sends the signal that reads of read next UE data, the data of notifying first treatment circuit 501 and second treatment circuit 502 can read next UE, whole then device begin to read next UE data and carry out new round processing when continuing to send the data of previous UE after second processing circuit processes; Otherwise, be one as if this counter and add counter, then the M value can be made as 45, and implementation and said process are similar, repeat no more here.
The present invention is in second treatment circuit, by T1 stand-by period and the T2 sequential interval among the compensation of delay unit sum counter monitoring means elimination Fig. 4 that increases shift register, obtain the sequential after the optimization shown in Figure 7, make HS-SCCH chnnel coding flow process dateout compact more, total data output time-delay is little, has improved the utilance of circuit.
Such scheme can be applied to fully realize with the FPGA hardware mode in the HSDPA system, accomplish real-time processing.
The front provides the description of detailed embodiment, so that any technical staff of this area can use or utilize the present invention.Various modifications to these embodiment are conspicuous to those skilled in the art.Thereby, the embodiment shown in the invention is not restricted to here, and the wide region of principle that should disclose and new feature according to meeting here.
Claims (5)
1. the HS-SCCH channel coding device that inserts of a high speed downlink packet, comprise first treatment circuit and second treatment circuit, described first treatment circuit comprises the first convolution coding unit and first rate matching unit, the input data are encoded through the first convolution coding unit, output after the first rate matching unit carries out rate-matched and XOR processing again, it is characterized in that
The duration of a data block is three time slots on the described HS-SCCH channel, and described first treatment circuit is used to finish the processing and the output of the first time slot data, and described second treatment circuit is used to finish the processing and the output of second and third time slot data;
Described second treatment circuit provides the enable signal that reads next group input data for described first treatment circuit, comprise the CRC16 circuit unit, the second convolutional encoding unit, the second rate-matched unit sum counter monitoring means that link to each other successively, and also be connected with the compensation of delay unit: before the described CRC16 circuit unit, between the CRC16 circuit unit and the second convolutional encoding unit, between the second convolutional encoding unit and the second rate-matched unit in one or several following position;
Described compensation of delay unit, be used to make second treatment circuit to processing time of input data equal first treatment circuit to the processing time of input data and first processing circuit processes after data output time sum;
Described counter monitoring means is used to monitor the output of the second treatment circuit data, control the reception of first treatment circuit and second treatment circuit input data, the input data that make the previous cycle are through first treatment circuit, when the output of second processing circuit processes is finished, and the data of first treatment circuit of following one-period are also just finished dealing with and begun output.
2. HS-SCCH channel coding device as claimed in claim 1 is characterized in that, described compensation of delay unit makes second treatment circuit, 5 clock cycle of time-delay processing time to the input data.
3. HS-SCCH channel coding device as claimed in claim 1 is characterized in that, described compensation of delay unit is a shift register.
4. HS-SCCH channel coding device as claimed in claim 1, it is characterized in that, described counter monitoring means is used to monitor the output of the second treatment circuit data, the reception of controlling first treatment circuit and second treatment circuit input data is meant, described counter monitoring means is monitored the transmitting counter of the second treatment circuit dateout, when monitor value that this Counter Value equals to preset, described counter monitoring means sends the signal that reads of read next cycle input data, notifies described first treatment circuit and the second treatment circuit reading of data.
5. HS-SCCH channel coding device as claimed in claim 4 is characterized in that, if the transmitting counter of the described second treatment circuit dateout is a down counter, the default monitor value of then described counter monitoring means is 35; If the transmitting counter of the described second treatment circuit dateout is for adding counter, monitor value default in the then described counter monitoring means is 45.
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| SG11201811700XA (en) | 2016-07-01 | 2019-01-30 | Guangdong Oppo Mobile Telecommunications Corp Ltd | Method for signal transmission, network device, and terminal device |
| CN107959522B (en) * | 2017-10-18 | 2021-07-20 | 中国电子科技集团公司电子科学研究院 | Inter-satellite communication method, space-based backbone network and computer storage medium |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1430361A (en) * | 2001-12-30 | 2003-07-16 | 华为技术有限公司 | Data transmission control method of downgoing high speed shared channel in high speed data insertion system |
| EP1628431A2 (en) * | 2004-08-16 | 2006-02-22 | Fujitsu Limited | Mobile station for W-CDMA |
| CN1868158A (en) * | 2003-10-09 | 2006-11-22 | 艾利森电话股份有限公司 | Adaptive threshold for HS-SCCH Part 1 decoding |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1430361A (en) * | 2001-12-30 | 2003-07-16 | 华为技术有限公司 | Data transmission control method of downgoing high speed shared channel in high speed data insertion system |
| CN1868158A (en) * | 2003-10-09 | 2006-11-22 | 艾利森电话股份有限公司 | Adaptive threshold for HS-SCCH Part 1 decoding |
| EP1628431A2 (en) * | 2004-08-16 | 2006-02-22 | Fujitsu Limited | Mobile station for W-CDMA |
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Effective date of registration: 20151022 Address after: Dameisha Yantian District of Shenzhen City, Guangdong province 518085 Building No. 1 Patentee after: SHENZHEN ZTE MICROELECTRONICS TECHNOLOGY CO., LTD. Address before: 518057 Nanshan District high tech Industrial Park, Guangdong, South Road, science and technology, ZTE building, legal department Patentee before: ZTE Corporation |
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Application publication date: 20070829 Assignee: Xi'an Chris Semiconductor Technology Co. Ltd. Assignor: SHENZHEN ZTE MICROELECTRONICS TECHNOLOGY CO., LTD. Contract record no.: 2019440020036 Denomination of invention: HS-SCCH channel coding device for high speed downlink packet access Granted publication date: 20100519 License type: Common License Record date: 20190619 |