CN100557808C - Image sensor for reducing dark current and manufacturing method thereof - Google Patents

Abstract

An image sensor comprising: a substrate region having a first conductivity type; a photodiode region having a second conductivity type in the substrate; a photodiode region located on a surface of the substrate and above the photodiode region a hole accumulation device (HAD) region of the first conductivity type; and a transfer gate over the substrate surface adjacent to the HAD region. The image sensor further includes: a first channel region of a first conductivity type in the substrate aligned under the transfer gate; a second channel region of the second conductivity type between the transfer gate and the first channel region; and a floating diffusion region in the substrate in electrical contact with the second channel region. A method of manufacturing an image sensor is also disclosed.

Description

Image sensor for reducing dark current and manufacturing method thereof

technical field

Generally, the present invention relates to image sensors. In particular, the present invention relates to an image sensor that reduces dark current by configuration, and a method of manufacturing an image sensor that reduces dark current.

Background technique

Certain types of image sensors use photodiodes to collect incoming light and convert it into electrical charges that can be image-processed. Examples include charge-coupled device (CCD) image sensors and complementary metal-oxide-semiconductor (CMOS) image sensors (CIS), see Figures 1 and 2, respectively. The CCD sensor in Figure 1 is typically constructed from an array of photodetectors electrically connected to a vertical CCD that acts as an analog shift register. The vertical CCD powers the horizontal CCD, which in turn drives the output amplifier. In contrast, the CIS device in FIG. 2 features an array of photodetectors with access devices (eg, transistors) for connecting wordlines and bitlines. The word lines are connected to a row decoder circuit, and the bit lines are connected to the column decoder circuit through column amplifiers. As shown, the column amplifiers drive the output amplifiers. The construction of CIS devices is similar to that of CMOS memory devices.

One disadvantage of the photodiode employed is related to its tendency to accumulate charge in the absence of incident light. This result is often referred to as "dark current". Dark current from the photodiode can appear as "white" pixels in the processed image, reducing picture quality.

Dark current is usually caused by many different factors, including plasma damage, stress, implant damage, wafer defects, electric fields, etc. However, one particularly important source of dark current is the dangling silicon bonds present on the surface of the silicon substrate of the image sensor. At relatively high thermal ranges, these dangling silicon bonds generate negative charges that the photodiode can accumulate even in the absence of incident light. Such high heat ranges can occur, for example, when cell phones with image sensors are used for extended periods of time.

There is a general need in the art for image sensors that exhibit reduced dark current, for example, caused by dangling silicon bonds at the surface of a silicon substrate.

Contents of the invention

According to one aspect of the present invention, the provided image sensor includes: a substrate; a photodiode region located in the substrate; a hole accumulation device located on the surface of the substrate and above the photodiode region (HAD) region; a transfer gate on the substrate surface adjacent to the HAD region; a first channel region in the substrate and aligned below the transfer gate; a second channel region in the substrate between the transfer gate and the first channel region; and a floating diffusion region in the substrate in electrical contact with the second channel region .

According to another aspect of the present invention, an image sensor is provided, which includes an active pixel array and a CMOS control circuit connected to the active pixel array. The active pixel array includes a pixel matrix, and each pixel includes: a substrate; a photodiode region located in the substrate; holes located on the surface of the substrate and above the photodiode region an accumulation device (HAD) region; a transfer gate on the substrate surface adjacent to the HAD region; a first channel region in the substrate and aligned below the transfer gate ; a second channel region located in the substrate between the transfer gate and the first channel region; and a floating diffusion region located in the substrate, which is connected to the second channel region electrical contact.

According to another aspect of the present invention, the provided image sensor includes: a substrate; a photodiode region located in the substrate; a hole accumulator located on the surface of the substrate and above the photodiode region a device (HAD) region; a transfer gate located above the substrate surface adjacent to the HAD region; a first channel region located in the substrate and below the transfer gate; located on the substrate on the bottom surface, a second channel region between the transfer gate and the first channel region; and, a buried channel charge-coupled device (BCCD) region in the substrate, wherein the BCCD region is connected to the The second channel region is in electrical contact.

According to yet another aspect of the present invention, there is provided an image sensor circuit including a plurality of pixels operatively connected to a charge-coupled device (CCD). Each pixel includes: a substrate; a photodiode region located in the substrate; a hole accumulation device (HAD) region located on the surface of the substrate and above the photodiode region; A transfer gate adjacent to the HAD region above the bottom surface; a first channel region located in the substrate and below the transfer gate; located on the substrate surface between the transfer gate and the first channel region a second channel region between the channel regions; and, a buried channel charge coupled device (BCCD) region in the substrate, wherein the BCCD region is in electrical contact with the second channel region.

According to another aspect of the present invention, the provided method of manufacturing an image sensor includes: implanting impurities into a substrate to define a first channel region extending from a surface of the substrate to a first depth; injecting impurities into the substrate implanting impurities into the surface of the bottom to define a second channel region, which is located above the first channel region and extends from the substrate surface to a second depth; above the substrate surface, and at the forming a transfer gate electrode over the first and second channel regions; implanting impurities into the substrate to define a hole accumulation device (HAD) region extending from a surface of the substrate to a third depth, and adjacent to the gate electrode; implanting impurities into the substrate to define a photodiode region buried in the substrate and extending from the substrate surface to a fourth depth; and, injecting impurities into the substrate Impurities are implanted into the bottom to define a diffusion region in electrical contact with the second channel region, wherein the HAD region is located above the photodiode region.

Description of drawings

These and other aspects and features of the present invention will become apparent from the following detailed description with reference to the accompanying drawings, in which:

Fig. 1 is a schematic block diagram of a charge-coupled device (CCD) image sensor;

2 is a schematic block diagram of a complementary metal oxide semiconductor (CMOS) image sensor (CIS);

Fig. 3 is a schematic block diagram of a CIS device according to an embodiment of the present invention;

Fig. 4 is the equivalent circuit diagram of the photodetector element of the CIS device in Fig. 3;

Figure 5 is a schematic cross-sectional view of a portion of the photodetector element of Figure 4;

6 is a graphical view explaining charge accumulation in the photodiode region of a CIS device without a second channel configuration;

7 is a graphical view explaining the lack of charge accumulation in the photodiode region of a CIS device having a second channel configuration according to an embodiment of the present invention;

Fig. 8 is a schematic block diagram of a CCD image sensor according to an embodiment of the present invention;

9 is a schematic cross-sectional view of a portion of a photodetector element in the CCD image sensor of FIG. 8;

10 is a graphical view explaining charge accumulation in a photodiode region of a CCD image sensor not having a two-channel configuration;

11 is a graphical view explaining lack of charge accumulation in a photodiode region of a CCD image sensor having a second channel configuration according to an embodiment of the present invention; and

12(A) to 12(G) are schematic cross-sectional views explaining a method of manufacturing a CIS device according to an embodiment of the present invention.

Detailed ways

The invention will now be illustrated by means of several preferred, but non-limiting, examples.

Next, an image sensor according to a first embodiment of the present invention will be described with reference to FIGS. 3-7.

FIG. 3 illustrates an example in which an embodiment of the present invention is configured as a CMOS image sensor (CIS) 10 . CIS 10 generally includes active pixel array 20 and CMOS control circuitry 30 . As schematically shown in FIG. 3, pixel array 20 includes a plurality of active pixels 22 arranged generally in a matrix. The word lines are respectively connected to the pixels 22 of each row of the pixel array 20 , and the bit lines are respectively connected to the pixels 22 of each column of the pixel array 20 . The CMOS circuitry 30 includes a row decoder 32 for selecting a row (word line) of the pixel array 20 and a column decoder 31 for selecting a column (bit line) of the pixel array 20 . The selected bit line is connected to output amplifier 40 through switching element 50 controlled by CMOS circuitry 30 .

An equivalent circuit diagram of an example of the active pixel 22 is shown in FIG. 4 . Photodiodes PD of active pixels 22 capture incident light and convert it into electrical charge. The charges are selectively transferred from the photodiode PD to the floating diffusion region FD through the transfer transistor Tx. The transfer transistor Tx is controlled by a transfer gate TG signal. The floating diffusion FD is connected to the gate of the driving transistor Dx, which functions as a source follower (amplifier) that buffers the output voltage. The output voltage is selectively transmitted to the output line OUT through the selection transistor Sx. The selection transistor Sx is controlled by a selection signal SEL. The reset transistor Rx is controlled by a reset signal RS, which clears charges accumulated in the floating diffusion FD to a reference level.

FIG. 5 is a schematic cross-sectional view of an embodiment of the photodiode PD, transfer transistor Tx, and reset transistor Rx shown in FIG. 4 . For explanation purposes, photodiode PD is included in the photodiode portion of P-type substrate region 100, reset transistor Rx is included in the floating diffusion portion of said P-type substrate region 100, and transfer transistor Tx is connected between the two. between.

Referring to FIG. 5 , a photodiode (PD) in this example is formed by an N-type PD region 142 located in the surface of the photodiode portion of the substrate region 100 . When light is incident on the surface of the substrate region 100 , negative charges are accumulated in the PD region 142 .

In order to reduce dangling silicon bonds existing on the surface of the substrate region 100 , a P+ type hole accumulation device (HAD) region 140 is interposed between the surface of the substrate region 100 and the PD region 142 . The HAD region 140 causes negative charges to recombine in the surface region of the substrate region 100 located above the PD region 142 , thereby avoiding the accumulation of such charges in the PD region 142 .

The floating diffusion portion of the substrate 100 includes an N+ type floating diffusion region 152, an N+ type drain region 154, and a gate 134 extending therebetween. In this example, as shown in FIG. 4 , the gate 134 receives the reset signal RS, the drain region 154 is connected to VDD, and the floating diffusion region 152 is connected to the floating node FD. Drain region 154 , floating diffusion region 152 and gate 134 define reset transistor Rx in FIG. 4 .

Still referring to FIG. 5 , transfer gate 132 is located above the surface of substrate region 100 between HAD region 140 and floating diffusion region 152 . In addition, the first P-type channel region 112 is located in the substrate region 100 and is aligned under the transfer gate 132, and the second N-type channel region 114 is located between the transfer gate 132 and the first channel region. 112 in the substrate region 100 . As shown by arrow A in FIG. 5 , the floating diffusion region 152 is in electrical contact with the second channel region 114 .

In the example of this embodiment, the impurity concentration of the floating diffusion region 152 is higher than that of the second channel region 114, the impurity concentration of the first channel region 112 is higher than that of the substrate region 100, and the HAD region The impurity concentration of 140 is higher than that of the substrate 100 . In addition, in this example, the first channel region 112 is in contact with both the HAD region 140 and the PD region 142 , so that the second channel region 114 is isolated from the PD region 142 by the HAD region 140 .

In addition, in the example of this embodiment, the implantation depth of the second channel region 114 is smaller than the implantation depth of the floating diffusion region 152 and smaller than the implantation depth of the HAD region 140 . In addition, in the present example, the implantation depth of the first channel region 112 is less than the implantation depth of the PD region 142 and is less than the implantation depth of the floating diffusion region 152 .

In addition, in the example of this embodiment, the transfer gate 132 partially overlaps the PD region 142 and the HAD region 140 , wherein the overlapping degree of the HAD region 140 is smaller than that of the PD region 142 .

6 and 7 are potential distribution diagrams for explaining the effect of the second channel region 114 in FIG. 5 . In particular, FIG. 6 shows the potential distribution when the second channel region 114 is not provided (that is, only the first channel region 112 is provided); FIG. 7 shows that both the first channel region 112 and the The potential distribution in the case of the second channel region 114 (ie, as shown in FIG. 5 ) is provided.

As mentioned above, the function of the HAD region 140 is to prevent the presence of suspended silicon bonds on the substrate surface from introducing charges into the PD region 142 , thereby reducing dark current. However, any dangling silicon bonds existing at the substrate surface under the gate electrode 132 may cause charges, which may accumulate in the PD region, resulting in generation of dark current. This embodiment solves this problem by including the second channel region between the substrate surface and the first channel region.

That is to say, it can be seen from the comparison of FIG. 6 and FIG. 7 that the provision of the second channel region 114 changes the potential distribution under the gate electrode of the transfer transistor. More precisely, by electrically coupling an N+-type floating diffusion region to an N-type second channel region, under said gate electrode, the potential distribution increases continuously in a direction towards said floating diffusion region. As such, electrons formed on the substrate surface below the gate electrode (eg, from silicon dangling bonds) will drift to the floating diffusion region instead of to the PD region 142 . Accordingly, charges are not accumulated in the PD region 142, thereby reducing dark current.

In contrast, as shown in FIG. 6 , when the second channel region 114 is not provided, the potential distribution increases from the intermediate region in the direction toward the PD region under the gate electrode. As such, electrons formed on the surface under the gate electrode will drift into the PD region, increasing the dark current.

FIG. 8 illustrates an example in which an embodiment of the present invention is configured as a CCD image sensor 200 . CCD image sensor 200 generally includes: a plurality of pixels 210, each pixel 210 has a photodiode and a transfer gate; a vertical CCD 220; horizontal CCD 230; and floating diffusion region 240; and a source follower (amplifier )250.

9 is a schematic cross-sectional view of an embodiment of the photodiode region and transfer transistor of pixel 210 shown in FIG. 8 .

Referring to FIG. 9 , the photodiode of this example is composed of an N-type photodiode region 310 located in a P-type layer 302 formed on an N-type semiconductor substrate 300 . When light is incident through the opening 372 of the light shielding layer 370 , negative charges will accumulate in the photodiode region 310 . Reference numeral 340 denotes a P-type isolation region.

In order to reduce the dangling silicon bonds existing on the surface of the P-type layer 302 , a P+-type hole accumulation device (HAD) region 312 is inserted between the surface of the P-type layer 302 and the N-type photodiode region 310 . HAD region 312 causes negative charges to recombine on the surface region of P-type layer 302 , thereby preventing accumulation of such charges in N-type photodiode region 310 .

Still referring to FIG. 9 , transfer gate 360 is located on the surface of P-type layer 302 between HAD region 312 and N+-type buried channel CCD (BCCD) 320 . In addition, the first P-type channel region 332 is located in the P-type layer 302 and under the transfer gate 360; the second N-type channel region 334 is located between the transfer gate 360 and the first channel region 332 in the P-type layer 302 . BCCD 320 is in electrical contact with second channel region 334.

In the example of this embodiment, the impurity concentration of BCCD 320 is higher than the impurity concentration of the second channel region 334, the impurity concentration of the first channel region 332 is higher than the impurity concentration of the P-type layer 302, and the impurity concentration of the HAD region 312 The concentration is higher than the impurity concentration of the P-type layer 302 . Moreover, in this example, the first channel region 332 is in contact with both the HAD region 312 and the photodiode region 310 , thereby isolating the second channel region 334 from the photodiode region 310 .

In addition, in the example of this embodiment, the implantation depth of the second channel region 334 is less than the implantation depth of the BCCD 320 and less than the implantation depth of the HAD region 312. Also, in this example, the implantation depth of the first channel region 332 is less than the implantation depth of the photodiode region 310 and less than the implantation depth of the BCCD 320.

In addition, although not shown in FIG. 9, the transfer gate 360 may partially overlap the photodiode region 310 and the HAD region 312, and the overlapping degree of the HAD region 312 may be smaller than that of the photodiode region 310, as shown in FIG. device shown.

10 and 11 are potential distribution diagrams for explaining the effect of the second channel region 334 in FIG. 9 . In particular, FIG. 10 shows the potential distribution when the second channel region 334 is not provided (that is, only the first channel region 332 is provided); FIG. 11 shows that both the first channel region 332 and the The potential distribution in the case of providing the second channel region 334 (ie, as shown in FIG. 9 ) is provided.

It can be seen from the comparison of FIG. 10 and FIG. 11 that the provision of the second channel region 334 changes the potential distribution under the gate electrode of the transfer transistor. More precisely, by electrically coupling the N+-type BCCD to the N-type second channel region, under the gate electrode, the potential distribution increases continuously in the direction towards the floating diffusion region. As such, electrons formed on the substrate surface below the gate electrode (eg, from silicon dangling bonds) will drift to the floating diffusion region, rather than to the N-type photodiode region. Therefore, charges are not accumulated in the photodiode region, thereby reducing dark current.

In contrast, as shown in FIG. 10 , when the second channel region 334 is not provided, under the gate electrode, the potential distribution increases from the intermediate region in the direction toward the photodiode region. As such, electrons formed on the surface under the gate electrode will drift into the photodiode region, increasing the dark current.

An exemplary method of fabricating the device shown in FIG. 5 will now be described with reference to FIGS. 12A to 12G .

Initially, as shown in FIG. 12A , a LOCOS region or STI region 102 is formed in the semiconductor substrate 100 to define the active region of the substrate 100 .

Thereafter, as shown in FIG. 12B , mask layer 110 is patterned over the surface of substrate 100 with an opening defining transistor region 104 . Afterwards, P-type impurities are implanted through the opening to define a P-type channel region 112 . In this example, boron was implanted at 30KeV to obtain an impurity concentration of approximately 1×10 ¹² /cm ² .

Afterwards, as shown in FIG. 12C , N-type impurities are implanted through the opening in the mask layer 110 to form an N-type channel region 114 . In this example, arsenic was implanted at 30 KeV to obtain an impurity concentration of about 5×10 ¹² /cm ² . As shown, two channel regions 112 and 114 are obtained, wherein the N-type channel region 114 is located between the P-type channel region 112 and the opening in the mask layer 110 .

Referring to FIG. 12D , an insulating layer and a conductive layer are deposited and patterned to define a gate structure over the active region of the substrate 100 . In particular, a first gate structure is aligned over channel regions 112 and 114 and is bounded by gate insulating layer 122 and gate electrode 132 . A second gate structure is separated from the first gate structure, the second gate structure being bounded by the gate insulating layer 124 and the gate electrode 134 .

Next, as shown in FIG. 12E, P-type ions are implanted through openings (not shown) in the mask, which are aligned over the photodiode region of the device, thereby forming a P+-type HAD region 140. . In this example, BF2 was implanted at 50KeV to obtain an impurity concentration of about 5×10 ¹³ /cm ² .

After that, as shown in FIG. 12F , N-type impurities are implanted through the opening in the mask layer, thereby forming an N-type photodiode region 142 . In this example, arsenic was implanted at 400KeV to obtain an impurity concentration of about 1.7×10 ¹² /cm ² . Here, the same mask layer used when forming the HAD region 140 may be selectively used. Also, the gate electrode 132 may optionally overlap the photodiode region 142, as indicated by reference letter W in FIG. 12F.

Finally, referring to FIG. 12G , by implanting N-type impurities, an N+ type floating diffusion region 152 and an N+ type drain region 154 are formed.

In each of the above embodiments, the photodiode region, the second channel region and the floating diffusion region (or CCD region) are all defined by N-type impurities, and the first channel region and the substrate (or layer) is bounded by P-type impurities. However, the present invention can also be configured as follows: the photodiode region, the second channel region and the floating diffusion region (or CCD region) are defined by P-type impurities, and the first channel region is defined by N-type impurities and substrate (or layer).

While the invention has been described above in conjunction with its preferred embodiments, the invention is not intended to be limited. On the contrary, various changes and modifications to the described preferred embodiment will become apparent to those skilled in the art. Therefore, the present invention is not limited only to the preferred embodiments described above. Rather, the true spirit and scope of the invention are defined by the appended claims.

Claims (19)

1. An image sensor comprising: a substrate having a first conductivity type; a photodiode region of the second conductivity type in the substrate; a hole accumulation device region on the surface of the substrate and above the photodiode region; a transfer gate located above the surface of the substrate adjacent to the hole accumulating device region; a first channel region of a first conductivity type in the substrate and below the transfer gate; a second channel region of a second conductivity type between the transfer gate and the first channel region at the surface of the substrate; and A buried channel charge-coupled device region in the substrate under the transfer gate, wherein the buried channel charge-coupled device region is in electrical contact with the second channel region. 2. The image sensor of claim 1, wherein an impurity concentration of the buried channel CCD region is higher than an impurity concentration of the second channel region. 3. The image sensor of claim 1, wherein an impurity concentration of the first channel region is smaller than an impurity concentration of the substrate. 4. The image sensor according to claim 1, wherein an impurity concentration of the hole accumulation device region is higher than an impurity concentration of the substrate. 5. The image sensor of claim 1, wherein the second channel region is isolated from the photodiode region by the hole accumulation device region and the first channel region. 6. The image sensor according to claim 1, wherein the implantation depth of the second channel region is smaller than the implantation depth of the buried channel CCD region. 7. The image sensor of claim 1, wherein an implantation depth of the second channel region is smaller than an implantation depth of the hole accumulation device region. 8. The image sensor of claim 1, wherein an implantation depth of the first channel region is smaller than an implantation depth of the photodiode region. 9. The image sensor according to claim 1, wherein the implantation depth of the second channel region is less than the implantation depth of the buried channel CCD region; wherein the implantation depth of the second channel region is less than The implantation depth of the hole accumulation device region, and wherein the implantation depth of the first channel region is smaller than the implantation depth of the photodiode region. 10. The image sensor of claim 1, wherein the first channel region is in contact with the hole accumulation device region and the photodiode region. 11. The image sensor according to claim 1, wherein the first conductivity type is a P conductivity type, and the second conductivity type is an N conductivity type. 12. The image sensor according to claim 1, wherein the first conductivity type is an N conductivity type, and the second conductivity type is a P conductivity type. 13. An image sensor comprising a plurality of pixels operationally connected to a charge-coupled device, wherein each of said pixels comprises: a substrate having a first conductivity type; a photodiode region of the second conductivity type in the substrate; a hole accumulating device region on the substrate surface and above the photodiode region; a transfer gate located above the substrate surface adjacent to the hole accumulating device region; a first channel region of a first conductivity type in the substrate and below the transfer gate; a second channel region of a second conductivity type between the transfer gate and the first channel region on the substrate surface; and A buried channel charge-coupled device region in the substrate under the transfer gate, wherein the buried channel charge-coupled device region is in electrical contact with the second channel region. 14. The image sensor of claim 13, wherein an impurity concentration of the buried channel CCD region is higher than an impurity concentration of the second channel region. 15. The image sensor according to claim 13, wherein an impurity concentration of the first channel region is higher than an impurity concentration of the substrate, wherein an impurity concentration of the hole accumulating device region is higher than that of the substrate. low impurity concentration, and wherein the second channel region is isolated from the photodiode region by the hole accumulation device region and the first channel region. 16. The image sensor according to claim 13, wherein the implantation depth of the second channel region is less than the implantation depth of the buried channel CCD region; wherein the implantation depth of the second channel region is less than The implantation depth of the hole accumulation device region, and wherein the implantation depth of the first channel region is smaller than the implantation depth of the photodiode region. 17. The image sensor of claim 13, wherein the first channel region is in contact with the hole accumulation device region and the photodiode region. 18. The image sensor according to claim 13, wherein the first conductivity type is a P conductivity type, and the second conductivity type is an N conductivity type. 19. The image sensor according to claim 13, wherein the first conductivity type is an N conductivity type, and the second conductivity type is a P conductivity type.

Images