CN100555585C

CN100555585C - Triple diffusion methods prepare igbt N-/P-/P+ substrate approach

Info

Publication number: CN100555585C
Application number: CNB2008101216455A
Authority: CN
Inventors: 陈福元; 毛建军; 胡煜涛; 胡梦
Original assignee: HANGZHOU HANGXIN ELECTRONIC INDUSTRY Co Ltd
Current assignee: HANGZHOU JINGDI SEMICONDUCTOR CO., LTD.
Priority date: 2008-10-23
Filing date: 2008-10-23
Publication date: 2009-10-28
Anticipated expiration: 2028-10-23
Also published as: CN101399202A

Abstract

The invention discloses the triple diffusion methods of a kind of employing and prepare igbt N-/P-/P+ substrate approach.Comprise the steps: 1) prediffusion P+/P-semiconductor impurities on whole of silicon single crystal flake; 2) under 1260～1300 ℃ of temperature, carry out the knot of 100～250 hours interior prediffusion P+/P-impurity of silicon; 3) grind the P+/P-diffusion layer of removing a surface, and polishing N-face is a minute surface; 4) on the N-/P-/P+ silicon chip, make igbt.The present invention is based on the difference on epitaxial wafer and the diffusion sheet price, make withstand voltage igbt (IGBT) substrate slice between 600-1200V, have good economic benefit by adopting triple diffusion process methods.

Description

Triple diffusion methods prepare igbt N-/P-/P+ substrate approach

Technical field

The present invention relates to a kind of triple diffusion method and prepare igbt N-/P-/P+ substrate approach.

Background technology

Igbt (IGBT) is bipolar and multiple device MOS, it integrates MOSFET and bipolar advantage, with regard to the application of power electronic device, its characteristic obviously is better than bipolar transistor and power MOSFET, so be subjected to people's favor since coming out always.

The making of igbt (IGBT) needs a kind of like this material, promptly forms thick high resistant N layer on low-resistance P one, thereby obtains high puncture voltage and low conducting resistance.General triple diffusions, thick epitaxy technology and the direct keypad technology of silicon chip (SDB) of adopting of making for this kind backing material.And thick epitaxy technology is except existing self-diffusion phenomenon inevitably, and it is very difficult obtaining surface of good, and price is more expensive.Because silicon epitaxy layer is a silicon with the atomic form strictness grows on the lattice direction of its substrate silicon monocrystalline and form, require preparation technology's difficulty of high-precision equipment and technology, particularly thick epitaxial wafer big, the cost height.Comparatively speaking, the SDB technology can overcome the shortcoming of impurity self-diffusion in the silicon epitaxial wafer. and be a kind of more satisfactory method.But produce in enormous quantities because the present situation of domestic SDB technology is difficult to realization, and price is also quite expensive.In view of igbt (IGBT) remarkable power-performance and application widely, people propose to adopt triple diffusion methods to make the used silicon chip substrate of igbt (IGBT), to promote the bigger development of igbt (IGBT).

The manufacture method of triple diffusion transistors just proposed as far back as 1957～1958 years, owing to transistorized collector region, base, emitter region are all obtained by method of diffusion, just was called triple diffusions.Triple diffusions are to be easy to guaranteed high resistant monocrystal material with quality to replace the high resistant epitaxial material, thereby avoid the various defective effects of epitaxial material.Current triple diffusion technique is very ripe, becomes an important technology of semiconductor manufacturing industry.

Summary of the invention

The objective of the invention is to overcome the deficiencies in the prior art, provide a kind of triple diffusion method to prepare igbt N-/P-/P+ substrate approach.

Comprise the steps:

1) prediffusion P+/P-semiconductor impurities on whole of silicon single crystal flake;

2) under 1260～1300 ℃ of temperature, carry out the knot of 100～250 hours interior prediffusion P+/P-impurity of silicon;

3) grind the P+/P-diffusion layer of removing a surface, and polishing N-face is a minute surface;

4) on the N-/P-/P+ silicon chip, make igbt.

The time of impurity prediffusion is 2-4 hour in the described step 1), and temperature is 1100 ℃-1260 ℃.

The doped source ratio of P+/P-semiconductor impurities is 1: 30 in the described step 1).

Described step 2) temperature is 1270 ℃-1290 ℃ in; Be 150～230 hours diffusion time

The present invention is based on the difference on epitaxial wafer and the diffusion sheet price, make withstand voltage igbt (IGBT) substrate slice between 600-1200v, have good economic benefit by adopting triple diffusion process methods.

Description of drawings

Fig. 1 is igbt (IGBT) the triple diffusion sheet preparation flow of N-/P-/P+ substrate silicon figure.

Fig. 2 is igbt (IGBT) structural representation.

Embodiment

Triple diffusion methods prepare igbt (IGBT): A, diffuse into the P+/P-semiconductor impurities in advance on whole of original silicon single crystal flake; B, high temperature carry out the knot of pre-expansion P+/P-impurity in the silicon for a long time; C: grinding removal one surperficial upward P+/P-diffusion layer and polishing the N-face is minute surface; D, finish P well region diffusion, the diffusion of N+ source region on the N-/P-/P+ silicon chip, igbt (IGBT) is made in the gate dielectric growth.

Igbt (IGBT) with triple diffusion method preparations mainly comprises following steps with substrate N-/P-/P+ silicon chip:

1) select N type 30-50 Ω .cm silicon chip for use, through surface treatment, clean, it is stand-by to dry the back.

2) proportionally prepare the p type doped source that is adopted.

3), and do the pre-diffusion that distributes in the whole surface deposition P-of silicon chip doped source.

4), and do the pre-diffusion that distributes in the whole surface deposition P+ of silicon chip doped source.

5) the long-time knot diffusion of high temperature.

6) grind the P+/P-layer of removing a surface, obtain the N-/P-/P+ silicon chip.Chemico-mechanical polishing N-surface is to required N-/P-/P+ silicon substrate film thickness.

Technological process is 1) with N type silicon single crystal (N type, electricalresistivity=20-50 Ω cm) is cut into the monocrystalline silicon piece that thickness is 520 ± 10 μ m, through No. 1 chemical electronics cleaning fluid (NH4OH: H2O2: H2O=1: 2: 5) and the strict cleaning of No. 2 chemical electronics cleaning fluids (HCL: H2O2: H2O=1: 2: 8).The cleaning reaction temperature of chemistry electronics cleaning fluid is 80-85 ℃, and the reaction time is 10 minutes.Then silicon chip is placed pure water cleaning down cleaning.Pure water resistivity 〉=12 megohms centimetre, time 〉=60 minute of at every turn washing by water.Silicon chip is 120 ℃ drying in oven, stoving time 〉=30 minute.2), according to the ratio preparation P+/P-doped source of the weight ratio of high concentration P+ doped source and low concentration P-doped source=1: 30.3), the diffuse source for preparing is uniformly coated on the silicon chip two sides.And (1100 ℃-1260 ℃) mix concentration height, doping abundance, P that junction depth is shallow in the impurity source pre-deposition diffusion of carrying out 2-4 hour down at a certain temperature ⁺/ P-N-type semiconductor N impurity.4), in silicon chip, obtain the P+/P-/N-/P-/P+ type shallow diffused junction structure of tow sides symmetry after, under 1260-1300 ℃ temperature, silicon chip is carried out the p type impurity knot diffusion of 100-250 hour (decide according to the needed silicon chip final thickness and the N-single crystalline layer thickness that will keep diffusion time) again, the p type impurity total amount of originally mixing in this process remains unchanged substantially, diffused junction is added be deep to 150-220 μ m.Because boron is different with the diffusion coefficient of aluminium in silicon, thereby has formed P+P-/N-/P-/P+ moldeed depth junction structure during this period.5) grind to remove P+/P-on the face, then and tie diffusion layer deeply and the N-layer grinding and polishing of this face become minute surface (requiring to keep the silicon chip gross thickness according to transistor design is 250-300 μ m), obtain N thus ^-/ P-/P ⁺Type silicon is tied diffusion sheet deeply.Advantage of the present invention is: triple diffusions are to be easy to guaranteed high resistant monocrystal material with quality to replace the high resistant epitaxial material, thereby avoid the various defective effects of epitaxial material, the p type impurity source that utilizes different diffusion coefficients has simultaneously formed the structure of P+/P-(the fast diffusant source has formed the P-layer by once spreading nature, slow diffusion impurity source forms the P+ layer), simplified production technology; Adopting base substrate is the substrates of the triple diffusion sheets of dark knot silicon of P+/P-structure as manufacturing igbt (IGBT), has reduced the cost of raw material significantly, and product is realized than high performance-price ratio.

Embodiment 1

1) prediffusion P+/P-semiconductor impurities on whole of silicon single crystal flake; The time of prediffusion is 2-4 hour, and temperature is 1100 ℃-1260 ℃.

The consumption (weight) of high concentration P+ doped source and low concentration P-doped source is than being 1: 30.

2) under 1260～1300 ℃ of temperature, carry out the knot of 100～250 hours interior prediffusion P+/P-impurity of silicon.

4) on the N-/P-/P+ silicon chip, make igbt.The thickness of P-/P+ layer is 160～250 microns.

Embodiment 2

1) prediffusion P+/P-semiconductor impurities on whole of silicon single crystal flake; The time of prediffusion is 2 hours, 1230 ℃ of temperature.

The doped source ratio of P+/P-semiconductor impurities is 1: 30.

2) under 1270 ℃ of temperature, carry out the knot of the 230 hours interior prediffusion P+/P-impurity of silicon.

3) grind the P+/P-diffusion layer of removing a surface, and polishing N-face is a minute surface.

4) on the N-/P-/P+ silicon chip, make igbt.The thickness of P-/P+ layer is 220 microns.

Embodiment 3

1) prediffusion P+/P-semiconductor impurities on whole of silicon single crystal flake; The time of prediffusion is 4 hours, and temperature is 1180 ℃.

The doped source ratio of P+/P-semiconductor impurities is 1: 30.

2) under 1280 ℃ of temperature, carry out the knot of the 150 hours interior prediffusion P+/P-impurity of silicon.

4) on the N-/P-/P+ silicon chip, make igbt.The thickness of P-/P+ layer is 170 microns.

Embodiment 4

1) prediffusion P+/P-semiconductor impurities on whole of silicon single crystal flake; The time of prediffusion is 3 hours, and temperature is 1210 ℃.

The doped source ratio of P+/P-semiconductor impurities is 1: 30.

2) under 1275 ℃ of temperature, carry out the knot of the 170 hours interior prediffusion P+/P-impurity of silicon.

4) on the N-/P-/P+ silicon chip, make igbt.The thickness of P-/P+ layer is 190 microns.

Claims

1, a kind of triple diffusion method prepares the method for igbt with the N-/P-/P+ silicon substrate, it is characterized in that comprising the steps:

3) grind removal one lip-deep P+/P-diffusion layer, and polishing N-face is a minute surface;

4) on the N-/P-/P+ silicon chip, make igbt.

2, a kind of triple diffusion methods according to claim 1 prepare the method for igbt with the N-/P-/P+ silicon substrate, and the time that it is characterized in that impurity prediffusion in the described step 1) is 2-4 hour, and temperature is 1100 ℃-1260 ℃.

3, a kind of triple diffusion methods according to claim 1 prepare the method for igbt with the N-/P-/P+ silicon substrate, and the doped source ratio that it is characterized in that P+/P-semiconductor impurities in the described step 1) is 1: 30.

4, a kind of triple diffusion methods according to claim 1 prepare the method for igbt with the N-/P-/P+ silicon substrate, it is characterized in that described step 2) in temperature be 1270 ℃-1290 ℃; Be 150～230 hours diffusion time.