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CN100541580C - The method of display device and driving display device - Google Patents

The method of display device and driving display device Download PDF

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Publication number
CN100541580C
CN100541580C CNB2003801024018A CN200380102401A CN100541580C CN 100541580 C CN100541580 C CN 100541580C CN B2003801024018 A CNB2003801024018 A CN B2003801024018A CN 200380102401 A CN200380102401 A CN 200380102401A CN 100541580 C CN100541580 C CN 100541580C
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China
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current
circuit
signal
display device
voltage
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CN1708779A (en
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两泽克彦
白崎友之
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Soras Oled
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Casio Computer Co Ltd
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Abstract

Display device comprises: display board comprises decussate each other many signal line (DL) and multi-strip scanning line (SL) and has near the point of crossing that is arranged in many signal line and sweep trace a plurality of display pixels (EM) of optical element (OEL); Signal drive circuit (130A-G) has a plurality of current generating circuits (ILA, ILB, ISA, ISB, ISC-F, PXA-D); Current generating circuit comprises that drive current produces circuit (22A-D), is used for based on the value that shows signal is provided to each bar sweep trace, produces drive current according to a plurality of grading currents; (120A 120B), is used for the sweep signal order is applied to each signal line scan drive circuit, so that in each line cycle, the selection mode of each display pixel is set; Grading current produces circuit (21A-D), is used for producing a plurality of grading currents according at least based on each shows signal bit of constant predetermined reference current.

Description

The method of display device and driving display device
Technical field
The present invention relates to a kind of display device, on the display board that comprises a plurality of display pixels, show required image information, more specifically, relate to the method for a kind of display device and this display device of driving with current drive-type optical element.
Background technology
In recent years, along with occurring with surprising speed such as flat panel display equipments such as LCD (LCD) flat panel monitor, personal computer and visual device monitor with the electronic curtain that is called as cathode ray tube (CRT) are becoming out-of-date apace.Especially, because it provides the many real advantage that surmount other display techniques, so LCD is general.RT compares with traditional C, and LCD is thinner, lighter and consume the energy of much less.In our daily life, the LCD that grows on trees, from large screen television to small-sized laptop computer and PDA(Personal Digital Assistant) and even littler cell phone, digital camera and many other electronic equipments, occur with different shape and size.
As the display device of future generation (display) of following this revolutionary character LCD technology, such as organic field luminescence (EL) device (after this being called as organic EL device), inorganic electroluminescent element (after this being called as inorganic EL element) or light emitting diode (LED) etc., comprise that the full-scale application of the self-luminous display (display device) of the display board that is made of the emissive type light-emitting component that is called as active matrix develops.Particularly, active matrix is the LCD type, and wherein each display element (each pixel) comprises such as transistorized active block keeping its state in scan period, and is called as thin film transistor (TFT) or TFT.
In such generation self-emitting display, especially, compare the self-luminous display of having used the driven with active matrix method with LCD, the display speed response is very fast, and has unconfined viewing angle.In addition, in future, have the more high radiance of the energy consumption of much less, more high-contrast, high-resolution display board etc. are inevitable.Owing to do not need backlightly in such LCD display, so it has very outstanding feature: the thinner and light-dutyer product of weight of shape is possible.
Briefly, the display board of this particular type comprises the array of display pixel, near the light-emitting component that described display pixel is included in each intersection point of signal wire and arranges along the direction of writing the sweep trace that Inbound is provided with by line; Scanner driver sequentially applies sweep signal on schedule, and the display pixel of specified line is arranged on selection mode; And data driver produces write current (drive current) according to the video data that offers each display pixel by signal wire, and above-described write current is offered each display pixel.Each light-emitting component is according to video data, carry out light with predetermined levels of luminosity and produce operation, and with required image information display on display board.The configuration that autoluminescence produces escope hereinafter will be described.
In the display driver operation of such display, produce each write current according to video data with current value from data driver to a plurality of display pixels, provide it to display pixel simultaneously by the selected specified line of scanner driver.This and electric current appointment type driving method form contrast, in electric current appointment type driving method, at each line of a screen with by the display pixel of the selected specified line of scanner driver, repetitive operation is so that each light-emitting component is luminous with predetermined levels of luminosity continuously.Pulse-length modulation (PWM) type driving method etc. is known, in the method, repeat to provide the constant drive current from data driver, each time width (deration of signal) consistent continuously at a screen, and make each light-emitting component luminous with predetermined levels of luminosity with video data with steady state value.
Yet, in above mentioned light-emitting component escope, have problems, will explain the fact that it suffers this defective below.
Particularly, the data driver basis produces write current with the corresponding video data of each display pixel, and above-mentioned write current basis offers the conventional arrangement of display pixel by each signal wire that links to each other with the lead-out terminal of data driver and the video data in the conventional ADS driving control method changes.Therefore, electric current corresponding with each signal line from the scheduled current source, offer the circuit arrangement of the transistor that forms respectively, latch cicuit (latchcircuit) etc. in data driver also will change.Here, usually, capacitive element (distribution electric capacity) is present in the signal wiring.The result, for the electric current that offers data driver from above-mentioned current source, when offering circuit arrangement by signal wiring and provide to carry out electric current, the operation that the electric current that provides from current source is provided is equivalent to stray capacitance charging and the discharge predetermined potential during being present in signal wiring.As a result, when the electric current that provides by signal wiring was extremely low, being used for the charging of the signal wiring that electric current provides and discharge operation can spended time, and by this time, makes the current potential of signal wire stable, the cycle that needs are quite long.
On the other hand, the operating cycle of distributing to the operations such as electric current maintenance in each signal line becomes brief, and obtained necessary high speed operation in the data driver, like this, the structure of the quantity of the quantity of signal wire and the display pixel of display board increases pro rata.
Yet as the above mentioned, especially, charging that electric current provides in signal wiring and discharge operation need a certain amount of time; Along with the miniaturization of display board or high-resolution (high resolving power) etc., the current value that offers the write current of display board by signal wire becomes lower.Its shortcoming that has is: time quantum required in the charging of signal wiring and discharge operation increases, must carry out the rate controlled of the operating speed of the data driver that causes owing to charging and the speed of discharge operation, and the picture quality of realizing ideal becomes difficult.
In addition, disposed the display device that comprises the traditional data driver, produced write current according to video data, and offered display pixel by each signal line by data driver.Yet because write current is to produce the simulating signal that state changes according to the light of light-emitting component, so signal is subjected to the influence of external noise or signal degradation easily, and this has produced reduction or change that the light in the light-emitting component produces luminosity.This problem makes that being difficult to obtain stable image with suitable levels of luminosity shows.
Summary of the invention
Consider that above-mentioned situation has proposed the present invention.Therefore, the present invention has the following advantages: proposed a kind of display device, on display board, show image information in response to shows signal, described display board has display pixel, described display pixel has the current drive-type optical element and produces with the drive current of the shows signal that offers optical element with respect to response, improve operating speed, even under the drive current situation during having reduced the low-grade cycle; So that reduce to produce the required time quantum of drive current; And improve with resulting effect and to show the image quality of response characteristic to realize ideal.
In order to realize aforementioned advantages, first display device of the present invention comprises: display board has decussate each other many signal line and multi-strip scanning line and has near the point of crossing that is arranged in described many signal line and multi-strip scanning line a plurality of display pixels of optical element; Scan drive circuit is used for the sweep signal order is applied to each signal line, so that the selection mode of each display pixel of each line is set; And signal drive circuit, comprise a plurality of current generating circuits; Current generating circuit comprises that at least grading current produces circuit and drive current produces circuit; Grading current produces circuit according to constant predetermined reference current, produce and the corresponding a plurality of grading currents of each shows signal bit, and drive current produces circuit based on the value that the shows signal of the drive current that is produced is provided to each signal line, produces drive current according to a plurality of grading currents.
According to display device of the present invention, each current generating circuit in above-mentioned signal drive circuit also comprises signal holding circuit, is used for receiving and keeping shows signal; Based on the value of the signal that is kept in the signal holding circuit, according to a plurality of grading currents select and set according to the grading current of each bit value of shows signal.
According to the present invention, each current generating circuit produces a plurality of grading currents, comprises a plurality of grading current transistors, wherein, with the ratio that differs from one another by the 2n appointment the transistorized channel width of each grading current is set.Its each control terminal is connected in parallel, and grading current flows through on the transistorized current path of each grading current.In addition, each grading current produces circuit and comprises generating circuit from reference voltage, is used for producing reference voltage according to reference current.Generating circuit from reference voltage comprises reference current transistor, is used to produce the reference voltage to control terminal, and reference current is offered current path.The reference current transistor control terminal is connected to the transistorized control terminal of a plurality of grading currents jointly.Reference current transistor and a plurality of grading current transistor have constituted current mirror circuit.
In addition, according to the present invention, signal drive circuit comprises the configuration that reference current wherein is provided to a plurality of grading currents generation circuit.Provide reference current via the reference current supply lines.Each grade produces circuit and comprises power supply control commutation circuit, is used to control the power supply state that produces circuit from the reference current supply lines to suitable grading current.Power supply control commutation circuit and reception and the maintenance timing during at the shows signal of the signal holding device in each current generating circuit is synchronous, and selectivity is carried out switching controls, thereby any the grading current circuit that can be only produces circuit to a plurality of grading currents provides reference current.
According to the present invention, each grading current produces circuit and comprises that designated state is provided with circuit, is used for signal wire and is set to given voltage, and when shows signal had designated value, described given voltage made optical element drive the assigned operation state that is in.The shows signal designated value is according to shows signal whole value of non-selected each grading current therefrom.Given voltage is the voltage that is used for optical element is driven the state that is arranged on the lowest class.
In addition, according to the present invention, each current generating circuit also comprises reset circuit, is used for applying predetermined reset voltage to signal wire before providing the timing of drive current to signal wire.Resetting voltage is at least low-potential voltage, is used for stored charge in the capacitive element on the optical element that appends to display pixel is discharged, and is used for optical element is carried out initialization.When the shows signal designated value presupposes non-selected a plurality of grading currents whole, apply described resetting voltage.
And according to the present invention, the optical element in the display pixel comprises light-emitting component, is used for by the levels of luminosity according to the current value of supply current, realizes that light produces operation.For example, described optical element has the light-emitting component that is made of organic EL device.Described display pixel comprises pixel-driving circuit at least, has voltage hold circuit, is used to keep the component of voltage in response to the drive current that provides from signal drive circuit; And current suppling circuit, be used for the component of voltage that keeps according to voltage hold circuit, provide light emission drive current to light-emitting component, and make light-emitting component luminous.Current suppling circuit comprises the transistor that is used for light emitting drive, is used for providing glow current to light-emitting component.
In order to realize aforementioned advantages, be set to come second display device of the present invention of the display device of displays image information to comprise according to the shows signal that is made of digital signal: (1) display board has a plurality of display pixels that are equipped with current generating circuit; Near the current drive-type optical element in point of crossing that described current generating circuit comprises decussate each other many signal line and multi-strip scanning line and is arranged in described many signal line and multi-strip scanning line at least; Grading current produces circuit, is used for producing and the corresponding a plurality of grading currents of each shows signal bit according to predetermined constant reference current; Drive current produces circuit, is used for producing drive current based on the value that the shows signal of drive current is provided to optical element; (2) scan drive circuit is used for order and applies sweep signal, so that the selection mode of each display pixel of each line is set; And (3) signal drive circuit, be used for providing shows signal to many signal line.
According to the present invention, current generating circuit comprises signal holding circuit, is used to receive shows signal, and keeps this signal according to the value of the shows signal that is kept in the holding circuit; Selection and set are according to the grading current of each bit value of shows signal from a plurality of grading currents; And generation drive current.
According to the present invention, each grading current produces circuit and comprises a plurality of grading currents, comprises a plurality of grading current transistors, wherein, with the ratio that differs from one another by the 2n appointment the transistorized channel width of each grading current is set.Its each control terminal is connected in parallel, and grading current flows through on the transistorized current path of each grading current.In addition, each grading current produces circuit and comprises generating circuit from reference voltage, is used for producing reference voltage according to reference current.Generating circuit from reference voltage comprises reference current transistor, is used to produce the reference voltage to control terminal, and reference current is offered current path.The reference current transistor control terminal is connected to the transistorized control terminal of a plurality of grading currents jointly.Reference current transistor and a plurality of grading current transistor have constituted current mirror circuit.
According to the present invention, each grading current produces circuit and comprises that designated state is provided with circuit, is used for signal wire and is set to given voltage, and when shows signal had designated value, described given voltage made optical element drive the assigned operation state that is in.The shows signal designated value is according to shows signal whole value of non-selected each grading current therefrom.Given voltage is the voltage that is used for optical element is driven the state that is arranged on the lowest class.
In addition, according to the present invention, each current generating circuit also comprises reset circuit, is used for applying predetermined reset voltage to signal wire before providing the timing of drive current to signal wire.Resetting voltage is at least low-potential voltage, is used for stored charge in the capacitive element on the optical element that appends to display pixel is discharged, and is used for optical element is carried out initialization.When the shows signal designated value presupposes non-selected a plurality of grading currents whole, apply described resetting voltage.
According to the present invention, the optical element in the display pixel comprises light-emitting component, is used for by the levels of luminosity according to the current value of supply current, realizes that light produces operation.For example, described optical element has the light-emitting component that is made of organic EL device.
In addition, according to the present invention, during reference current transistor, grading current transistor and light produce and drive any has the transistorized configuration that comprises the body terminal electrode at least.
When reading in conjunction with the accompanying drawings, from following detailed description, above-mentioned and other purpose of the present invention and novel feature will manifest more completely.Yet, should be appreciated that these accompanying drawings only are illustrative, but not limiting the scope of the invention.
Description of drawings
Fig. 1 shows the profile block scheme of first embodiment of the current generating circuit in the display device related to the present invention;
Fig. 2 shows the electric wiring plan of an example of the latch cicuit of the current generating circuit that is applied to this embodiment;
Fig. 3 shows the electric wiring plan of the example that the current generation section of the current generating circuit that is applied to this embodiment divides;
Fig. 4 shows the profile block scheme of second embodiment of the current generating circuit in the display device related to the present invention;
Fig. 5 shows the electric wiring plan of the example that the current generation section of the current generating circuit that is applied to this embodiment divides;
Fig. 6 shows the profile block scheme of the 3rd embodiment of the current generating circuit in the display device related to the present invention;
The designated state that Fig. 7 shows the current generating circuit that can be applicable to this embodiment is provided with the electric wiring plan of example of detailed configuration of the logical circuit of part;
Fig. 8 shows the profile block scheme of the 4th embodiment of the current generating circuit in the display device related to the present invention;
The designated state that Fig. 9 shows the current generating circuit that can be applicable to this embodiment is provided with the electric wiring plan of example of detailed configuration of the logical circuit of part;
Figure 10 shows the profile block scheme of the example that the current generation section of the 5th embodiment of the current generating circuit that is applied to display device related to the present invention divides;
Figure 11 shows the figure of an example of the detailed circuit that the current generation section of current generating circuit in this embodiment divides;
Figure 12 shows the profile block scheme of another example that the current generation section of the current generating circuit that is applied to this embodiment divides;
Figure 13 shows the profile block scheme of first embodiment of display device related to the present invention;
Figure 14 shows the profile block scheme of the ios dhcp sample configuration IOS DHCP of the display board that is applied to the display device relevant with this embodiment;
Figure 15 shows the profile block scheme of another ios dhcp sample configuration IOS DHCP of the display device relevant with this embodiment;
Figure 16 shows the electric wiring plan with an ios dhcp sample configuration IOS DHCP of the current drain that can be applicable to the display device relevant with this embodiment (current sinking) the corresponding pixel-driving circuit of method;
The electric wiring plan of the configuration of first embodiment that Figure 17 shows at the data driver of the display device relevant with the present invention;
Figure 18 shows the sequential chart of example of the drive controlling operation of data driver in this embodiment;
Figure 19 shows the sequential chart of an example of the drive controlling operation of display board in this embodiment;
Figure 20 shows the electric wiring plan of configuration of second embodiment of the data driver in display device related to the present invention;
Figure 21 shows and can be applicable to the electric wiring plan of an ios dhcp sample configuration IOS DHCP of the corresponding pixel-driving circuit of electric current applying method of the display device among this embodiment;
Figure 22 shows the profile block scheme of example of current generating circuit of the 3rd embodiment of the data driver that is applied in the display device relevant with the present invention;
Figure 23 shows the profile block scheme of another example of the current generating circuit that is applied to the data driver among this embodiment;
Figure 24 shows the electric wiring plan of configuration of the 4th embodiment of the data driver in display device related to the present invention;
Figure 25 shows the electric wiring plan that the write current that is applied to the data driver among this embodiment produces an example of circuit;
Figure 26 shows the anti-phase latch cicuit of the data driver that is applied to this embodiment and selects to be provided with the electric wiring plan of an example of circuit;
Figure 27 shows the sequential chart of an example of the drive controlling operation in this embodiment the data driver;
Figure 28 shows the electric wiring plan of configuration of the 5th embodiment of the data driver in the display device relevant with the present invention;
Figure 29 shows the electric wiring plan that the write current that is applied to the data driver among this embodiment produces an example of circuit;
Figure 30 shows the electric wiring plan of configuration of the 6th embodiment of the data driver in the display device relevant with the present invention;
Figure 31 shows the electric wiring plan with the display device another example, that can be applicable to this embodiment of the configuration of the corresponding pixel-driving circuit of electric current applying method;
Figure 32 shows the sequential chart of an example of the drive controlling operation in the data driver of this embodiment;
Figure 33 is the sequential chart of an example of the drive controlling operation of display board in this embodiment;
Figure 34 shows the electric wiring plan of configuration of the 7th embodiment of the data driver in display device related to the present invention;
Figure 35 shows the electric wiring plan with the display device another ios dhcp sample configuration IOS DHCP, that can be applicable to this embodiment of the corresponding pixel-driving circuit of circuitry consumes method;
Figure 36 shows the electric wiring plan of configuration of the 8th embodiment of the data driver in the display device relevant with the present invention;
Figure 37 shows the sequential chart of an example of the drive controlling operation of data driver in this embodiment;
Figure 38 shows the electric wiring plan as another ios dhcp sample configuration IOS DHCP of the display pixel that can be applicable to display device related to the present invention;
Figure 39 shows the electric wiring plan of another ios dhcp sample configuration IOS DHCP of the display pixel that can be applicable to display device related to the present invention;
Figure 40 shows the sequential chart of an example of the drive controlling operation in the display device relevant with this embodiment;
Figure 41 shows the profile block scheme of an ios dhcp sample configuration IOS DHCP of second embodiment of display device related to the present invention;
Figure 42 shows the electric wiring plan of an embodiment of the pixel-driving circuit that is applied to the display device among this embodiment;
Figure 43 shows the electric wiring plan of an embodiment of the data driver that is applied to the display device among this embodiment;
Figure 44 shows the sequential chart of an example of the drive controlling operation in the display device of this embodiment;
Figure 45 shows the electric wiring plan of another embodiment of the pixel-driving circuit that is applied to the display device among this embodiment;
Figure 46 shows the profile block scheme of another ios dhcp sample configuration IOS DHCP in the display device of this embodiment;
Figure 47 shows the electric wiring plan of another embodiment of the pixel-driving circuit that is applied to the display device among this embodiment;
Figure 48 A-48B shows the basic circuit of the N channel thin-film field effect transistor in the conventional arrangement and the figure of voltage-current characteristic;
Figure 49 A-49B shows the basic circuit of the P channel thin-film field effect transistor in the conventional arrangement and the figure of voltage-current characteristic;
Figure 50 A-50B shows the contact between the voltage-current characteristic that is used for the transistor (p channel transistor) that light produce to drive, and the current value of the drain current (light generation drive current) that is provided with when write operation and light produce operation;
Figure 51 A-51B shows the synoptic diagram of the surface level configuration of the P channel thin-film transistor with body terminal arrangement;
Figure 52 A-52D shows the synoptic diagram of the cross-sectional configuration of the P channel thin-film transistor with body terminal arrangement;
Figure 53 A-53B shows the basic circuit of the N channel thin-film transistor with body terminal arrangement and the figure of voltage-current characteristic;
Figure 54 A-54B shows the basic circuit of the P channel thin-film transistor with body terminal arrangement and the figure of voltage-current characteristic.
Embodiment
Below with reference to the preferred embodiment driving method that is applied to display device relevant and display device, shown in the drawings, describe the present invention in detail with the present invention.
At first, the data driver of the display device relevant with the present invention or the configuration of current generating circuit are applied to pixel-driving circuit, and will explain the control method of current generating circuit with reference to these accompanying drawings.
1, current generating circuit
First embodiment of current generating circuit
At first will explain first embodiment of the current generating circuit in the display device related to the present invention with reference to the accompanying drawings.
Fig. 1 shows the profile block scheme of first embodiment of the current generating circuit in display device related to the present invention.
As shown in Figure 1, relevant with this embodiment current generating circuit ILA has the configuration that divides 20A to form by signal latch part 10 (signal holding circuit) and current generation section.Signal latch part 10 comprises latch cicuit LC0, LC1, LC2 and LC3 (LC0-LC3), receive digital signal d0, d1, d2 and the d3 (d0-d3) of a plurality of bits (showing the situation of four bits in this embodiment) be used to specify current value separately and keep its (latch one or more, be determined on a case-by-case basis).Current generation section divides 20A to the load current supply lines CL output that links to each other with load, reference current Iref with constant current value that provides from current feedback circuit IRA is provided for it, and, produce the drive current ID that has with respect to the current value of reference current Iref predetermined ratio according to output signal d10, d11, d12 and d13 (d10-d13) from above-mentioned signal latch part 10 (each latch cicuit (LC0-LC3)) output.
Here, current feedback circuit IRA links to each other with the voltage contact+V that is connected to high power supply voltage, so that reference current Iref divides the direction of 20A to flow through reference current supply lines Ls by current generation section.
To explain above-mentioned configuration in detail below.
Fig. 2 shows the electric wiring plan of an example of the latch cicuit that is applied to the current generating circuit among this embodiment.
Fig. 3 shows the electric wiring plan of the example that the current generation section of the current generating circuit that is applied to this embodiment divides.
As shown in Figure 1, signal latch part 10, a plurality of latch cicuit LC0-LC3 form concurrently according to the bit number (4 bit) of digital signal d0-d3; Receive above-mentioned digital signal d0-d3 simultaneously, the timing controling signal CLK according to from output such as timing generator, shift register (being omitted in the drawings) provides each digital signal respectively; And carry out according to suitable digital signal d0-d3 and keep operation with output signal level.
Here, as shown in Figure 2, each the latch cicuit LC0-LC3 that constitutes signal latch part 10 has the configuration that comprises a plurality of known complementary metal oxide semiconductor (CMOS)s (CMOS) transistor npn npn circuit, connects with P channel-type (after this being called as p channel transistor) and n channel-type (after this being called as the N channel transistor) mos field effect transistor (MOSFET) transistor npn npn.
Particularly, as shown in Figure 2, this latch cicuit LC (LC0-LC3) has following configuration, comprising: the CMOS 11 that is made of p channel transistor Tr1 and N channel transistor Tr2, the CMOS 12 that is made of p channel transistor Tr3 and N channel transistor Tr4, the CMOS 13 that is made of p channel transistor Tr5 and N channel transistor Tr6, the CMOS 14 that is made of p channel transistor Tr7 and N channel transistor Tr8, the CMOS 15 that is made of p channel transistor Tr9 and N channel transistor Tr10 and the CMOS 16 that is made of p channel transistor Tr11 and N channel transistor Tr12.
At CMOS 11 input CK places, contact (clock input terminal of latch cicuit LC), timing controling signal (clock signal) CLK is provided, and output contact N11 (after this explain for convenience, will be expressed as " contact " to the reference of " contact ") links to each other with CMOS 12 input contacts.In addition, above mentioned timing controling signal CLK is offered CMOS 13 input terminals.CMOS13 output contact N12 links to each other CMOS 12 output contacts with CMOS 14 input contacts.CMOS 14 output contact N13 link to each other with CMOS 16 input contacts with CMOS 15.On a side, from the sub-OT of the reversed-phase output of latch cicuit LC *(, be expressed as " OT for the ease of making an explanation in the reference element in description and Fig. 2 *") signal level of output contact N13 is output as reversed-phase output signal.On opposite side, the signal level of output CMOS 15 output contact N15 from the noninverting lead-out terminal OT of latch cicuit LC is as noninverting output signal.
In addition, each the N channel transistor Tr2, Tr8, Tr10 and Tr12 formation CMOS 11, CMOS 14, CMOS 15 and the CMOS 16 that link to each other with low supply voltage Vgnd (ground voltage) of each p channel transistor Tr1, Tr7, Tr9 and Tr11 that links to each other with high power supply voltage Vdd by the end by its current path and the end by its current path.For CMOS 12 p channel transistor Tr3 and CMOS 13 N channel transistor Tr6, an end of current path links to each other with the signal input terminal IN of latch cicuit LC, and above-mentioned digital signal d0-d3 is provided.In addition, for CMOS 12 N channel transistor Tr4 and CMOS 13 p channel transistor Tr5, an end of current path links to each other with above CMOS 16 output contact N14.
In having the signal latch part 10 of such configuration, at first, when applying timing controling signal CLK (high level pulse signal) with prearranged signals width, CMOS 12 p channel transistor Tr3 and CMOS 13 N channel transistor Tr6 carry out " conducting " operation, receive the suitably digital signal d0-d3 of timing, and the signal level of specifying CMOS 12 and CMOS 13 public output contact N12 by digital signal d0-d3.Therefore, according to the signal level (signal level of digital signal d0-d3) of output contact N12, determine to offer noninverting lead-out terminal OT and the sub-OT of reversed-phase output of CMOS 16 output contact N14 *Each signal level (high level/low level).
Here, although applying above-mentioned timing controling signal CLK (being timing controling signal CLK low level state) afterwards, MOS 12 p channel transistor Tr3 and CMOS 13 N channel transistor Tr6 carry out " ending " and (OFF) operate, and (ON) operate but CMOS 12 N channel transistor Tr4 and CMOS 13 p channel transistor Tr5 carry out " conducting ".Specify the signal level of the public output contact N12 of CMOS 12 and CMOS 13, and receive the signal level (being equivalent to noninverting output signal (signal level of noninverting lead-out terminal OT)) of CMOS 16 output contact N14.Therefore, the noninverting output signal (signal level of noninverting lead-out terminal OT) and reversed-phase output signal (the sub-OT of reversed-phase output that have the signal level of the application time that is equivalent to timing controling signal CLK *Signal level) continue and export.The signal level of output signal is remained on identical output state, up to application time, till the signal level of signal input terminal IN (signal level of digital signal d0-d3) changes at next timing controling signal CLK.
As shown in Figure 3, current generation section divides 20A to comprise current mirror circuit (grading current generation circuit) 21A and commutation circuit (drive current generation circuit) 22A.Current mirror circuit 21A produces a plurality of grading current Idsa, Idsb, Idsc and Idsd, has the current value of the ratio (each have different ratios) different with respect to reference current Iref difference.Commutation circuit 22A basis is selected grading current from output signal d10, d11, d12 and the d13 (signal level of noninverting lead-out terminal OT as shown in Figure 2) of each latch cicuit LC0-LC3 of above-mentioned signal latch part 10 randomly from a plurality of above mentioned grading current Idsa-Idsd.
Particularly, as shown in Figure 3, current mirror circuit 21A is applied to the current generation section that is configured to by N channel transistor Tr21 (reference current transistor) and a plurality of N channel transistor (grading current transistor) Tr22, Tr23, Tr24, Tr25 divides 20A.N channel transistor Tr21 have by with electric current input contact INi and low supply voltage Vgnd (ground voltage) between the reference current Iref that provides of the reference current supply lines Ls that links to each other of current path.The control terminal (gate terminal) of N channel transistor Tr21 (reference current transistor) links to each other with contact Ng, and each bar current path (source electrode-drain terminal) is connected between each contact Na, Nb, Nc and Nd and the low supply voltage Vgnd.Each control terminal of N channel transistor (grading current transistor) Tr22, Tr23, Tr24, Tr25 (corresponding to a plurality of latch cicuit LC0-LC3) links to each other with contact Ng jointly.Here, contact Ng is configured to directly link to each other with electric current input contact INi and the capacitor C1 that is connected between the low supply voltage Vgnd.
Reference current transistor Tr21 produces at control terminal (gate terminal: reference voltage Vref contact Ng).When reference current Iref being offered electric current input contact INi, reference current Iref flows to current path.Each of grading current transistor Tr 21-Tr25 makes grading current flow to each current path according to the reference voltage Vref that offers each control terminal.
In addition, commutation circuit 22A is applied to current generation section divides 20A, it has by it makes current path be connected electric current output contact OUTi and is connected to configuration between each contact Na, Nb, Nc and the Nd of load.Output signal d10-d13 outputs to the control terminal parallel with a plurality of (4 equipment) N channel transistor Tr26, Tr27, Tr28 and Tr29 from each above-mentioned latch cicuit LC0-LC3 respectively.
Here, divide among the 20A in the current generation section that is applied to this embodiment, especially, the grading current Idsa-Idsd that flows to each grading current transistor Tr 22-Tr25 and constitute current mirror circuit 21A is set to have the current value of comparing each different predetermined ratio with the reference current Iref that flows to reference current transistor Tr21.Particularly, the transistor size of each grading current transistor Tr 22-Tr25 is each different ratio.For example, under the situation of fixing each grading current transistor Tr 22-Tr25 of channel length, form ratio (W2: W3: W4: W5), thereby make each channel width: 8 corresponding to 1: 2: 4.
Therefore, be W1 if the channel width of reference current transistor Tr21 presupposed, the current value that then will flow to the grading current Idsa-Idsd of each grading current transistor Tr 22-Tr25 is set to Idsa=(W2/W1) * Iref, Idsb=(W3/W1) * Iref, Idsc=(W3/W1) * Iref and Idsd=(W4/W1) * Iref respectively.Therefore, each of channel width that can be by grading current transistor Tr 22-Tr25 is set to 2 n(n=0,1,2,3, 2 n=1,2,4,8 ...), the current value between can grading current is set to be appointed as 2 nRatio.
According to this mode, the current value that each grading current Idsa-Idsd is set comprises current value 2 with generation nThe drive current ID of level.As further describing after a while,, select and gather grading current at random according to a plurality of digital signal d0-d3 bits (output signal d10-d13).Therefore, shown in Fig. 1 to 3, when " conducting " state according to the transistor Tr 26-Tr29 that links to each other with each grading current transistor Tr 22-Tr25 applied 4 bit digital signal d0-d3, the drive current ID that is then produced became 2 4=16 different current values.
Divide among the 20A in current generation section with such configuration, signal level according to the output signal d10-d13 that from above-mentioned latch cicuit LC0-LC3, exports, the special transistor of commutation circuit 22A is carried out " conducting " operation (when by any or a plurality of formations among the Tr26-Tr29 that carries out " conducting " operation, except the situation of carrying out any Tr26-Tr29 that " ending " operate).Reference current Iref flows to the grading current transistor (any of Tr22-Tr25 or a plurality of) of the current mirror transistor 22A that links to each other with the related transistor of carrying out " conducting " operation from reference current transistor Tr21.Grading current Idsa-Idsd has predetermined ratio (2 nIndividual grade) current value, and flow as mentioned above.At electric current output contact OUTi place, drive current ID has the current value that the composite value by these grading currents constitutes.From the load-side that links to each other with electric current output contact OUTi, flow to low supply voltage Vgnd by " conducting " state transistor (no matter Tr26-Tr29 in which) and grading current transistor (no matter Tr22-Tr25 which) at the electric current of contact OUTi place output.
Therefore, in the current generating circuit ILA relevant with this embodiment, be input to signal latch part 10 and offer of the timing of a plurality of digital signal d0-d3 bits of load according to response, the drive current ID that is produced is converted to the analog current that divides 20A from current generation section with predetermined current value by timing controling signal CLK appointment.(in this embodiment that is as above mentioned, drawing drive current) in direction from the current generating circuit of load-side.
Therefore, in the current generating circuit ILA relevant with this embodiment, according to a plurality of digital signal d0-d3 bits (the output signal d10-d13 of signal latch part 10), reference current Iref is offered current generation section from current generator IRA by reference current supply lines Ls divide 20A.From having with respect to selecting a plurality of grading current Idsi-Idsl of the current value of coherent reference electric current I ref predetermined ratio and the grading current of set appointment.Constitute drive current ID, thereby make the output device that is produced that required current value be arranged.The electric current (reference current) that offers above-mentioned reference current supply lines Ls (signal wiring) is constant, and this is owing to do not produce the voltage fluctuation of the current source of following variation.For example, even produced insignificant drive current, in by the operation of the caused current generating circuit of charge or discharge of current stray capacitance, do not postpone; Thus, can make the operating speed rising of current generating circuit also can drive this load at faster speed.
In addition, as described in detail after a while, above-mentioned a plurality of digital signal bits are applied to video data on the display device, so that show required image information.In this case, by drive current that current generating circuit produced and exported corresponding to offering each display pixel that forms display board or the write current that offers the light-emitting component of each display pixel.
Second embodiment of current generating circuit
Next, will second embodiment of current generating circuit related to the present invention be described with reference to the accompanying drawings.
Fig. 4 shows the profile block scheme of second embodiment of the current generating circuit in the display device related to the present invention.
Fig. 5 shows the electric wiring plan of the example that the current generation section of the current generating circuit that is applied to this embodiment divides.
Therefore, about any equivalent in the foregoing description, adopt identical or equivalent term and from describe, simplify or omit explanation it.
In the above-described embodiments, although situation (for convenience shown in having constructed from the load-side that links to each other with current generating circuit ILA, be described as " current drain method "), thereby on the direction of current generating circuit ILA, draw drive current ID, but this embodiment has the configuration (being described as for convenience, " electric current applying method ") that makes the direction of drive current ID from current generating circuit ILA side along load mobile (pouring in).
Particularly, as shown in Figure 4, the current generating circuit ILB relevant with this embodiment has the configuration that is equivalent to first embodiment, comprises the current generator IRB that signal latch part 10 and current generation section are divided 20B and divided 20B to link to each other by reference current supply lines Ls and current generation section.Reference current Iref divides 20B one effluent to go out along the direction of the current generator IRB that links to each other with low supply voltage Vgnd from current generation section.
Signal latch part 10 has the configuration that forms latch cicuit LC0-LC3 respectively with a plurality of digital signal d0-d3 accordingly.The reversed-phase output signal d10 that will link to each other with each latch cicuit LC0-LC3 *-d13 *(, for convenience, in description, be expressed as d10 with reference to the similar elements among the figure 4 *-d13 *, represent the sub-OT of reversed-phase output shown in Figure 2 *Signal level) output to current generation section and divide 20B.
As shown in Figure 5, briefly, the current generation section relevant with this embodiment divides 20B to have current mirror circuit 21B and commutation circuit 22B, has the circuit arrangement (with reference to figure 3) that is similar to above mentioned first embodiment and almost is equivalent.Dispose this part, thereby drive current ID is selected randomly and gather a plurality of grading current Idsi, Idsj, Idsk and the Idsl that has with respect to the current value of reference Iref predetermined ratio, and according to output signal d10 from each latch cicuit LC0-LC3 *-d13 *, produce the electric current that offers load current supply lines CL.
Particularly, the configuration of current mirror circuit 21B and commutation circuit 22B is made of p channel transistor Tr31-Tr39.Reference current transistor Tr31 is connected between electric current input contact INi and the voltage contact+V, and control terminal is connected to voltage contact+V by electric current input contact INi and contact Nh with capacitor C1.In addition, 32-Tr35 is connected between contact Ni, Nj, Nk and Nl and the voltage contact+V with the grading current transistor Tr, and control terminal is connected to contact Nh jointly.In addition, the transistor Tr 36-Tr39 that is used to switch is configured, thereby makes each and be connected between above-mentioned contact Ni, Nj, Nk and Nl and the electric current output contact OUTi from each, and will be from the output signal d10 of latch cicuit LC0-LC3 output *-d13 *Each all is applied to control terminal concurrently.
Here also in this embodiment configuration, be provided with current mirror circuit 21B, the size (that is the channel width when, fixed channel length being set) that forms each grading current transistor Tr 32-Tr35 is so that it is corresponding to the predetermined ratio based on reference current transistor Tr31.Set up the grading current Idsi-Idsl that flows into each current path, thereby make the current value of each have the predetermined ratio different with respect to reference current Iref.
Therefore, also in the current generating circuit 20B relevant, respond the output signal d10 of output from signal latch part 10 (latch cicuit LC0-LC3) with this embodiment *-d13 *Signal level, the special transistor Tr36-Tr39 of commutation circuit 22B carries out " conducting " operation.Therefore, the grading current transistor Tr 32-Tr35 that flows through of the grading current Idsi-Idsl of current value of twice with predetermined ratio of reference current Iref.By electric current output contact OUTi, these resultant currents are offered the load that links to each other with electric current output contact OUTi, as drive current ID.(in this embodiment, drive current flows through from the direction of current generating circuit side in load).
In addition, be similar to the situation of first embodiment, the current generating circuit LIB among this embodiment has following configuration: select from a plurality of grading current Idsi-Idsl and gather specific grading current to produce and output device has the drive current ID of required current value.Because it is constant offering the electric current (reference current) of above mentioned reference current supply lines LS (signal wiring), even produced insignificant drive current, the operating speed of current generating circuit is risen, and can drive this load at faster speed.
The 3rd embodiment of current generating circuit
Next the 3rd embodiment of the current generating circuit relevant with the present invention will be explained with reference to the accompanying drawings.
Fig. 6 shows the profile block scheme of the 3rd embodiment of the current generating circuit in the display device related to the present invention.
The designated state that Fig. 7 shows the current generating circuit that can be applicable to this embodiment is provided with the electric wiring plan of example of detailed configuration of the logical circuit of part.
Here,, adopt identical or equivalent term, and from describe, simplify or omit this explanation for any equivalent among the above mentioned embodiment.
As shown in Figure 6, the current generating circuit ISA relevant with this embodiment has the configuration that is equivalent to first embodiment, comprises that signal latch part 10, current generation section divide 20A and designated state that part 30A is set.Designated state is provided with part 30A (designated state is provided with circuit) and has the configuration that given voltage (given voltage: described after a while blank screen display voltage Vbk or resetting voltage Vr) is applied to load current supply lines CL, it links to each other with the noninverting lead-out terminal OT of latch cicuit LC0-LC3, and only the mode of operation with appointment drives this load.
Here, the current generator IRA that links to each other with the voltage contact+V that is connected to high power supply voltage makes reference current Iref divide in current generation section by reference current supply lines Ls and flows into (pouring in) on the direction of 20A.
For as shown in Figure 6 designated state part 30A is set, configuration comprises that non-/ exclusive disjunction circuit 31 (the designation number value is judged part) (after this being called as NOR circuit) and given voltage apply transistor T N32 (given voltage applying portion).Non-/exclusive disjunction circuit 31 is handled the entering signal of the output signal d10-d13 that exports from each above-mentioned latch cicuit LC0-LC3.The given voltage that constitutes by N channel type field effect transistors (after this being called as FET) apply transistor T N32 respectively be applied to given voltage (Vbk, the voltage source on the control terminal (rejection gate) on the end of current path Vr) and with load current supply lines CL opposition side on the lead-out terminal of relevant NOR circuit 31 link to each other.
Here, as shown in Figure 7 NOR circuit 31 is configured to series circuit and parallel circuit.Series circuit is connected with a plurality of P channel-type FETTr41-Tr44 between high power supply voltage Vdd and the output contact Nout.Parallel circuit is in parallel with a plurality of N channel fet Tr45-Tr48 between low supply voltage Vgnd (ground voltage) and the output contact Nout.Therefore, realized NOR circuit 31, and be easy to be applied to the control terminal of each P raceway groove and N channel fet Tr41-Tr44 and Tr45-Tr48 from the output signal d10-d13 of each latch cicuit LC0-LC3 respectively with known circuit arrangement.
Designated state with such configuration is provided with among the part 30A, and NOR circuit 31 judgements are in the designated state that is set to (0) from all signal levels of the output signal d10-d13 of above-mentioned latch cicuit LC0-LC3 output.Only when being in this designated state, given voltage applies transistor T N32 and carries out " conducting " operation, and (Vbk Vr) is applied to load current supply lines CL with given voltage.
Therefore, according to the current generating circuit ISA of this embodiment, have the effect identical with first embodiment, current generating circuit is according to the drive controlling of a plurality of digital signal bits execution to load.When dividing the output of the electric current among the 20A by isolating current generation section, when all digital signal bits (output signal d10-d13) are set to zero (0), the signal level of electric current power supply line CL will be in high impedance status.Can solve the mode of operation problem of unstable that makes load.In addition, utilize to be set to all digital signal bits (output signal d10-d13) of zero, be set to the voltage of appointment, can drive this load with the mode of operation of appointment by the signal level of load current supply lines CL.These functions are suitable for eliminating unusual in the display, perhaps when on the display device data driver that is applied to this current generating circuit, apply resetting voltage (will describe in detail after a while).
The 4th embodiment of current generating circuit
Next will the 4th embodiment that the circuit relevant with the present invention produces circuit be described with reference to the accompanying drawings.
Fig. 8 shows the profile block scheme of the 4th embodiment of the current generating circuit in the display device related to the present invention.
The designated state that Fig. 9 shows the current generating circuit that can be applicable to this embodiment is provided with the electric wiring plan of detailed configuration example of the logical circuit of part.
Here,, adopt identical or equivalent term, and from describe, simplify or omit its explanation about any equivalent among the above mentioned embodiment.
Although (for convenience to the situation shown in above mentioned the 3rd embodiment, be described as " current drain method ") thus be configured from the load-side that links to each other with current generating circuit ISA and draw load driving electric current I D in the direction of current generating circuit ISA, but having, the 4th embodiment make load driving electric current I D flow into the configuration (being described as for convenience, " electric current applying method ") of (pouring in) in the direction of load from current generating circuit ISB side.
Particularly, as shown in Figure 8, the current generating circuit ISB relevant with this embodiment has the configuration with the above-mentioned second embodiment equivalence, comprises that signal latch part 10, current generation section divide 20B and designated state that part 30B is set.During only when linking to each other with the noninverting lead-out terminal OT of latch cicuit LC0-LC3 so that with the load of assigned operation state-driven, designated state is provided with part 30B, and (Vbk Vr) is applied to load current supply lines CL with given voltage.
Here, current generating circuit ISB links to each other with low supply voltage Vgnd, thereby makes reference current Iref divide 20b to flow in the direction of current generator IRB by reference current supply lines Ls from current generation section.
As shown in Figure 8, designated state is provided with part 30B and comprises that exclusive disjunction circuit 33 and given voltage apply transistor T P34.Exclusive disjunction circuit 33 (after this being called as digital value is judged part or circuit) is provided with the entering signal of the output signal d10-d13 that exports from each above-mentioned latch cicuit LC0-LC3.Given voltage applies transistor T P34 (given voltage applying portion) and is made of p channel transistor, respectively from or the output of circuit 33 with an end of current path is wherein applied the control terminal of voltage source of given voltage Vbk and the other end one side of electric current power supply line CL links to each other to it.
Here, shown in Fig. 9 A or circuit 33 realize by known circuit arrangement, comprising: Sheffer stroke gate 33c (after this being called as NAND circuit), with from the fan-out of two inputs NOR circuit 33a and 33b as input.Output signal d10-d11 and the d12-d13 from each latch cicuit LC0-LC3 imported in two set of two inputs NOR circuit 33a and 33b respectively.
Particularly, shown in Fig. 9 B, such known circuit configuration is applied to be connected on respectively p channel transistor Tr51a-Tr52a and Tr51b-Tr52b between high power supply voltage Vdd and output contact Nota and the Notb with the notion of two inputs among NOR circuit 33a and the 33b, and N channel transistor Tr53a-Tr54a and Tr53b-Tr54b are connected in parallel between low supply voltage Vgnd and output contact Nota and the Notb; And respectively the output signal d10-d13 of each latch cicuit LC0-LC3 is applied to the control terminal of P raceway groove and N channel transistor Tr51a-Tr54a and Tr51b-Tr54b.
In addition, shown in Fig. 9 B, shown NAND circuit 33c utilizes known circuit arrangement to use following notion: use each p channel transistor Tr55-Tr56 that is connected in parallel between high power supply voltage Vdd and the output contact Notc respectively; Be connected in parallel on the N channel transistor Tr57-Tr58 between low supply voltage Vgnd and the output contact Notc; And each the fan-out of above mentioned two inputs NOR circuit 33a and 33b (signal level of output contact Nota and Notb) is applied to the control terminal of each P raceway groove and N channel transistor Tr55-Tr56 and Tr57-Tr58.
In addition, be provided with among the part 30B, or circuit 33 judges whether all signal output signal d10-d13 that export are in the designated state that is set to zero (0) from above-mentioned latch cicuit LC0-LC3 at designated state with such configuration.Given voltage applies transistor T P34 and only carry out " conducting " operation in this designated state, and given voltage Vbk is applied to load by electric current power supply line CL.
Therefore, also in the current generating circuit ISB of this embodiment, in the electric current applying method, can obtain the effect identical with the situation of the 3rd embodiment.
The 5th embodiment of current generating circuit
Next will explain with reference to the accompanying drawings that circuit related to the present invention produces the 5th embodiment of circuit.
As described after a while, produce at the write current that will current generating circuit according to the present invention be applied to display-device driver under the situation of circuit group, operate and be configured to predetermined reference current offered each of a plurality of current generating circuits concurrently although be configured to make a plurality of current generating circuits, but when from a constant-current supply jointly when a plurality of current generating circuits provide reference current, the current value of wherein according to the quantity of current generating circuit the reference current that provides from constant-current supply being shunted is provided the current value that offers each current generating circuit.At this moment, for the electric current that offers each current generating circuit, wherein the component characteristic (channel resistance etc.) of the reference current transistor of the current generation section of each current generating circuit branch almost is equal to each other, owing to it is shunted almost equally, therefore the electric current that offers each current generating circuit as the reference electric current becomes almost electric current (steady current) uniformly.Therefore, can produce equal drive current.
Yet, if changing each other, the component characteristic at each current generating circuit reference current transistor (for example makes the variation of difference or surrounding environment, physical attribute, aging etc. along with the time for example), because offering the variation of the electric current of each current generating circuit is to be in a kind of like this situation, promptly, uneven variation has reference current, and therefore, the drive current that is produced also will change.
Then, except the configuration in each the foregoing description, this embodiment comprises that it is intermittent configuration that reference current wherein is provided from current generator in current generating circuit.Therefore, when operating simultaneously concurrently with a plurality of current generating circuits, be applied to the data driver of the display device of describing current generating circuit related to the present invention after a while, and optionally reference current is offered each current generating circuit from current generator, promptly, can construct it, thus can be with the disposable current generating circuit that offers of reference current.Therefore, each current generating circuit uses identical reference current to produce drive current, and can change by the controlling and driving electric current.When being applied to opertaing device, it can control the variation of the luminous grade of each display pixel, and can obtain splendid image quality.
Figure 10 shows the profile block scheme of the example that the current generation section of the 5th embodiment of the current generating circuit that is applied to display device related to the present invention divides.
Figure 11 shows the figure of an example of the detailed circuit that the current generation section of current generating circuit in this embodiment divides.
Figure 12 shows the profile block scheme of another example that the current generation section of the current generating circuit that is applied to this embodiment divides.
Here,, adopt identical or equivalent terms, and from describe, simplify or omit explanation it for any equivalent among the above mentioned embodiment.
Figure 10 shows the current generation section that is applied to the current generating circuit relevant with this embodiment and divides 20C.For example, this current generation section is divided 20C to have with the current generation section shown in above-mentioned second embodiment and is divided 20B (with reference to figure 5) the almost circuit arrangement of equivalence, and disposes current mirror circuit 21C and commutation circuit 22C.Current mirror circuit 21C has the configuration that is attached to commutation circuit, and control (provide or disconnect) is from the power supply state of the reference current Iref of electric current power supply.
Especially, current mirror circuit 21C is equipped with p channel transistor Tr61-Tr65 and commutation circuit TS1 and TS2.Reference current transistor Tr61 is connected between contact Nm and the power contact+V, and control terminal links to each other with contact Np.In addition, grading current transistor Tr 62-Tr65 is connected between voltage contact+V and contact Nq, Nr, Ns and the Nt, control terminal links to each other with contact Np jointly.Capacitor C1 is connected between above-mentioned contact Np and the voltage contact+V.In addition, commutation circuit TS1 is connected between electric current input INi and the above-mentioned contact Nm, and commutation circuit TS2 is connected between above-mentioned contact Nm and the contact Np.
Be similar to above mentioned current generation section and divide 20B, commutation circuit 22C disposes the parallel p channel transistor Tr66-Tr69 that is connected between each above-mentioned contact Nq, Nr, Ns and Nt and the electric current output contact OUTi, and with output signal d10 *-d13 *Output to each control terminal from a plurality of latch cicuits.
Therefore, also in this embodiment, form current mirror 21C, thereby the transistor size of each grading current transistor Tr 62-Tr65 is made of the predetermined ratio based on reference current transistor Tr61, and be provided with and flow to the grading current Idsq-Idst of each current path, thereby make each current value have different predetermined ratio with respect to the electric current (reference current Iref) that flows into reference current transistor Tr61.Therefore, response output signal d10 *-d13 *Signal level, the appointment transistor Tr 66-Tr69 of commutation circuit part 22C carries out " conducting " operation.Make grading current Idsq, Idsr, Idss, the Idst of current value of the twice of the predetermined ratio grading current transistor Tr 62-Tr65 that flows through with reference current Iref.From a plurality of grading current Idsq, Idsr, Idss, Idst, select and gather grading current at random, from electric current output contact OUTi, produce and output driving current ID.
In addition, the current mirror circuit 21C relevant with present embodiment dispose be formed on the commutation circuit TS1 between electric current input contact INi and the contact Nm and be formed on contact Nm and contact Np between commutation circuit TS1.Commutation circuit TS1 and TS2 carry out and control are set correctly to carry out " conducting " and " ending " operation.Therefore, dispose commutation circuit TS1 and TS2 so that provide or disconnect the current path of the reference current Iref of reference current transistor Tr61, and to the current path of reference current transistor Tr61 and the switching controls of connection between the control terminal or disconnection.
Here, as shown in figure 11, especially, commutation circuit TS1 and TS2 can dispose the N channel transistor, thereby carry out switching controls to " conducting " and " ending " state by single control signal rck (will describe in detail after a while).In circuit arrangement shown in Figure 11, by applying high-level control signal rck, two commutation circuit TS1 and TS2 carry out " conducting " operation.Thus, will offer contact Nm and contact Np, and reference current transistor Tr61 will be carried out " conducting " operation by the reference current Iref that current generator produced.Equally, by applying low level control signal rck, two commutation circuit TS1 and TS2 carry out " end " operation and isolate and provide reference current Iref to contact Nm and contact Np, and reference current transistor Tr61 are carried out " ending " operate.
In addition, when being applied to describe after a while in this embodiment when comprising that current generation section is divided the data driver of a plurality of current generating circuits of 20C the generation that has solved the drive current in each current generating circuit.By carrying out " conducting " and " ending ", selective control is formed commutation circuit TS1 and TS2 in each current generating circuit; Only commutation circuit TS1 and the TS2 that forms carried out " conducting " operation in any current generating circuit; And the commutation circuit TS1 that forms in other current generating circuits and TS2 carried out " end " operation, it is disposable to carry out all controls, thereby only provides reference current Iref to the current generating circuit of being correlated with.Therefore, therefore the only reference current transistor of a current generating circuit owing to reference current Iref being offered in a plurality of current generating circuits produces drive current according to current reference current Iref.
In addition, for current generating circuit shown in this embodiment and the configuration that can realize equivalent function, for example, can also use current generation section and divide 20D (current mirror circuit 21D) with circuit arrangement shown in Figure 12.In other words, except formation is equivalent to the reference current transistor Tr61 and grading current transistor Tr 62-Tr65 of current mirror circuit of current mirror circuit 21C shown in Figure 11, current mirror circuit 21D shown in Figure 12 has following configuration, comprising: be connected the commutation circuit TS3 between the current path of electric current input contact INi and reference current transistor Tr61 and be connected commutation circuit TS4 between the control terminal (contact Np) of electric current input contact INi and reference current transistor Tr61.
Therefore, for current mirror circuit 21D and current mirror circuit 21C shown in Figure 11, above-mentioned commutation circuit TS3 and TS4 are configured, thereby can carry out the switching controls power supply of the control terminal of reference current Iref current path and reference current transistor Tr61 or disconnect.
In addition, in this embodiment, although comprise that to the circuit arrangement of additional commutation circuit TS1-TS2 of structure or TS3-TS4 current generation section shown in Figure 5 divides 20B, promptly, show the current mirror circuit 21B and the commutation circuit 22B that dispose p channel transistor, but the present invention is not limited only to the type.Therefore, divide 20A, can have the circuit arrangement of in the configuration of the commutation circuit 22A that comprises current mirror circuit 21A and constitute, having added commutation circuit TS1-TS2 or TS3-TS4 by the N channel transistor for current generation section shown in Figure 3.Commutation circuit TS1-TS2 or TS3-TS4 are not limited to the N channel transistor, can also use p channel transistor, and utilization and the above signal of mentioning control signal rck opposite polarity are carried out the switching controls to " conducting " and " ending " state.The detailed configuration of the current generating circuit that comprises that these current generation section are divided has been shown in the configuration of the display device data driver of describing after a while.
2, display device
Current generating circuit with above mentioned combination and function is applicable as the desirable pixel-driving circuit of the display pixel of the display control apparatus that forms mail apparatus or display board.The display device of the such current generating circuit relevant with the present invention will be described in detail below.
At first, with explaining with reference to the accompanying drawings the current generating circuit relevant with the present invention is applied to embodiment under the situation of drive control apparatus of display device.
First embodiment of display device
Figure 13 shows the profile block scheme of first embodiment of display device related to the present invention.
Figure 14 shows the profile block scheme of the ios dhcp sample configuration IOS DHCP of the display board that is applied to the display device relevant with this embodiment.
Figure 15 shows the profile block scheme of another ios dhcp sample configuration IOS DHCP of the display device relevant with this embodiment.
Here, explanation is comprised configuration with the corresponding display pixel of active matrix panel.In addition, in this embodiment, the configuration of the current drain method that is adopted will be explained.
Shown in Figure 13-14, briefly, the display device 100A relevant with this embodiment comprises: display board 110 is made of a plurality of display pixel EM that arrange by matrix shape; Scanner driver 120A (scanner driver circuit), SL links to each other with sweep trace; Data driver 130A (signal drive circuit), DL links to each other with signal wire; Voltage driver 140 links to each other with the pressure-wire VL that is connected jointly at each the display pixel group who writes the Inbound arrangement by the line of display board 110A, and arranges concurrently with above-mentioned sweep trace SL; System controller 150 outputs are used to produce the mode of operation that various control signals are come gated sweep driver 120A, data driver 130A and voltage driver 140; And display board generation circuit 160, owing to, produce video data, timing signal etc. according to the vision signal that provides from display board 110A outside.
Afterwards, will explain each said structure in detail.
Display board
Particularly, display board 110A as shown in figure 14 has a plurality of sweep trace SL and pressure-wire VL, a plurality of signal wire DL (data line) and a plurality of display pixel EM.A plurality of sweep trace SL arrange parallelly.Arrange many signal line DL so as with sweep trace SL and pressure-wire VL square crossing.Arrange a plurality of display pixel EM so that the intersection point of its each bar line that approaches to intersect vertically.(wherein having formed the pixel-driving circuit DCx that describes subsequently and the configuration of organic EL device).
For example, display pixel EM is made of pixel-driving circuit DCx and optical element.Write current Ipix (drive current) that pixel-driving circuit DCx provides from data driver 130A according to the sweep signal Vsel that applies from scanner driver 120 by sweep trace SL, by signal wire DL and the supply voltage Vsc that applies from voltage driver 140 by pressure-wire VL, control produces operation to write operation and the light in each display pixel EM of write current Ipix.Described optical element is made of light-emitting component, described light-emitting component is known organic EL device OEL, as the current drive-type optical element, by it, the current value that drive current is provided according to the light that provides from pixel-driving circuit DCx is controlled light generation luminosity (also being called brightness and intensity).In this embodiment, although show the situation that organic EL device OEL is applied as current drive illuminant element, can use the light-emitting component except light emitting diode etc.
Here, briefly, pixel-driving circuit DCx has following function: response video data selection mode receives write current Ipix and remains voltage level, and responding scanning signal Vsel controls described voltage level according to selection/non-selected state of each display pixel EM; According at the voltage level (as above being mentioned) that non-selected state kept, provide light to produce drive current to organic field luminescence (EL) device OEL (after this being called as organic EL device) (optical element); And keep with the predetermined luminous operation of levels of luminosity.In addition, the explanation that the possible exemplary circuit that can be applicable to pixel-driving circuit DCx is disposed will be described after a while.
Scanner driver
Scanner driver 120A is according to the scan control signal that provides from system controller 150, by sequentially applying sweep signal Vsel to each sweep trace SL at predetermined regularly place, for each line of display pixel group is provided with selection mode; To offer each signal line DL based on the write current Ipix of video data by data driver 130A; And control will be scheduled to write current and be written in each display pixel.
Particularly, scanner driver 120A shown in Figure 14 is formed by displaced block SB (being made of shift register) and impact damper, and has multistage.In this scanner driver 120, output by shift register from the top of display board 110A the shift signal after the displacement of its underpart sequentially, and according to the scan control signal that provides from system controller 150 (scan start signal SSTR, scan clock signal SCLK etc.), pass through impact damper, this shift signal is applied to each bar sweep trace SL, as sweep signal Vsel with predetermined voltage level (selection level).
Data driver
Data driver 130A is according to the data controlling signal that provides from system controller 150, receives and keeps comprising the video data that produces a plurality of digital signal bits that circuit 160 provided from shows signal; According to relevant video data, produce write current Ipix with current value; And simultaneously and control write current power supply concurrently to each signal line DL.Therefore, in the data driver 130A relevant with this embodiment, ideally, the current generating circuit of above-mentioned each embodiment is compatible.After a while detailed circuit configuration example and its drive controlling of data of description driver 130A are operated.
Voltage driver
Voltage driver 140 extracts predetermined write current Ipix according to video data, and with regularly synchronously by such as on the direction of pressure-wire VL via the data driver 130A of display pixel EM (pixel-driving circuit DCx), select level (for example being set to be lower than the low level of ground connection power supply (ground voltage)) to be applied to pressure-wire VL supply voltage Vsc, according to the voltage control signal that provides from system controller 150, the selection mode at each bar line of each display pixel group is set from scanner driver 120.Simultaneously, voltage driver 140 is on the direction of pressure-wire VL via the organic EL device OEL (optical element) of display pixel EM (pixel-driving circuit DCx), the light that control is equivalent to above-mentioned write current Ipix produces flowing of drive current, with regularly synchronously by the non-selected level of supply voltage Vsc (for example high level) is applied to pressure-wire VL, from the non-selected state of scanner driver 120 settings at each line of each display pixel group.
Particularly, voltage driver 140 shown in Figure 14 is by displaced block SB (being made of shift register) and be similar to above-mentioned and the impact damper corresponding scanner driver 120A of each bar pressure-wire VL and form, has multistage and powers from system controller 150.In this voltage driver 140, according to the voltage control signal synchronous (energy enabling signal VSTR, voltage clock signal VCLK etc.) with above-mentioned scan control signal, be displaced to the shift signal of bottom in proper order from the top of display board 110A from shift register output, and be applied to each bar pressure-wire VL by impact damper, as supply voltage Vsc with predetermined voltage level.
System controller
System controller 150 produces the timing signal that provides the circuit 160 according to described after a while from shows signal, receives each the signal of scanner driver 120A, data driver 130A and voltage driver 140 at least.By producing and output scanning control signal (the scan start signal SSTR that is as above mentioned, scan clock signal SCLK etc.), data controlling signal and voltage control signal (the energy enabling signal VSTR that is as above mentioned, voltage clock signal VCLK etc.), each driver is in predetermined regularly place operation.Make supply voltage Vsc, sweep signal Vsel and write current Ipix output to display pixel 110A; In pixel-driving circuit DCx, carry out continuous predetermined drive controlling operation; And carry out control to display pixel 110A so that show predetermined picture information according to vision signal.
System controller 150 is according to producing the timing signal that circuit 160 provides from described shows signal subsequently, produces and to each output scanning control signal, data controlling signal ((scan start signal SSTR, scan clock signal SCLK, sampling start STR and shift clock signal SFC etc.), the voltage control signal ((energy enabling signal VSTR, voltage clock signal VCLK etc.) of scanner driver 120A, data driver 130A and voltage driver 140 at least.By producing and export above-mentioned signal, system controller 150 makes each driver in predetermined regularly place operation; To display board 110A output supply voltage Vsc, sweep signal Vsel and write current Ipix; In pixel-driving circuit DCx, carry out predetermined drive controlling operation continuously; And carry out control to display board 110A so that show predetermined image information according to vision signal.
Shows signal produces circuit
For example, extract the levels of luminosity component of signal the vision signal that shows signal generation circuit 160 provides outside display device 100A; In each line cycle (horizontal scanning period) at video data plate 110A, provide the levels of luminosity component of signal; And provide the video data and the data driver 130A that constitute by a plurality of digital signal bits.Here, when above-mentioned vision signal comprised the timing signal component of having specified such as the Displaying timer of the image information of television broadcasting signal (composite video signal), shows signal produced another function that circuit 160 has the function of the timing signal component that offers system controller 150 and extracts above-mentioned levels of luminosity component of signal.In this case, above-mentioned controller 150 produces the above-mentioned scan control signal, data controlling signal and the voltage control signal that offer scanner driver 120A, data driver 130A and voltage driver 140 according to producing the timing signal that circuit 160 provides from shows signal.
In addition, although in this embodiment, as Figure 13 and shown in Figure 14, explained the configuration that wherein respectively being arranged as of scanner driver 120A and voltage driver 140 is attached to the outer driver of placing of display board 110A, the present invention is not limited thereto.For example, as the above mentioned, because it is according to equivalent control signal (scan control signal and the voltage control signal) operation with synchronization timing, as shown in figure 15, for example, can form scanner driver 120A and voltage driver 140, offer scanner driver 120B thereby make it have the supply voltage Vsc that output timing and the generation of sweep signal Vsel is synchronous.According to such structure, can simplify the configuration of peripheral circuit and save the space.
In addition, configuration for the display device shown in Figure 13-15, the pixel-driving circuit DCx that forms in each display pixel EM is provided with control by the state according to supply voltage Vsc signal level to described sweep signal Vsel execution after a while, forms display board (with reference to Figure 16).Although realized the situation of predetermined drive controlling operation corresponding to circuit arrangement wherein, the present invention is not limited thereto, after a while with described (with reference to Figure 20).For example, can have the circuit arrangement that by it conventional constant voltage level is applied and is set to the display device shown in Figure 13 and Figure 14 in this case with the pixel-driving circuit that high power supply voltage directly links to each other.The configuration that does not have voltage driver 140 also is applicable.
Pixel-driving circuit
Subsequently, description is applied to the ios dhcp sample configuration IOS DHCP of pixel-driving circuit of each display pixel of above-mentioned display board.
Figure 16 shows the electric wiring plan with an ios dhcp sample configuration IOS DHCP of the corresponding pixel-driving circuit of current drain method that can be applicable to the display device relevant with this embodiment.
In addition, the pixel-driving circuit shown in here only shows the example that can be applicable to display device related to the present invention.Needless to say, it can be other circuit arrangement with equivalent operation function.
As shown in figure 16, relevant with this sample situation pixel-driving circuit DCx has following configuration: N channel transistor Tr71, N channel transistor Tr72, N channel transistor Tr73 and capacitor Cx.In this pixel-driving circuit DCx, thereby having arranged sweep trace SL and signal wire DL therein makes these lines with near the point of crossing intersected with each other, right angle, N channel transistor Tr71 links to each other with contact Nxa by source terminal respectively, pressure-wire VL with sweep trace SL parallel arranged links to each other by drain terminal, and links to each other with sweep trace SL by gate terminal.N channel transistor Tr72 links to each other with sweep trace SL by gate terminal respectively, and drain terminal links to each other with contact Nxb with signal wire DL respectively with source terminal.N channel transistor Tr73 links to each other with contact Nxa by gate terminal respectively, and links to each other with contact Nxb with pressure-wire VL with source terminal by drain terminal respectively.Capacitor Cx is connected between contact Nxa and the Nxb.
In addition, produce drive current by the light that provides from pixel-driving circuit DCx and controlled the organic EL device OEL that before produces the luminosity description at light.Organic EL device OEL anode terminal links to each other with the contact Nxb of above-mentioned pixel-driving circuit, and cathode terminal links to each other with low supply voltage Vgnd (ground voltage) respectively.Here, the stray capacitance that capacitor Cx can form between the gate-source of N channel transistor Tr73, and capacitive element (capacitor) can add (interpolation) individually between this gate-source, except stray capacitance.
At first, drive controlling operation for the organic EL device OEL in the pixel-driving circuit DCx of such structure, in the write operation cycle, when high level (selection level) sweep signal Vsel was applied to sweep trace SL, supply voltage Vsc applied low level to pressure-wire VL simultaneously.In addition, regularly synchronous with this, pixel-driving circuit DCx provides to signal wire DL and is scheduled to write current Ipix (being equivalent to above mentioned drive current ID), and this need carry out according to predetermined levels of luminosity light generation of organic EL device OEL is operated.Here, provide the negative polarity electric current as write current Ipix, and be provided with, thereby drawing correlated current via the direction of the data driver 130A of signal wire DL from pixel-driving circuit DCx (current drain method) side.
Correspondingly, N channel transistor Tr71 and the Tr72 that constitutes pixel-driving circuit DCx carries out " conducting " operation.Simultaneously, the low level of supply voltage Vsc is applied to contact Nxa (promptly, the gate terminal of N channel transistor Tr73 and the end of capacitor Cx), and the low supply voltage level is applied to contact Nxb (promptly, the source terminal side of N channel transistor Tr73 and the other end of capacitor Cx), but not make the low level of supply voltage Vsc through N channel transistor Tr72 by the introducing operation of write current Ipix.
According to this mode, when between contact Nxa and Nxb, the voltage potential difference occurring (between the gate-source of N channel transistor Tr73), N channel transistor Tr73 carries out " conducting " operation, and according to the write operation electric current of write current Ipix from pressure-wire VL via the direction of the signal wire DL of N channel transistor Tr73, contact Nxb and N channel transistor Tr72 flow (after a while will with reference to Figure 19).
At this moment, will and contact Nxa and Nxb between the corresponding charge storage of voltage potential difference that produced in capacitor Cx, and remain component of voltage (condenser charge).In addition, at this moment, owing to be applied to the power supply (voltage is to ground) that the power supply of the anode terminal (contact Nxb) of organic EL device OEL becomes and is lower than cathode terminal, therefore, the bias voltage that will reverse is applied to organic EL device OEL.Light produces drive current and does not flow into organic EL device OEL, and does not carry out the light generation.
Subsequently, in light produces the operating cycle, when it is applied to sweep trace SL with low level (non-selected level) sweep signal Vsel, the high level of supply voltage Vsc is applied to pressure-wire VL.In addition, regularly synchronous with this, suspend drawing in the operation of write current Ipix (promptly writing Control current).
Therefore, because in N channel transistor Tr71 and Tr72 execution " ending " operation, interrupt (cut-out) and will be applied to contact Nxb, correspondingly, interrupted supply voltage Vsc applying to contact Nxa owing to the voltage level that drawing in the operation of write current Ipix produces.Then, capacitor Cx remains on stored charge in the above-mentioned write operation.
According to this mode, when capacitor Cx keeps electric charge in write operation the time that the voltage potential between holding contact Nxa and the Nxb (between the gate-source of N channel transistor Tr73) is poor, and N channel transistor Tr73 remains " conducting " state.In addition, be higher than voltage and be applied to pressure-wire VL to the supply voltage Vsc of the voltage level on ground owing to will have, therefore, the power supply (ground voltage) that the power supply that is applied to the anode terminal of organic EL device OEL becomes and is higher than cathode terminal.
Therefore, light produces drive current and is flowing into organic EL device OEL from pressure-wire VL via the forward bias direction of N channel transistor Tr73 and contact Nxb, and organic EL device OEL is luminous with predetermined levels of luminosity.Here, because the voltage potential that the voltage potential poor (charging voltage) that is kept by capacitor Cx is equivalent to when making the write operation electric current flow into N channel transistor Tr73 when above-mentioned write operation is poor, the light that flows into organic EL device OEL produces drive current and will have the current value that is equivalent to the aforesaid operations electric current.Therefore, produce in the operating cycle at light, according to respond the component of voltage that the predetermined light that writes produces state (levels of luminosity) in the write operation cycle, to provide light to produce drive current continuously, and organic EL device OEL continued operation, and with required levels of luminosity luminous (reference is described Figure 19 after a while).According to this mode, in the pixel-driving circuit relevant with this embodiment, N channel transistor Tr73 has as being used for the transistorized function that light produces driving.
First embodiment of data driver
Subsequently, explanation is applied to first embodiment of the data driver of display device related to the present invention.In each signal wire, form the current generating circuit of each the foregoing description respectively, and constitute the data driver relevant with this embodiment, thereby make the reference current that is provided have steady state value,, for example opposite from single current generator with each current generating circuit via common current power supply line.
The electric wiring plan of the configuration of first embodiment that Figure 17 shows at the data driver of the display device relevant with the present invention.
Here, the explanation that the configuration that provides with above-mentioned current generating circuit is complementary.In addition, any equivalent with reference in above-mentioned each embodiment adopts identical and equivalent term, and after this will simplify and omit the explanation to it from describe.
As shown in figure 17, the data driver 130A relevant with this embodiment has following configuration, have: shift-register circuit 131A, when sampling enabling signal STR being shifted according to the shift clock signal SFC that provides from system controller 150 as data controlling signal, by predetermined regularly sequentially export shift signal SR1, SR2, SR3 ... (being equivalent to above-mentioned timing controling signal CLK); Write current produces circuit group 132A, according to from shift signal SR1, the SR2 of shift-register circuit 131A, SR3 ... timing input, sequentially be received in a line and produce video data d0-dk that circuit 160 orders provide (here from shows signal in the cycle, for convenience, be equivalent to the above-mentioned digital signal d0-d3 that is set to k=3), the light of response in each display pixel EM produces luminosity, produce write current Ipix, and by each signal wire DL1, DL2, DL3 ... provide.Common reference electric current supply lines Ls writes each write current generation circuit I LA1, ILA2, the ILA3 that circuit group 132A is given birth in miscarriage to formation regularly ... reference current with constant current value Iref is provided.In the outside of data driver 130A, form reference current Iref from current generator IR (being equivalent to above-mentioned current generator IRA).Here, with the configuration of the current generating circuit ILA of above-mentioned first embodiment be applied to form write current that write current produces circuit group 132A produce circuit I LA1, ILA2, ILA3 ... each, have signal latch circuit 101,102,103 ... (being equivalent to above-mentioned signal latch part 10) and current generating circuit 201A, 202A, 203A ... (be equivalent to described current generation section and divide 20A).
The drive controlling method
Next, the drive controlling method of the display device with above-mentioned configuration will be explained with reference to the accompanying drawings.
Figure 18 shows the sequential chart of example of the drive controlling operation of data driver in this embodiment.
Figure 19 shows the sequential chart of an example of the drive controlling operation of display board in this embodiment.
Here, except configuration shown in Figure 17, correspondingly, will make an explanation with reference to the configuration of figure 1 and current generating circuit shown in Figure 3.
At first, drive controlling operation in data driver 130A is carried out signal and is kept operation, this operation receives from shows signal generation circuit 160 and offers at above-mentioned write current generation circuit I LA1, ILA2, ILA3, the middle signal latch circuit 101 that forms, 102,103, video data d0-d3, and during the fixed cycle, keep video data d0-d3, and, electric current generation powered operation carries out by being set, described operation is based on keeping operation to produce circuit I LA1 from write current by signal, ILA2, ILA3, the middle current generating circuit 201A that forms, 202A, the holding signal d10-d13 of the video data d0-d3 that 203A receives, d20-d23, d30-d33, according to passing through each signal line DL1, DL2, DL3 offers the above-mentioned video data d0-d3 of each display pixel, produces write current Ipix.
Here, keep in the operation at signal, as shown in figure 18, according to the shift signal SR1, the SR2 that export in proper order from shift-register circuit 131A, SR3 ... this the operation from each above-mentioned signal latch circuit 101,102,103 ... in sequentially receive each line of response display pixel EM (promptly, each signal line DL1, DL2, DL3 ...) the video data d0-d3 that changes, and carry out continuously in the cycle at a line.From signal latch circuit 101,102,103 ... in sequentially receive video data d0-d3, and the fixed cycle (follow shift signal SR1, SR2, SR3 ... afterwards till output) afterwards, with holding signal d10-d13, d20-d23, d30-d33 ... output to current generating circuit 201A, 202A, 203A ...
In addition, produce in the powered operation at electric current, as shown in figure 18, according to holding signal d10-d13, d20-d23, d30-d33 ..., be controlled at each current generating circuit 201A, 202A, 203A ... in " conduction and cut-off " states (transistor Tr 26-Tr29 shown in Figure 3) of formed a plurality of switching transistors.The resultant current that will flow into the grading current of the grading current transistor (transistor Tr 22-Tr25 shown in Figure 3) that links to each other with the switching transistor of carrying out " conducting " operation pass through each signal line DL1, DL2, DL3 ... sequentially provide, as write current Ipix.
Here, control write current Ipix so that in the fixing at least cycle parallel simultaneously offer all signal wire DL1, DL2, DL3 ...
In addition, mention in this embodiment, according to the appointment transistor size that reference current Iref is set up in advance, produce and to have predetermined ratio (for example 2 as above n, n=0,1,2,3 ...) a plurality of grading currents of current value.According to above-mentioned holding signal, responding to switch transistorized " conduction and cut-off " operation is selected and is gathered the predetermine level electric current.The light grade luminosity of response in each display pixel EM produces negative polarity write current Ipix, and write current Ipix is flowed, thus can from signal wire DL1, DL2, DL3 ... cause this electric current on the direction of the data driver 130A of side.
In addition, in the data driver relevant with this embodiment, as shown in figure 17, have following configuration: a plurality of write currents produce circuit I LA1, ILA2, ILA3 ... be parallel to the common reference electric current supply lines Ls that powers by reference current Iref with constant current value from current generator IR.As shown in figure 18, each current generating circuit ILA1, ILA2, ILA3 ... in, since according to video data d0-d3 produce concurrently simultaneously to each signal line DL1, DL2, DL3 ... write current Ipix, by reference current supply lines Ls offer each current generating circuit ILA1, ILA2, ILA3 ... electric current be not self reference current Iref from current generator IR.As an alternative, the write current of parallel work-flow produces the quantity (being equivalent to the quantity of the signal wire of arranging in display board 110A, for example the m line) of circuit when as above mentioning, and provides to have the almost electric current of the current value of five equilibrium (Iref/m).
In addition, as shown in figure 19, the operation of drive controlling in display board 110A is arranged in use in a scan round period T sc (sweep spacing) one-period that shows required image information on the screen of display board 110A; In this scan round period T sc, select the display pixel group who links to each other with the invisible scanning line; The video data that write operation cycle (selection cycle) Tse response provides from data driver 130A, Ipix writes write current, and it is remained signal level; Response provides light to produce electric current based on the above-mentioned video data of the signal level that is kept to organic el device OEL (optical element); Set up light and produce operating cycle Tnse (the non-selected cycle of display pixel EM), this cycle carries out light with predetermined levels of luminosity and produces operation (Tsc=Tse+Tnse); And the drive controlling of execution and the above pixel-driving circuit DCx equivalence of in each operating cycle, being mentioned.Here, write operation period T se is set, thereby time-interleaving each other can not occur at each line.In addition, in the cycle to major general's write operation period T se is set to comprise the fixed cycle, in the electric current generation powered operation of above-mentioned data driver 130A, provide write current Ipix to each signal line concurrently.
Say exactly, as shown in figure 19, to the write operation period T se of display board by at display pixel EM from the specified line (i line) of scanner driver 120 and voltage driver 140, the prearranged signals level of scanning sweep trace SL and pressure-wire VL, carry out the instant operation that keeps write current Ipix, as the component of voltage that offers each signal line DL by data driver 130A concurrently.Light subsequently produces among the operating cycle Tnse, by based on the component of voltage that during above-mentioned write operation, is kept, provide light to produce drive current continuously to organic EL device OEL (optical element) continuously, continue light with the levels of luminosity consistent and produce operation with video data.
As shown in figure 19, by to each bar line of the display pixel group that constitutes display board 110A repeatedly order carry out so a series of drive controlling operations, write the video data at the display board of a screen, each display pixel EM comes luminous with predetermined levels of luminosity and the required image information that will show.
The result, in the data driver 130A and display device 100A relevant with this embodiment, by the data driver 130A relevant and each the signal line DL among the display device 100A, write current Ipix is offered the display pixel group of specified line with this embodiment.Because (particularly based on reference current Iref, equal to produce the electric current of reference current Iref of the quantity five equilibrium of circuit with write current) from each write current produce circuit I LA1, ILA2, ILA3 ... in produce it, wherein according to offer each write current produce circuit I LA1, ILA2, ILA3 ... video data d0-d3 (or write current Ipix), provide described reference current Iref by reference current line Ls from current generator IR is public, current value can not fluctuate.Can alleviate the restriction of the operation that charging and discharge process by reference current supply lines Ls are produced.In addition, can realize the remarkable enhancing and the image quality of demonstration response characteristic of operating speed, the display device of data driver with obvious augmented performance.
In addition, for data driver (write current generation circuit), compare with the reference current transistor that wherein flows through above-mentioned reference current, the transistorized channel width of a plurality of grading currents of the circuit arrangement with current mirror circuit is set, thereby make each by predetermined ratio (for example 2 nGrade) constitutes.Because being flow through, write current is set to 2 nA plurality of grading currents of current value can produce video data by gathering these electric currents according to its state.Utilize suitable simple configuration, can use the analog current that has with the corresponding suitable current value of video data (a plurality of digital signal bit) to produce write current, and the light generation operation that can carry out display pixel EM by suitable levels of luminosity.
Second embodiment of data driver
Subsequently explanation is applied to second embodiment of the data driver of the display device relevant with the present invention.
Although with wherein dispose data driver above-mentioned first embodiment in the corresponding current arrangements of current drain method of introducing write current from the direction of the data driver of display pixel, but the present invention is not limited thereto, on the contrary, can dispose it in the circuit arrangement that the direction from the display pixel of data driver flows through the electric current applying method of (introducing) by the write current that is wherein provided.
Utilize the circuit arrangement of electric current applying method to dispose the data driver relevant with this embodiment.
Figure 20 shows the electric wiring plan of configuration of second embodiment of the data driver in display device related to the present invention.
Here, the explanation that the configuration that provides with above-mentioned current generating circuit is complementary.In addition, any equivalent with reference in above-mentioned each embodiment adopts identical or equivalent term, and will simplify or omit the explanation to it afterwards from describe.
For example, as shown in figure 20, the data driver 130B relevant with this embodiment has the configuration that is formed by following assembly: shift-register circuit 131B, according to the data controlling signal that provides from system controller 150 (shift clock signal SFC and sampling enabling signal STR), sequentially export shift signal SR1, SR2, SR3, Write current produces circuit group 132B, according to suitable shift signal SR1, SR2, SR3 ... timing input, sequentially receive the video data d0-d3 that order provides from shows signal generation circuit 160 at a line cycle, produce luminosity according to the light among each display pixel EM and produce write current Ipix, and by each signal line DL1, DL2, DL3 ... it is provided; And common reference electric current supply lines Ls draws the reference current Iref with current value regularly from the current generator IR (being equivalent to above-mentioned current generator IRB) that the outside at data driver 130B forms.Here, each write current produce circuit I LB1, ILB2, ILB3 ... form write current and produce circuit group 132B, be applied to the configuration of the current generating circuit ILB of above-mentioned second embodiment.In addition, this configuration comprise signal latch circuit 101,102,103 ... (being equivalent to above-mentioned signal latch circuit 10) and current generating circuit 201B, 202B, 203B ... (be equivalent to above-mentioned current generation section and divide 20B).
The first drive controlling method (with reference to figure 18-19) with the display device shown in the foregoing description is identical in fact in the drive controlling operation of data driver 130B, and it is set to signal maintenance operation.According to output in proper order from shift register 131B each above-mentioned latch cicuit 101,102,103 ... shift signal SR1, SR2, SR3 ... this the operation from each above-mentioned signal latch circuit 101,102,103 ... in sequentially receive each line of response display pixel EM (each signal line DL1, DL2, DL3 ...) the video data d0-d3 that changes, and carry out continuously in the cycle at a line.Holding signal d10*-d13*, d20*-d23*, d30*-d33* ... be equivalent to the inversion signal of fixed cycle and video data d0-d3, and output to current generating circuit 201B, 202B, 203B ...
In addition, electric current produce powered operation according to holding signal d10*-d13*, d20*-d23*, d30*-d33* ..., from have in advance at from each current generating circuit 201B, 202B, 203B ... in select and set predetermine level electric current in a plurality of grading currents of current value of predetermined ratio of the reference current Iref appointment of drawing; Produce the write current Ipix of positive polarity, this electric current sequentially is provided so that its from each signal line DL1, DL2 of data driver 130B side, DL3 ... the direction of display pixel EM on flow through.
Pixel-driving circuit
Figure 21 shows and can be applicable to the electric wiring plan of an ios dhcp sample configuration IOS DHCP of the corresponding pixel-driving circuit of electric current applying method of the display device among this embodiment.
In addition, pixel-driving circuit shown in is only for can be applicable to an embodiment of the display device relevant with this embodiment.Needless to say, can there be other circuit arrangement with equivalent operation function.
As shown in figure 21, dispose relevant pixel-driving circuit DCy with this embodiment and comprise p channel transistor Tr81, N channel transistor Tr82, p channel transistor Tr83, N channel transistor Tr84 and capacitor Cy.The drain terminal of p channel transistor Tr81 links to each other with contact Nya with voltage contact+V respectively with source terminal; Gate terminal links to each other with sweep trace SL and is positioned near the intersection point of sweep trace SL and signal wire DL.The gate terminal of N channel transistor Tr82 links to each other with sweep trace SL, and drain terminal and source terminal and signal wire DL and contact Nya are connected with each other.The gate terminal of p channel transistor Tr83 links to each other with contact Nyb, and drain terminal and source terminal and contact Nya and Nyc are connected with each other.The gate terminal of N channel transistor Tr84 links to each other with sweep trace SL, and drain terminal and source terminal and contact Nyb and contact Nyc are connected with each other.In addition, capacitor Cy is connected between contact Nya and the contact Nyb.Here, voltage contact+V links to each other with voltage driver shown in the foregoing description or direct high power supply voltage by pressure-wire, and applies constant high power supply voltage.
In addition, this example arrangement comprises that utilizing it to produce drive current by the light that provides from such pixel-driving circuit Dcy controls the organic EL device OEL that light produces luminosity.The contact Nyc of anode terminal and above-mentioned pixel driver circuit DCy is connected with each other, and cathode terminal links to each other with low supply voltage Vgnd separately.Here, capacitor Cy can be formed in the stray capacitance between the gate-to-source of transistor Tr 83, and except stray capacitance, can be between gate-source with capacitive element (capacitor) separately additional (interpolation).
In the drive controlling operation of the organic EL device OEL of the pixel-driving circuit Dcy with such configuration at first in the write operation cycle, write current Ipix is provided, so that when high level (selection level) sweep signal Vsel is applied to sweep trace SL, to produce operation at the light of carrying out organic EL device OEL with the predetermined levels of luminosity of the synchronous signal wire DL of this timing.Here, write current Ipix provides set positive polarity electric current, thereby makes correlated current to flow through from the direction of data driver 130B side via the pixel-driving circuit Dcy of signal wire DL.
Therefore, in transistor Tr 82 that forms pixel-driving circuit Dcy and Tr84 execution " conducting " operation, transistor Tr 81 is carried out " ending " operation, and provides and offer the corresponding positive current of write current Ipix of the signal wire DL that is applied to contact Nya.In addition, as the connection between contact Nyb and the contact Nyc, controlling this current potential between the gate-to-source of transistor Tr 83 and between source electrode-drain electrode.Thus, in capacitor Cy (between contact Nya and contact Nyb) occurred according to the voltage potential of write current poor.To accumulating and remain component of voltage (electric charge) with the corresponding electric charge of this voltage potential difference.
Subsequently, in light produces the operating cycle, applying low level (non-selection level) sweep signal Vsel to sweep trace SL when, its and this regularly synchronously with the power supply of interruption (disconnection) write current Ipix.As a result, capacitor Cy is carrying out between the transistor Tr 82 and Tr84 that " end " operate, between signal wire DL and the contact Nya and between contact Nyb and the contact Nyc, is remaining on the electric charge that is accumulated in the above-mentioned write operation by being electrically interposed in.
According to this mode, when capacitor Cy keeps charging voltage during in write operation that the voltage potential of (between the gate-source of transistor Tr 83) between holding contact Nyb and the contact Nyc is poor, and transistor Tr 83 is carried out " conducting " operation.The result, by applying said scanning signals Vsel (low level), because transistor Tr 81 is carried out " conducting " operation simultaneously, therefore the light that responds write current Ipix produces drive current and flows to organic EL device OEL from voltage contact+V (high power supply voltage) by transistor Tr 81 and Tr83, and organic EL device OEL is luminous with predetermined levels of luminosity.According to this mode, in the pixel-driving circuit relevant with this embodiment, N channel transistor Tr83 will have as being used for the transistorized function that light produces driving.
Therefore, have in write operation cycle of display board 110A of above-mentioned pixel-driving circuit (with reference to Figure 13) at display pixel EM at each line, by each signal line DL1, DL2, DL3 ... above-mentioned write current Ipix is provided.Current write current Ipix is remained component of voltage, and produce operating period at light and be provided with.According to the component of voltage that is kept, light is produced drive current offer organic EL device OEL continuously.Produce operation to continue this light with the corresponding levels of luminosity of video data d0-d3.
Therefore, as explaining in this embodiment, in fact, can produce the write current that offers display pixel (display pixel EM) according to the current value of the reference current that provides by common current power supply line.The current value that offers each write current generation circuit that forms data driver can not fluctuate.Therefore, can alleviate operating speed restriction to the charging that comes from electric current power supply line and discharge, and the operating speed that can promote data driver.
The 3rd embodiment of data driver
Subsequently, explanation is applied to the 3rd embodiment of the data driver of above-mentioned display device.
Figure 22 shows the profile block scheme of example of current generating circuit of the 3rd embodiment of the data driver that is applied in the display device relevant with the present invention.
Figure 23 shows the profile block scheme of another example of the current generating circuit that is applied to the data driver among this embodiment.
Data driver among the 3rd embodiment is applied to form the current generation section branch of current generating circuit that each write current produces the data driver of circuit with the current generation section branch of the current generating circuit of the 5th embodiment shown in Figure 11, comprises the configuration of the data driver that is equivalent to second embodiment shown in Figure 20 simultaneously.
Here, for any equivalent in the foregoing description, additional phase with or equivalent term, and from describe, simplify or omit description it.
For example, as shown in figure 22, dispose current generating circuit ILC that the write current that is provided with produces circuit and comprise that signal search part 10 shown in Figure 4 and the described current generation section of Figure 11 divide 20C in the data driver relevant with this embodiment.And current generating circuit ILC disposes operation setting circuit 70.Operation setting circuit 70 comprises phase inverter 72, provides counter-rotating to handle to the predetermined selection signal SEL that provides from system controller 150 grades; P channel transistor Tr71 will be by 72 outputs of above-mentioned phase inverter the inversion signal (inverted status) of selection signal SEL be applied to the control terminal that connects on the opposite side of signal wire DL current path, and electric current output OUTi is coupled on an end of current path; NAND circuit 73 is carried out to the anti-phase output of phase inverter 72 with from the input of the shift signal SR of shift-register circuit 131; Phase inverter 74 is carried out the counter-rotating processing to the fan-out (Sheffer stroke gate) of NAND circuit 73; And be phase inverter 75 at last, further counter-rotating is carried out in the anti-phase output of phase inverter 74 handled.
In having the current generating circuit ILC of such configuration, if input high level is selected signal SL, the transistor Tr 71 that then forms in operation setting circuit 70 is carried out " conducting " operation, current generation section divides the electric current output contact OUTi of 20C to link to each other with signal wire DL by transistor Tr 71, and current generating circuit is set to selection mode.
Simultaneously, the low level timing controling signal is input to output contact CK regularly irrelevant, that form each latch cicuit LC0-LC3 of signal latch part 10 with shift signal SR from phase inverter 72 and NAND circuit 73 and phase inverter 74 and 75; And with the high level timing controling signal be input to regularly the input contact CK*.In each latch cicuit LC0-LC3, receive and maintenance video data d0-d3, and apply the timing of high-level control signal rck to it.As a result, reference current Iref is offered current generation section divide 20C, set is according to the grading current of video data d0-d3, and the light among generation and each display pixel EM produces the corresponding write current Ipix of luminosity.Therefore, will optionally apply the write current Ipix based on video data d0-d3 regularly, that produced by the above-mentioned clock signal rck in each current generating circuit ILC and pass through signal wire DL, sequentially offer each display pixel EM to it.
On opposite side, if the selection signal SL of input low level, then transistor Tr 71 will be carried out " ending " operation, and current generation section divides the electric current output contact OUTi of 20C to be separated with signal wire DL, and current generating circuit ILC is set to non-selected state.
Immediately, the output timing of input contact CK with the shift signal SR (high level) of input contact CK* of each latch cicuit LC0-LC3 is gone in phase inverter 72 and NAND circuit 73 and phase inverter 74 and 75 responses.Timing controling signal with signal level of opposite polarity receives and maintenance video data d0-d3.Apply the timing of above-mentioned control signal rck, and produce write current Ipix according to video data d0-d3.Therefore, although produce write current Ipix according to video data d0-d3, it will be in the state of not powering to signal wire DL.
Comprise that the drive controlling class of operation of the data driver of such current generating circuit ILC is similar to the drive controlling method (with reference to Figure 18) of the display device shown in the foregoing description, and utilize and formedly in each of a plurality of current generating circuit ILC to latch part 10 it is set to signal and keeps operation; According to from shift-register circuit 131 sequentially shift signal SR1, SR2, the SR3 of output ..., it is set to selection mode.Holding signal d10*-d13* is equivalent to the inversion signal of the video data d0-d3 that the video data d0-d3 at each line sequentially receives, and it is outputed to current generation section divides 20C.
In addition, exist regularly,, produce in the powered operation, above-mentioned control signal rck optionally only is applied to the current generating circuit ILC among (it does not become high level simultaneously) a plurality of current generating circuit ILC at electric current by it.According to holding signal d10*-d13*, reference current Iref is offered current generation section divide 20C.From having in advance according to selecting a plurality of grading currents of the specified current value of this reference current Iref and set predetermine level electric current, sequentially provide by each signal wire DL1, DL2, DL3 ... the write current Ipix that produces with conventional polarity, thus it is flowed on the direction of display pixel EM.
Therefore, according to the display device relevant with this embodiment, by reference current Iref is optionally offered with each signal wire DL1, DL2, DL3 ... each current generating circuit ILC of Xing Chenging accordingly, by producing according to video data d0-d3 and gathering grading current, solved the generation of this write current based on reference current Iref.Because having, this write current can offer equating and suitable current value of each display pixel EM, and can not be subjected to the influence of variation of the component characteristic of circuit characteristic between each current generating circuit and active device transistor etc., therefore the grade display operation that can realize ideal, and can realize the enhancing of display image signals.
In addition, when producing write current in this embodiment, control signal rck carries out switching controls, so that to commutation circuit TS1-TS2 and the TS3-TS4 power supply state of the reference current Iref of each current generating circuit ILC (current generation section is divided 20C).Although explained the situation that applies the signal that is produced and output to system controller 150, the present invention is not limited thereto, can reduce the processing load in the system controller etc., and simplify circuit arrangement.For example, use current other control signals that provide at the control of the operation among each current generating circuit ILC, can construct following configuration, thereby can carry out switching controls above-mentioned commutation circuit TS1-TS2 and TS3-TS4.
For example, as shown in figure 23, above-mentioned current generating circuit ILD and current generating circuit ILC shown in Figure 22 are arranged in the configuration, thereby it can provide control signal rck, so that (promptly at the anti-phase output of formed phase inverter 74 in the operation setting circuit 70 of current generating circuit ILC, be input to the timing controling signal of the input contact CK of each the latch cicuit LC0-LC3 that is configured to signal latch part 10), divide the switching controls of carrying out among the 20C commutation circuit TS1-TS2 and TS3-TS4 in current generation section.
Promptly, for timing (the shift signal SR1 of output and the timing of SR2 from shift-register circuit 131 based on the timing controling signal of input contact CK that goes to above-mentioned each latch cicuit LC0-LC3 and CK*, and it is regularly synchronous with this), in each latch cicuit LC0-LC3, execution is used to receive and keeps the signal of video data d0-d3 to keep operation, and high-level control signal rck regularly is applied on the opposite side.Carry out electric current and produce powered operation, in this operation, produce write current Ipix, and reference current Iref is offered current generation section divide 20C according to video data d0-d3.In the drive controlling method of each of using simultaneously repetition (concurrently) these operations continuously, timing controling signal and above-mentioned control signal rck that regularly input is provided to the input contact of each latch cicuit LC0-LC3 CK will be set synchronously.Therefore, can use single timing controling signal to control each operation.
Therefore, in the processing load etc. that can reduce in the system controller, can simplify this circuit arrangement; Owing to can use the existing control signal that offers each current generating circuit ILC to carry out drive controlling simultaneously, therefore can simplify according to the maintenance of the signal in the signal latch part 10 of such configuration operation and current generation section and divide the electric current among the 20C to produce powered operation.
In addition, under Figure 22 and current generating circuit ILC shown in Figure 23 and ILD, current generating circuit LIB and these environment shown in Figure 4, for the write current that is produced by each current generating circuit ILC and ILD, although it has the circuit arrangement that is configured such that it flows through on the direction via the display pixel EM of each signal wire, the present invention is not limited thereto.It can have the circuit arrangement that is similar to current generating circuit ILA setting shown in Figure 1, thereby above-mentioned write current can be incorporated into current generating circuit ILC and ILD by signal wire from each display pixel side.
The 4th embodiment of data driver
Next explanation is applied to the 4th embodiment of the data driver of above-mentioned display device.
For the data driver relevant, briefly, in this configuration, in each signal wire, form two groups of write currents and produce circuit with this embodiment.Each group write current produces circuit and regularly locates to carry out reception, the maintenance of write current, the generation of video data at scheduled operation, and complementally and continuously carries out powered operation.In addition, when each write current produces circuit and comprises the identical configuration of current generating circuit among the 3rd embodiment with current generating circuit, each write current produces circuit provides voltage (blank screen display voltage) from appointment to signal wire, thereby each all has designated state part is set, and video data correspondingly becomes designated value.Here, in this embodiment, will offer write current from the positive reference current with constant current value of single current generator and produce circuit group.
Figure 24 shows the electric wiring plan of configuration of the 4th embodiment of the data driver in display device related to the present invention.
Figure 25 shows the electric wiring plan that the write current that is applied to the data driver among this embodiment produces an example of circuit.
Figure 26 shows the anti-phase latch cicuit of the data driver that is applied to this embodiment and selects to be provided with the electric wiring plan of an example of circuit.
Here, explanation is complementary with the configuration of above-mentioned current generating circuit.At this moment,, adopt identical or equivalent term, and from describe, simplify or omit explanation it for any equivalent in the above-described embodiments.
For example, as shown in figure 24, the data driver 130C relevant with this embodiment disposes: anti-phase latch cicuit 133A, be used for according to from system controller 150 as the shift clock signal SFC that data controlling signal provides, produce noninverting clock signal C K1 and inversion clock signal CK2; Shift register 134A, in according to noninverting clock signal C K1 and inversion clock signal CK2 displacement sampling enabling signal STR, predetermined timing place sequentially export shift signal SR1, SR2, SR3 ... (being equivalent to above-mentioned timing controling signal CLK); Two groups of write currents produce circuit group 135A and 135B, by each signal line DL1, DL2, DL3 ... power supply (drawing) sequentially be received in a line cycle from shows signal and produce the video data d0-dk that sequentially provides the circuit 160 (here, for convenience, as mentioned above, these signals are equivalent to the digital signal d0-d3 that is set to k=3), and the light among generation and each display pixel EM produces the corresponding write current Ipix of luminosity; Selection is provided with circuit 136A output and selects set-point signal (noninverting signal SLa and the inversion signal SLb of switch-over control signal SEL), so that according to from system controller 150 as the switch-over control signal SEL that data controlling signal provides, optionally operate any that above-mentioned write current produces circuit group 135A and 135B.
Here, at least dispose two groups of write currents and produce circuit group 135A and 135B, thereby the reference current Iref of public input has from current generator IR (being equivalent to above-mentioned current generator IRA) the regular constant current value that provides and from shows signal and produces the video data d0-dk that circuit 160 provides.
Two groups of write currents produce circuit group 135A and 135B has following configuration, each include a plurality of write currents produce circuit I SC1, ISC2 ... with ISD1, ISD2 ...Each write current generation circuit I SC1, ISC2 shown in Figure 25 ... with ISD1, ISD2 ... corresponding to the current generating circuit ISA among the 3rd embodiment of current generating circuit shown in Figure 6 (after this it is become write current and produces circuit I Sx), and dispose: signal latch part 10x, except current generation section is divided 20x, be equivalent to the configuration among the 3rd embodiment of current generating circuit; Designated state is provided with part 30x; And operation setting circuit 40x, according to switch-over control signal SEL, the mode of operation among each write current generation circuit I Sx is set optionally.
Here, because signal latch part 10x, current generation section divide 20x and designated state that part 30x is set and be equivalent in the signal latch part 10 shown in Fig. 6, from the detailed description of this part, omit current generation section and divide 20A and designated state that part 30A is set.
For example, as shown in figure 25, operation setting circuit 40x has following configuration, be included in the N channel transistor TN41 that forms in the current path of going to signal wire DL, and will be applied to control terminal from the selection set-point signal of selecting circuit 136A is set (noninverting signal SLa or inversion signal SLb).42 pairs of phase inverters select the set-point signal to carry out the counter-rotating processing.NAND circuit 43 carry out to from the shift signal SR of shift register 134A (SR1, SR2 ...) and the input of the anti-phase output of phase inverter 42.The fan-out of 44 pairs of NAND circuit 43 of phase inverter is carried out counter-rotating and is handled, and the counter-rotating processing is further carried out in the anti-phase output of 45 pairs of phase inverters 44 of phase inverter.
Produce among the circuit I Sx at write current with such configuration, if from selecting to be provided with input high level selection set-point signal (write current produces the control signal that circuit is set to selection mode) the circuit 136A, then formed N channel transistor TN41 will carry out " conducting " operation in operation setting circuit 40x.Current generation section divides the electric current output contact OUTi of 20x to link to each other with signal wire DL by N channel transistor TN41.Simultaneously, the low level timing controling signal of going to signal latch part 10x input contact CK is regularly irrelevant with the output from the shift signal SR of phase inverter 42, NAND circuit 43 and phase inverter 44 and 45, and the high level timing controling signal is input to input contact CK* regularly.Receive video data d0-d3, and divide the write current Ipix of 20x generation according to video data d0-d3 by current generation section.
When video data d0-d3 being set to entirely zero (0), simultaneously, interrupt (disconnection) current generation section and divide the Ipix of the write current among the 20x, and the light of carrying out in the designated state of display pixel EM producing operation (for example blank screen display operation).Apply response and part 30x divides the output contact OUTi electric current of 20x to current generation section the given voltage Vbk (blank screen display voltage) of blank screen display operation is set by designated state.
Therefore, in not comprising the ordinary grade display operation of blank screen show state, will offer display pixel EM by signal wire DL according to the write current Ipix that video data d0-d3 produces.When the blank screen display operation, disconnecting the power supply of above-mentioned write current Ipix, will be scheduled to given voltage Vbk (blank screen display voltage) and be applied to signal wire DL.
On the contrary, if from selecting to be provided with input low level selection set-point signal (the write current function circuit is set to the control signal of non-selected state) the part 136A, N channel transistor TN41 will carry out " ending " operation, and current generation section divide 20x electric current output contact OUTi will with signal wire DL isolated (separation).
Simultaneously, at this moment, regularly corresponding with the output of shift signal SR, the timing controling signal that will have complementation (coupling) signal level be input to from the output of the shift signal SR of phase inverter 42 and NAND circuit 43 and phase inverter 44 and 45 regularly input contact CK and the input contact CK* of corresponding signal latch part 10x, carry out reception, to the maintenance of write current Ipix with produce operation to video data d0-d3.Therefore, although produce write current Ipix according to video data d0-d3, it will be in not the state to signal wire DL power supply, and must write current produce circuit and be set to non-selected state.Therefore, be provided with the circuit 136A from the selection of describing after a while, be input to the signal level that two groups of write currents produce the selection set-point signal (noninverting signal SLa and the inversion signal SLb of switch-over control signal SEL) of circuit group 135A and 135B by suitable setting, can two groups write current any selection mode of producing circuit group 135A and 1 35B be set to selection mode, and another is set to non-selected state.
And briefly, anti-phase latch cicuit 133A and select is provided with circuit 136A and has equivalent electrical circuit configuration shown in Figure 26 A and 26B, so that use the configuration (for example complementary transistor circuit as shown in Figure 2) that comprises a plurality of known negative circuits.
Particularly, for anti-phase latch cicuit 133A and selection circuit 136A is set, displacement control signal SFC or switch-over control signal SEL are input to the input contact INs (anti-phase latch cicuit 133A or selection are provided with the input terminal of circuit 136A) of phase inverter INV1, and the output contact of phase inverter INV1 links to each other with the input contact of phase inverter INV2.The output contact of phase inverter INV2 links to each other with the input contact of phase inverter INV4.In addition, the number that above-mentioned displacement control signal SFC or switch-over control signal SEL is input to phase inverter INV3 claims terminals, and output contact links to each other with the input contact of phase inverter INV5.With when the input contact of phase inverter INV5 and phase inverter INV6 links to each other, the output contact of phase inverter INV5 links to each other with the input contact of phase inverter INV4 and phase inverter INV7 at the output contact of phase inverter INV4.In addition, the output contact of phase inverter INV6 links to each other with the noninverting lead-out terminal OUTs that anti-phase latch cicuit 133A or selection are provided with circuit 136A, and the output contact of phase inverter INV7 links to each other with the sub-OUTs* of reversed-phase output that anti-phase latch cicuit 133A or selection are provided with circuit 136A.
Be provided with among the circuit 136A in anti-phase latch cicuit 133A or selection,, then keep relevant signal level with phase inverter INV5 by phase inverter INV4 if apply displacement control signal SFC or switch-over control signal SEL with such structure.The not inversion signal of current demand signal level and each of inversion signal are all outputed to shift-register circuit 134A from noninverting lead-out terminal OUTs and anti-phase terminal OUTs*, as noninverting clock signal C K1 and inversion clock signal CK2.In addition, will be not inversion signal SLa and inversion signal SLb offer write current produce circuit group 135A (each write current produce circuit I LA1, ILA2 ...) and write current generation circuit group 135B (each write current generation circuit I LB1, ILB2 ...).
The drive controlling method
Next, the drive controlling method of the display device with above-mentioned configuration will be explained with reference to the accompanying drawings.
Figure 27 shows the sequential chart of an example of the drive controlling operation in this embodiment the data driver.
Except the 4th embodiment of Figure 24 and data driver shown in Figure 25, correspondingly also make an explanation with reference to the configuration of the 3rd embodiment of current generating circuit shown in Figure 6.
At first, operate for the drive controlling among the data driver 130C, signal maintenance operation receives from shows signal generation circuit 160 and offers formed each signal latch part 10x each the electric current write current generation circuit that is made of above-mentioned write current generation circuit group, and during the fixed cycle it is kept.According to the holding signal d10-d13 of the video data d0-d3 that keeps operation to be received by current demand signal, in write current generation circuit I Sx, form current generation section and divide 20x.When order is carried out electric current and is produced powered operation, produce write current Ipix according to above-mentioned video data d0-d3, and by each signal line DL1, DL2 ... offer each display pixel EM.When selecting to be provided with circuit 136A and carrying out two groups of write currents and produce these sequence of operations the circuit group, when producing the above-mentioned electric current generation of one of circuit group execution powered operation from write current, this finishes by repeating blocked operation, so that at opposite side, produce the circuit group above-mentioned signal maintenance of (walking abreast) execution simultaneously operation from write current.
Especially, in the data driver relevant with this embodiment, when realizing the blank screen display operation, wherein carry out light simultaneously and produce operation with the minimum levels of luminosity of the pre-display pixel that constitutes display board, for example, except keeping operation and electric current, above-mentioned signal produces the powered operation, disconnect to all signal wire DL1, DL2 ... the power supply of write current Ipix the time, to its control in case with given voltage Vbk (blank screen display voltage) be applied to all signal wire DL1, DL2 ...
At first, keep operation for signal, as shown in figure 27, producing after circuit group is set to selection mode by selecting to be provided with write current of circuit 136A, each write current produce signal latch part 10x that this write current that forms among circuit I Sx produces circuit group according to shift signal SR1, SR2 ... sequentially export from shift-register circuit 134A.This sequence of operation ground receive display pixel EM according to each line (that is, each signal line DL1, DL2 ...) the video data d0-d3 of displacement, and carry out continuously in the cycle at a line.Sequentially, produce the signal latch part 10x of circuit I Sx from the write current that receives this video data d0-d3, divide 20x output holding signal d10-d13 (up to according to thereafter switch-over control signal SEL, produce write current that circuit group is set to non-selected state and opposite side and produce cycle till circuit group is set to selection mode) from signal latch part 10x to current generation section by selecting to be provided with write current of circuit 136A from the constant cycle.
In addition, as shown in figure 27, produce in the powered operation at electric current, under " conduction and cut-off " state, current generation section divide a plurality of switching transistors that form among the 20x according to by each signal line DL1, DL2 ... the above-mentioned holding signal d10-d13 that order provides, control flow to the resultant current of the transistorized grading current of grading current that links to each other with the switching transistor of carrying out " conducting " operation, as write current Ipix.
Here, write current Ipix is set, thus in the constant cycle, at least simultaneously concurrently to each signal line DL1, DL2 ... this electric current is provided.In addition, in the above-described embodiments, produce a plurality of grading currents, described grading current has in advance at single reference current Iref according to the predetermined ratio of transistor size appointment (for example 2 n, n=1,2,3 ...) current value (seeing the formula of claim 12 and 15); By above-mentioned holding signal, utilize " conduction and cut-off " operation of switching transistor, select and set predetermine level electric current; Produce the write current Ipix of negative polarity, and write current Ipix flow through, thus from signal wire DL1, DL2 ... draw this electric current on the direction of the data driver 130A of side.
In the blank screen display operation, as shown in figure 27, be set to black display state (holding signal d10-d13 is complete zero (0)) by video data d0-d3, for dividing any switching transistor that forms among the 20x (transistor Tr 26-29 shown in Figure 3) in the current generation section of carrying out " ending " operation, interrupt (disconnection) grading current, and suspend the power supply of write current Ipix.Simultaneously, at this moment, by designated state the blank screen show state (holding signal d10-d13 is set to the state of (0)) that formed NOR circuit 31 among the part 30x is judged video data is set, given voltage applies transistor T N32 and specifies " conducting " operation, and will with blank screen show corresponding given voltage Vbk (blank screen display voltage) (light of minimum levels of luminosity produces operation) sequentially be applied to each signal line DL1, DL2 ...
Be controlled at that formed write current produces circuit group among the data driver 130A, be selection mode thereby two groups are arranged alternately.For example, the display pixel EM of odd line (odd-numbered line) will be offered from the write current Ipix that write current produces circuit group 135A, and the display pixel group of the even line (even-numbered line) on the opposite side will be offered from the write current Ipix that write current produces circuit group 135B.
The result, at data driver 130C relevant and display device 100A with this embodiment, utilize with each signal line DL1, DL2 ... when each write current generation circuit I Sx that forms accordingly carries out the ordinary grade display operation, produce, gather grading current, and utilize write current Ipix to each display pixel EM power supply with suitable current value according to video data d0-d3.And, when the blank screen display operation, interrupt (disconnection) write current Ipix from current generating circuit ISx at opposite side.Since will produce in response to the light of the minimum levels of luminosity of display pixel EM the predetermined blank screen display voltage of operation be applied to each signal line DL1, DL2 ... can obtain desirable grade shows, and when the blank screen display operation, given voltage can successfully stablize each signal line DL1, DL2 ... signal level.It can transfer to the blank screen show state apace, and can realize the demonstration response characteristic of display device and the raising of image quality.
Write current at data driver 130C produces among the circuit I Sx, in the configuration of applied current mirror image circuit, by the transistorized channel width of a plurality of grading currents that constitutes current mirror circuit is set with respect to reference current transistor, thereby make each have predetermined ratio (for example 2 nGrade), utilizes video data d0-d3 (digital signal), with respect to from the single reference current that single current generator provided, a plurality of grading currents that have by the current value of above-mentioned ratio appointment are flow through with two or more bits.Because write current Ipix has 2 nThe current value of grade can produce the suitable set to these electric currents.Therefore, quite simple circuit arrangement can produce the write current that is made of the analog current that has with the corresponding suitable current value of video data, and can produce operation with the light that suitable levels of luminosity be carried out display pixel EM.
In addition, to comprise that wherein data driver that two groups of write currents produce circuit is applied to be aligned to the situation of each signal line on the display board among this embodiment although explained, but the present invention is not limited thereto, and can use following data driver, for example, described data driver is by serial received and keep video data, carries out the generation of electric current powered operation and write current, comprises that the single write current to each signal line produces circuit.
The 5th embodiment of data driver
Next explanation is applied to the 5th embodiment of the data driver of above-mentioned display device.
Although it has current drain method circuit arrangement, wherein in the 4th embodiment of above-mentioned data driver from display pixel EM at data driver side projected current, but can use the circuit arrangement of following electric current applying method, wherein make write current flow into (pouring in) in the direction of display pixel from data driver.The 5th embodiment of data driver comprises the circuit arrangement of electric current applying method.
In addition, the data driver of the write current generation circuit relevant with this embodiment is similar to the 4th embodiment of above-mentioned data driver.Although form two set in each signal line, the write current with scheduled operation each set regularly produces circuit and comprises complementation and receive continuously and keep video data, and the configuration that produces write current and execution powered operation.When video data became designated value, it had the configuration that given voltage (blank screen display voltage) is provided to signal wire.Here, in this embodiment, provide negative reference current to have the constant current value that produces circuit group from single current generator to write current.
Figure 28 shows the electric wiring plan of configuration of the 5th embodiment of the data driver in the display device relevant with the present invention.
Figure 29 shows the electric wiring plan that the write current that is applied to the data driver among this embodiment produces an example of circuit.
Here, the explanation that the configuration that provides with above-mentioned current generating circuit is complementary.In addition, any equivalent with reference in above-mentioned each embodiment adopts identical or equivalent term, and after this will simplify or omit the explanation to it from describe.
For example, as shown in figure 28, the data driver 130D relevant with this embodiment formed by following assembly: anti-phase latch cicuit 133B and shift-register circuit with the configuration that is equivalent to above-mentioned the 4th embodiment, by it, sequentially receive the video data d0-d3 of a line in the cycle, with based on from shift signal SR1, the SR2 of shift-register circuit 134B ... incoming timing, produce luminosity according to the light among each display pixel EM and produce write current Ipix; Write current produces circuit group 135C and 135D, by each signal line DL1, DL2 ... power supply (can be applicable to pour in/flow into); And select circuit 136B is set, according to switch-over control signal SEL, optionally operate any that above-mentioned write current produces circuit group 135C and 135D.
Here, form two groups of write currents and produce circuit group 135C and 135D, thereby at least when jointly importing video data d0-d3, can draw reference current Iref publicly with the constant current value of regulating by current generator IR.
Two groups of write currents produce circuit group 135C and 135D each include a plurality of write currents produce circuit I SE1, ISE2 and ISF1, ISF2 ...Each write current generation circuit I SE1, ISE2 and ISF1, ISF2 ... be equivalent to current generating circuit ISB shown in Figure 8 and shown in Figure 29 (after this be commonly called write current and produce circuit I Sy).Digital latch part 10y is equivalent to the configuration of the 4th embodiment of current generating circuit.Divide 20y and designated state except current generation section and be provided with the part 30y, the operation setting circuit optionally is provided with the mode of operation that each write current produces circuit I Sy according to switch-over control signal SEL.
Here, be equivalent to the signal latch part 10 shown in Fig. 8 because signal latch part 10y, current generation section divide 20y and designated state that part 30y is set, therefore from the detailed description of this part, omit current generation section and divide 20B and designated state that part 30B is set.
For example, as shown in figure 29, operation setting 40y has following configuration, comprise p channel transistor TP101, the inversion signal that is used for to the selection set-point signal (noninverting signal SLa or inversion signal SLb) of circuit 136B to be set from selection is applied at the formed control terminal of the current path of going to signal wire DL.102 pairs of above-mentioned selections of phase inverter set-point signal is carried out counter-rotating and is handled.NAND circuit 103 is carried out the input to the shift signal SR of the anti-phase output of only depositing circuit 134B from phase inverter 102 and displacement, as input.Phase inverter 104 is carried out the counter-rotating of the fan-out of NAND circuit 103 is handled, and 150 pairs of further counter-rotatings of anti-phase outputs execution from phase inverter 104 of phase inverter are handled.
Produce among the circuit I Ly at write current with such configuration, if from selecting to be provided with input high level selection set-point signal the circuit 134B, then the p channel transistor TP101 in operation setting circuit 40y will carry out " conducting " operation, and current generation section divides the electric current output contact OUTi of 20y to link to each other with signal wire DL by p channel transistor TP101.Simultaneously, at this moment, the low level timing controling signal from phase inverter 102, NAND circuit 103 and phase inverter 104 and 105, is input to the contact CK that exports irrelevant signal latch part 10y with the timing of shift signal SR, and the high level timing controling signal is input to contact CK* regularly.Receive video data d0-d3, and divide the write current Ipix of 20y generation according to video data d0-d3 by current generation section.
When video data d0-d3 being set to entirely zero (0), when interruption (disconnection) current generation section is divided the output of the write current Ipix in 20, by designated state the given voltage Vbk (blank screen display voltage) that part 30y will respond the blank screen display operation is set and is applied to the electric current output contact OUTi that current generation section is divided 20y, thereby the light that can carry out display pixel in the state of appointment produces operation (for example blank screen display operation).
Therefore, in the ordinary grade display operation, except the blank screen show state, predetermined black given voltage Vbk (blank screen display voltage) is applied to signal wire DL, to offer display pixel EM by signal wire DL according to the write current Ipix that video data d0-d3 is produced, thereby the providing of above-mentioned write current Ipix (selection mode that write current produces circuit) in the blank screen display operation will be provided.
On the other hand, if from selecting to be provided with input low level selection set-point signal the circuit 134B, then p channel transistor TP101 will carry out " ending " operation, and current generation section divides the electric current output contact OUTi of 20y to be separated with signal wire DL.In addition, at this moment, the output timing of the shift signal SR of response phase inverter 102, NAND circuit 103 and phase inverter 104 and 105, the timing controling signal that will have the complementary signal level is input to input contact CK and the input contact CK* of signal latch part 10y.By receiving and keeping video data d0-d3, carry out the generation operation of write current Ipix.
Therefore, compare with above-mentioned the 4th embodiment, although produce write current Ipix according to video data d0-d3, it will be in not the state to signal wire DL power supply, and must write current produce circuit and be set to non-selected state.
Identical such as the operation of drive controlling such as data driver 130D with above-mentioned first embodiment, and in signal keeps operating, be provided with.Produce formed signal latch circuit 10y among the circuit I Sy for each write current that produces circuit group at the write current that is set to selection mode, according to from shift-register circuit 134B sequentially output shift signal SR1, SR2 ... sequentially receive the video data d0-d3 of each bar line, and the holding signal d10-d13 that will be equivalent to the reverse signal of video data d0-d3 outputs to current generation section and divides 20y.
In addition, electric current produces powered operation and selects and set predetermine level electric current from have in advance a plurality of grading currents according to the current value of holding signal d10*-d13* appointment.Here, produce the write current Ipix of positive polarity, thus from data driver 130B side via each signal line DL1, DL2 ... the direction of display pixel EM on correlated current (can be applicable to pour in/flow into) sequentially is provided.
In the blank screen display operation, by with video data d0-d3 ... be set to blank screen show state (holding signal d10-d13 is set to zero (0) entirely), simultaneously, suspend generation and write current Ipix power supply that current generation section is divided the grading current among the 20y.Be provided with among the part 30y at designated state and judge the blank screen show state, and will show with blank screen (light of minimum levels of luminosity produces operation) corresponding given voltage Vbk sequentially be applied to each signal wire DL1, DL2 ...
Therefore, also the display device of having used the data driver 130D relevant with this embodiment is provided with, by according to from each signal line DL1, DL2 ... each write current that forms accordingly produces the video data d0-d3 of circuit I Sy, produce and the set grading current, can provide the Ipix of the write current with suitable current value to each display pixel EM, and the grade display operation that can realize ideal.On opposite side, in the blank screen display operation, when the write current Ipix that disconnects from each current generating circuit ISy, by will be scheduled to the blank screen display voltage be applied to each signal line DL1, DL2 ... it the blank screen show state can be transferred to apace, and the demonstration response characteristic of display device and the raising of image quality can be realized.
The 6th embodiment of data driver
Next explanation is applied to the 6th embodiment of the data driver of above-mentioned display device.
When writing the generation circuit, receive, keep also to produce write current at each signal line formation; And for the configuration of carrying out powered operation at predetermined regularly place, it is to comprise that configuration identical with the data driver of the 5th embodiment and write current produce the system of circuit that each write current produces circuit.Especially, it has designated state part is set, and has and can correspondingly provide the configuration of given voltage (resetting voltage) conduct at the designated value of video data to signal wire.Here, in this embodiment, negative reference current produces circuit group from single current generator to write current steady state value is provided.
Figure 30 shows the electric wiring plan of configuration of the 6th embodiment of the data driver in display device related to the present invention.
Here,, adopt identical or equivalent term, and from describe, simplify or omit explanation it for any equivalent in the above-described embodiments.
For example, as shown in figure 30, data driver 130E in this embodiment has following configuration, comprises that shift register course of action 131C or circuit bank 300A, write current produce circuit group 137A and steady current generator IR.When displacement enabling signal SRT being shifted according to the shift clock signal SFC that provides as data controlling signal from system controller 150, shift register course of action 131C predetermined regularly place output shift signal SR1, SR2, SR3 ...Circuit bank 300A comprises or circuit 301,302,303 ... timing controling signal CLK is outputed to the write current of mentioning after a while produce group 137A, as the exclusive disjunction result, its input signal be set to according to system controller 150 from shift register 131C as from each shift signal SR1, SR2, SR3 ... the reseting controling signal RST (being equivalent to above-mentioned timing controling signal CLK) that provides of data controlling signal.Write current produce circuit group 137A comprise a plurality of write currents produce circuit PXA1, PXA2, PXA3 ... (be equivalent to the current driving circuit ISA among the 3rd embodiment of current generating circuit.Afterwards, for convenience, it is described as write current produces circuit PXA), its according to from each or circuit 301,302,303 ... timing controling signal CLK output, sequentially be received in video data d0-dk that a line provides from system controller 150 order in the cycle (here, for convenience of description, be equivalent to the above-mentioned digital signal d0-d3 that is set to k=3), produce write current Ipix according to the luminosity in each display pixel EM of display board 110B, and offer each signal line DL1, DL2, DL3 ...Steady current generator IR by common reference electric current supply lines Ls to each write current that forms in the outside of data driver 130E produce circuit PXA1, PXA2, PXA3 ... reference current with constant current value Iref is provided regularly.
Here, write current generation circuit PXA1, PXA2 and PXA3 ... comprise that the write current among the 5th embodiment that is equivalent to data driver shown in Figure 29 produces the configuration of circuit I Sy, have signal latch part, current generation section branch and designated state part is set.
Pixel-driving circuit
Subsequently, brief explanation is applied to the pixel-driving circuit of each the display pixel EM of the display board 110B in the display device relevant with this embodiment.
Figure 31 shows the electric wiring plan with the display device another example, that can be applicable to this embodiment of the configuration of the corresponding pixel-driving circuit of electric current applying method.
In addition, the pixel-driving circuit shown in here is only for can be applicable to an example of the display device relevant with this embodiment.Needless to say, possible other have the circuit arrangement of equivalent function.
As shown in figure 31, the pixel-driving circuit DCx that is applied to this example arrangement comprises p channel transistor Tr91, p channel transistor Tr92, p channel transistor Tr93, N channel transistor Tr94 and capacitor Cx.P channel transistor Tr91 utilizes drain terminal to link to each other with power supply Vdd contact respectively, utilizes source terminal to link to each other with contact Nxa, and utilizes gate terminal to link to each other with sweep trace SLa near the point of crossing of sweep trace SLa-SLb and signal wire DL.P channel transistor Tr92 utilizes drain terminal to link to each other with signal wire DL respectively, utilizes source terminal to link to each other with contact Nxa, and utilizes gate terminal to link to each other with sweep trace S1b.P channel transistor Tr93 utilizes drain terminal to link to each other with contact Nxa respectively, utilizes source terminal to link to each other with contact Nxc, and utilizes gate terminal to link to each other with contact Nxb.N channel transistor Tr94 utilizes drain terminal to link to each other with contact Nxb respectively, utilizes source terminal to link to each other with Nxc, and utilizes gate terminal to link to each other with sweep trace SLa.Capacitor Cx (retention volume, charge storage devices) is connected between contact Nxa and the contact Nxb.Here, power contact Vdd links to each other (omitting from figure) with the high voltage potential power supply by supply lines, and constant high-potential voltage is applied to regularly predetermined.
In addition, wherein utilize anode terminal to link to each other respectively, and utilize cathode terminal link to each other with low suppling voltage Vgnd (for example ground voltage) with the contact Nxc of above-mentioned pixel-driving circuit DCx by each organic EL device OEL from the luminosity of the light emission drive current of pixel-driving circuit DCx control.Here, the stray capacitance that capacitor Cx can form between the gate-source of N channel transistor Tr93, and except stray capacitance, capacitive element (capacitor) can be attached between the gate-source discretely.
Drive controlling operation with the organic EL device OEL among the pixel-driving circuit DCx of such configuration is at first during the write operation cycle, Vsel* is applied to sweep trace SLb with the low level sweep signal, and it is applied to sweep trace SLa with high level (selection level) sweep signal Vsel.Subsequently, regularly synchronous with this, pixel-driving circuit Dcx offers signal wire DL with write current Ipix, so that carry out the light emission operation of organic EL device OEL with the predetermined luminance grade.Here, provide and be provided with the write current Ipix electric current of positive polarity, thereby make suitable electric current flow through (pouring in) via the direction of the display pixel EM (pixel-driving circuit DCx) of signal wire DL from data driver 130E side.
Therefore, the transistor Tr 92 and the Tr94 that constitute pixel-driving circuit DCx carry out " conducting " operation, and transistor Tr 91 is carried out " ending " operation, and will be applied to contact Nxa with the corresponding positive potential of write current Ipix that offers signal wire DL.In addition, because contact Nxb and contact Nxc link together immediately, the voltage potential between the gate-source of transistor Tr 93 is controlled to be the equivalent voltage current potential.Therefore, when transistor Tr 93 is carried out " ending " operation, at (between contact Nxa and contact Nxb) between the end of capacitor Cx, it is poor to have occurred according to the voltage potential of the recruitment of write current Ipix, and the corresponding electric charge of accumulation and this voltage potential difference correlation, and remain component of voltage.
Subsequently, in cycle, when regularly synchronous with this, sweep signal Vsel is applied to sweep trace SLa with low level (non-selected level) in light emission operation, and when high level sweep signal Vsel* also is applied to sweep trace SLb, the power supply of write current Ipix of having interrupted (disconnection).Therefore, capacitor Cx remains on execution and " ends " stored charge in the transistor Tr 92 of operation and the above-mentioned write operation of Tr94, and carries out electricity interruption between signal wire DL and contact Nxa and contact Nxb and contact Nxc.
Therefore, when capacitor Cx keeps (storage) charging voltage during in write operation that the voltage potential of (between the gate-source of transistor Tr 93) between holding contact Nxa and the contact Nxb is poor, and transistor Tr 93 is carried out " conducting " and is operated.
In addition, by applying said scanning signals Vsel (low level), transistor Tr 91 is carried out " conducting " operation simultaneously.Light emission drive current (electric charge that is kept in capacitor Cx) according to write current Ipix flows into organic EL device OEL by transistor Tr 91 and Tr93 from power contact Vdd (high power supply voltage), and organic EL device OEL is luminous with the predetermined luminance grade.Therefore, in being applied to the pixel-driving circuit DCx of this embodiment, transistor Tr 93 has as the transistorized function that is used for light emitting drive.
The drive controlling method
Next will explain the operation of display device with reference to the accompanying drawings with above-mentioned configuration.
Figure 32 shows the sequential chart of an example of the drive controlling operation in the data driver of this embodiment.
Figure 33 is the sequential chart of an example of the drive controlling operation of display board in this embodiment.
Here, except configuration shown in Figure 30, the configuration with reference to figure 4 and current generating circuit shown in Figure 5 is correspondingly made an explanation.
Drive controlling operation among the data driver 130E is carried out by sequentially setting up reset operation, signal maintenance operation and electric current generation powered operation.At first, before described signal keeps operation after a while, reset operation by produce at above-mentioned each grading current circuit PXA1, PXA2, PXA3 ... in the designated state that forms part is set, with given voltage Vr (resetting voltage) be applied to each signal line DL1, DL2, DL3 ...Receive and keep from shows signal produce circuit 160 offer each grading current produce circuit PXA1, PXA2, PXA3 ... in the time of the video data d0-d3 of formed data latching part, signal keeps operation according to this video data d0-d3, exports inversion signal during the fixed cycle.Electric current produces powered operation to be passed through based on the output from the data latching part, according to come comfortable each grading current produce circuit PXA1, PXA2, PXA3 ... in the above-mentioned video data d0-d3 that divides of formed current generation section produce write current Ipix, respectively by each signal line DL1, DL2, DL3 ... to each display pixel EM power supply.
In addition, during other cycles outside the cycle that signal maintenance operation in carrying out a horizontal selection cycle and electric current produce powered operation, for example, at return line in the cycle, to each grading current produce circuit PXA1, PXA2, PXA3 ... carry out above-mentioned reset operation simultaneously.On the contrary, except the return line of a horizontal selection cycle in the cycle the cycle, each grading current produce circuit PXA1, PXA2, PXA3 ... in sequentially carry out signal and keep operation and electric current generation powered operation.
Here, shown in figure 32, during by the return line cycle before keeping operation at signal, provide the reset operation of high level reseting controling signal RST from system controller 150, with high level timing controling signal CLK from each or circuit 301,302,303 ... output to each grading current produce circuit PXA1, PXA2, PXA3 ... in set data latching part.In addition, regularly synchronous with this, provide the corresponding video data d0-d3 of light emission operation (being equivalent to the blank screen display operation) with the minimum brightness grade by produce circuit 160 from shows signal, as reseting data, in each data latching part, carry out reception and the maintenance (that is, complete zero (0)) of suitable video data d0-d3 simultaneously.
Subsequently, by from each or circuit 301,302,303 ... to each grading current produce circuit PXA1, PXA2, PXA3 ... data latching part output low level timing controling signal CLK when low level reseting controling signal RST is provided, the noninverting output signal of video data d0-d3 of storage is as mentioned above outputed to designated state part is set, and with given voltage Vr (resetting voltage) be applied to each signal wire DL1, DL2, DL3 ...Therefore, especially each signal line DL1, DL2, DL3 ... distribution electric capacity, in capacitance component stored charge, for example with each signal line DL1, DL2, DL3 ... set retention volume (capacitor Cx) will discharge among the display pixel EM that links to each other, and each current potential is set to predetermined low-potential state.
In addition, keep in the operation at signal, shown in figure 32, by low level reseting controling signal RST is provided from system controller 150, shift signal SR1, the SR2 that response is sequentially exported from shift register 131C, SR3 ... the timing controling signal CLK of signal level output to each grading current produce circuit PXA1, PXA2, PXA3 ... the data latching part.Sequentially receiving the timing be used to self-timing control signal CLK with (promptly from the display pixel EM of each line of each data latching part, each signal wire DL1, DL2, DL3 ...) the video data d0-d3 that changes accordingly becomes high level, and carry out continuously in the cycle at a line.In addition, in the fixed cycle (for example, up to subsequently high-frequency signal SR1, SR2, SR3 of output ... till cycle) keep wherein partly receiving the reversed-phase output signal of video data d0-d3 and output to the state of each current generation section in dividing by data latching.
In addition, produce in the powered operation at electric current, according to the reversed-phase output signal of output from above-mentioned data latching part, be controlled at " conduction and cut-off " state of a plurality of switching transistors (switching transistor Tr26-Tr29 shown in Figure 3) set in each current generation section branch.By each signal line DL1, DL2, DL3 ... sequentially provide the resultant current of the grading current that flows into the grading current transistor (transistor Tr 22-Tr25 shown in Figure 3) that links to each other with the switching transistor of carrying out " conducting " operation, as write current Ipix.
Here, for example, set up according to all signal wire DL1, DL2, DL3 ... write current Ipix, thereby can during the fixed cycle, provide it concurrently at least.In addition, in aforesaid embodiment, produce a plurality of grading currents, this grade electric current has with respect to reference current Iref in advance according to the predetermined ratio of transistor size appointment (for example 2 n, n=0,1,2,3 ...) current value.When switching transistor is carried out " conduction and cut-off " operation according to above-mentioned reversed-phase output signal, selection and the predetermined grading current of set; Produce the write current Ipix of positive polarity; And current write current Ipix is provided, thus make its from signal wire DL1, the DL2 of data driver 130E side, DL3 ... direction on flow through (pouring in).
In being applied to this embodiment of data driver 130E, as shown in figure 30, on the contrary, provide the common reference electric current supply lines Ls of reference current Iref to have fixed value by it from current generator IR, and a plurality of grading current produce circuit PXA1, PXA2, PXA3 ... has configuration in parallel.Owing to produce circuit PXA1 according to each grading current, PXA2, PXA3, in video data d0-d3, write current Ipix is offered each signal line DL1 simultaneously concurrently, DL2, DL3, (display pixel EM), offer each grading current by reference current supply lines Ls and produce circuit PXA1, PXA2, PXA3, electric current be not the reference current Iref that self provides by current generator IR, but the electric current that produces circuit corresponding to a plurality of grading currents (promptly, be equivalent to the quantity of the signal wire of in display board 110B, being arranged, for example m bar line).Therefore, the electric current of the current value (Iref/m) with five equilibrium will be provided.
Therefore, can circuit arrangement be set with m ratio doubly, this consider provide each grading current produce circuit PXA1, PXA2, PXA3 ... above-mentioned current value (Iref/m).Form each grading current produce circuit PXA1, PXA2, PXA3 ... the current generation section current mirror circuit part of dividing in this current value ratio (the channel width ratio of grading current transistor AND gate reference current transistor) of each grading current and reference current is set.
In addition, as producing other set configurations in the part at each grading current, switching device shifter is set, according to from produce such as each grading current circuit PXA1, PXA2, PXA3 ... shift-register circuit 131C in export shift signal SR1, SR2, SR3 ..., optionally carry out " conducting " operation.When only according to video data d0-d3 when electric current produces powered operation and produces write current Ipix in the cycle, remain from the reference current Iref of above-mentioned current generator IR constant, and optionally to each grading current produce circuit PXA1, PXA2, PXA3 ... power supply.
Figure 33 shows the drive controlling operation among the display board 110B, and a scan round signal Tsc shows required image information on the screen of a round-robin display board 110B of expression.In a scan round period T sc, select the display pixel EM that links to each other with the invisible scanning line.Write operation period T se (selection cycle) writes and the corresponding write current Ipix of video data d0-d3 that provides from data driver 130A, and it is stored in signal voltage.According to the signal voltage of being stored,, light emission drive current is offered organic EL device OEL according to above-mentioned video data.The light that the light emission operation of carrying out predetermined luminance grade (Tsc=Tse+Tnse) is set produces operating cycle Tnse (the non-selected cycle of display pixel EM), and carries out the drive controlling that is equivalent to above-mentioned pixel-driving circuit DCx in each operating cycle.Here, write operation period T se is set at each line, thus can time of occurrence overlapped.In addition, the electric current that write operation period T se is set at least be included in above-mentioned data driver 130A produces the cycle that the fixed cycle of write current Ipix is provided concurrently to each signal line in the powered operation.
Particularly, in write operation period T se to display pixel EM, as shown in figure 33, by sweep trace SLa and the SLb of the display pixel EM of (i line) from scanner driver 120B to specified line, carry out and store the operation that offers the write current Ipix of each signal line DL from data driver 130A as component of voltage concurrently simultaneously at the prearranged signals level.In light operating cycle Tnse subsequently, by will offering organic EL device OEL continuously based on the light emission drive current of institute's stored voltage component during above-mentioned write operation, keep with the luminous operation of the corresponding brightness degree of video data.
As shown in figure 33, by to each line of the display pixel group that constitutes display board 110B repeatedly order carry out so a series of drive controlling operations, write the video data at a screen, each display pixel EM is luminous with the predetermined luminance grade, and shows required image information.
Therefore, according to data driver and the display device relevant with this embodiment, by each signal line DL, from each grading current produce circuit PXA1, PXA2, PXA3 ... display pixel EM group to specified line provides write current Ipix.Especially, the write current Ipix that is produced is by constituting with the constant reference current Iref that can not fluctuate and provide based on the signal level from the video data d0-d3 of a plurality of digital signal bits of current generator IR (by common reference electric current supply lines Ls).During the power-on time (select time) of the write current Ipix of display pixel EM, even setting up briefly by the relatively low levels of luminosity of uses such as high-resolution display board (when the current value of write current Ipix when being insignificant) under the situation that light produces operation, can eliminate and offer data driver (each grading current generation circuit PXA1, PXA2, PXA3,) with the influence of the transmission lag in the signal that produces write current Ipix, the reduction of operating speed that can the control data driver, and can realize the demonstration response characteristic of display device and the raising of image quality.
In addition, particularly, under the situation of write current Ipix to the powered operation of each display pixel EM, the signal in data driver 130E keeps operation and electric current to produce before the powered operation, and the resetting voltage that constitutes constant low-voltage is applied to each signal line DL.Because can waiting the electric charge that accumulated in the capacitive character distribution (stray capacitance) on appending to signal wire and the capacitive element retention volume (the capacitor Cx of pixel-driving circuit) of display pixel EM, data driver fully discharges, therefore, can carry out initialization (resetting) to display device.When grading current that the selection cycle of temporary transient display pixel EM is set to be write according to the update displayed data, particularly when carry out light generation operation with extra high levels of luminosity after, when carrying out the light generation with low levels of luminosity immediately, can eliminate by the influence that electric charge caused remaining in above-mentioned capacitive element, and can shorten the required time of stabilization signal level.Therefore, because the stability roots level of data according to the show apace, therefore, can make the signal level that is applied to signal wire and display pixel and the writing speed of display pixel is risen.In addition, can improve the demonstration response characteristic and the image quality of display device.
The 7th embodiment of data driver
Next, explanation is applied to the 7th embodiment of the data driver of above-mentioned display device.
Although the above-mentioned data driver in the 6th embodiment comprise with from display pixel in data driver anti-phase the corresponding circuit arrangement of current drain method of projected current write current, the present invention is not limited thereto.It can be equipped with the circuit arrangement that the electric current applying method is provided, thereby makes the write current will be from data driver the direction of display pixel flow (pouring in).
The data driver relevant with this embodiment disposes the circuit arrangement of electric current applying method.
Figure 34 shows the electric wiring plan of configuration of the 7th embodiment of the data driver in display device related to the present invention.
Here, about any equivalent in the foregoing description, adopt identical or equivalent term and from describe, simplify or omit explanation it.
As shown in figure 34, briefly, the data driver 130G relevant with this embodiment has following configuration, comprising: shift-register circuit 131D or circuit bank 300B, write current produce circuit group 137B and current generator IR.Shift-register circuit 131D has the configuration that is equivalent to data driver 130E shown in Figure 30; Or circuit 300B comprise the electric current supply lines Ls that links to each other with current generator IR or circuit 301,302,303 ..., and apply the pressure-wire of given voltage Vr (resetting voltage) by it; And to produce by the write current that is used to produce write current Ipix current polarity circuit PXB1, PXB2, PXB3 ... (for convenience, after this being called as write current and producing circuit PXB) write current that constitutes produces circuit group 137B and is provided with, thus make it from the direction mobile (pour in) of display board 110D side by the data driver 130B of each signal wire DL.
Here, each write current produce circuit PXB1, PXB2, PXB3 ... have write current among the 4th embodiment that comprises with data driver shown in Figure 25 and produce the configuration of circuit I Sx equivalence, comprise that signal latch part, current generation section are divided and designated state is provided with part.
Pixel-driving circuit
Subsequently explanation is applied to the configuration of pixel-driving circuit of each display pixel of the display board 110D relevant with this embodiment.
Figure 35 shows the electric wiring plan with the display device another ios dhcp sample configuration IOS DHCP, that can be applicable to this embodiment of the corresponding pixel-driving circuit of circuitry consumes method.
The pixel-driving circuit here only shows an example that can be applicable to display device of the present invention.Needless to say, can there be other circuit arrangement with equivalent operation function.
As shown in figure 35, for example, the pixel-driving circuit DCy relevant with this embodiment comprises N channel transistor Tr101, N channel transistor Tr102, N channel transistor Tr103 and capacitor Cy.N channel transistor Tr101 links to each other with contact Nya by drain terminal respectively, is connected to pressure-wire VL with sweep trace SL parallel arranged by source terminal, and links to each other by near the sweep trace SL the point of crossing of gate terminal and sweep trace SL and signal wire DL.N channel transistor Tr102 links to each other with contact Nyb with signal wire DL respectively with drain terminal by source terminal, and links to each other with sweep trace SL by gate terminal.N channel transistor Tr103 links to each other with contact Nyb with pressure-wire VL respectively with drain terminal by source terminal, and links to each other with contact Nya by gate terminal.Capacitor Cy is connected between contact Nya and the contact Nyb.
In addition, produce drive current by the light that provides from pixel-driving circuit DCy and control the organic EL device OEL that produces luminosity at light.Organic EL device OEL anode terminal links to each other with the contact Nyb of above-mentioned pixel-driving circuit Dcy, and cathode terminal links to each other with low supply voltage Vgnd (ground voltage) respectively.Here, capacitor can be the stray capacitance that forms between the gate-source of N channel transistor Tr103, and except stray capacitance, capacitive element (capacitor) can be attached between the gate-source discretely.
Here, as shown in figure 34, pressure-wire VL and sweep trace SL are arranged concurrently, and link to each other with an end that is connected to voltage driver 140 jointly accordingly with the display pixel EM of each line.
The drive controlling method
Drive controlling method in having the data driver 130B of such configuration is identical with drive controlling method (with reference to Figure 32) among the 6th embodiment of above-mentioned data driver.At first, in the reset operation before signal keeps operation and electric current generation powered operation, by applying reseting controling signal, by be provided with predetermined low-potential voltage state, each write current produce circuit PXB1, PXB2, PXB3 ... in the designated state that forms part is set, with given voltage Vr (resetting voltage) be applied to simultaneously each signal line DL1, DL2, DL3 ...
Subsequently, keep in the operation at signal, according to the shift signal SR1, the SR2 that export in proper order from shift-register circuit 131D, SR3 ..., will by each bar line (display pixel EM) from each write current produce circuit PXB1, PXB2, PXB3 ... data latching part in the noninverting output signal of the video data d0-d3 that receives of order output to during each current generation section divides.
In addition, produce in the powered operation at electric current, according to the above-mentioned noninverting output signal of dividing from current generation section, from each display pixel EM via each signal line DL1, DL2, DL3 ... optionally gather a plurality of grading currents to produce the write current Ipix of negative polarity, and it sequentially is provided, thereby can on the direction of data driver 130F, draws write current Ipix.
In the write operation cycle, when the sweep signal Vsel that will select level (high level) was applied to sweep trace SL, the operation of the drive controlling of the organic EL device OEL in having the pixel-driving circuit DCy of such structure was applied to pressure-wire VL with low level supply voltage Vsc at first.In addition, regularly synchronous with this, write current Ipix is provided to signal wire DL from data driver 130F.Here, be set to provide the write current Ipix of the electric current of negative polarity, thereby will drawing suitable electric current via the direction of the data driver 130B of signal wire DL from display pixel EM (pixel-driving circuit Dcy) side.Therefore, carry out " conducting " operation at N channel transistor Tr101 that constitutes pixel-driving circuit Dcy and Tr102, and when low level supply voltage Vsc is offered contact Nya, in the operation of write current Ipix, by drawing, via N channel transistor Tr102, the low supply voltage level is applied to contact Nyb, but not the low level of supply voltage Vsc.
According to this mode, when between contact Nya and Nyb (between the gate-source of N channel transistor Tr103) when the voltage potential difference occurring, N channel transistor Tr103 carries out " conducting " operation, and makes with the corresponding electric current of write current Ipix and flowing through via the direction of the signal wire DL of N channel transistor Tr103, contact Nyb and N channel transistor Tr102 from pressure-wire VL.
At this moment, the corresponding capacitor Cy of the potential difference (PD) electric charge that is produced between accumulation and contact Nya and the Nyb, and remain component of voltage (condenser charge).In addition, in this.Owing to be applied to the power supply (ground voltage) that the power supply of the anode terminal (contact Nxb) of organic EL device OEL becomes and is lower than cathode terminal, and the bias voltage that will reverse is applied to organic EL device OEL, therefore light produces drive current and can not flow into organic EL device OEL, and does not carry out light generation operation.
Subsequently, in light produces the operating cycle, when the non-selected level (low level) with sweep signal Vsel is applied to sweep trace SL, the high level of supply voltage Vsc is applied to pressure-wire VL.Regularly synchronous with this, suspend drawing in the operation of write current Ipix.
Because in N channel transistor Tr101 and Tr102 execution " disconnection " operation, interrupted (disconnection) and in the operation of write current Ipix, drawn caused voltage level applying to contact Nyb, therefore, correspondingly interrupted voltage voltage Vsc applying to contact Nya.Then, capacitor Cy remains on stored charge in the above-mentioned write operation.
According to this mode, when capacitor Cx keeps charging voltage during in write operation that the voltage potential of (between the gate-source of N channel transistor Tr103) between holding contact Nya and the Nyb is poor, and N channel transistor Tr103 will remain " conducting " state.In addition, be applied to pressure-wire VL owing to will have the power supply supply voltage of the voltage level that is higher than ground voltage, so light generation drive current is being introduced organic EL device OEL from pressure-wire VL via the direction of the forward bias of N channel transistor Tr103 and contact Nyb.
Here, because the potential difference (PD) when flowing into N channel transistor Tr103 with the corresponding electric current of write current Ipix when the potential difference (PD) (charging voltage) that kept is equivalent in above-mentioned write operation in capacitor Cy, the light generation drive current that flows into organic EL device OEL will have the current value that equals above-mentioned electric current.Organic EL device OEL basis and the corresponding component of voltage of the grading current that writes in the write operation cycle continue operation so that luminous with required levels of luminosity during light produces the operating cycle.
In addition, be similar to a series of drive controlling operations of use scanner driver 120A, voltage driver 140 and data driver 130F shown in Figure 33, repeat these operations in proper order by each line to the display pixel group that constitutes display board 110B, write video data at a screen, each display pixel EM is luminous with the predetermined brightness grade, and shows required image information.
Therefore, in addition,,, the electric charge that is accumulated in the capacitor element that appends to signal wire DL or display pixel EM is discharged fully by reset operation as what in the display device that is applied to the data driver 130F relevant, set up with this embodiment.Afterwards, it carries out initialization in predetermined low power supply status, and can produce each grading current that offers display board (display pixel), and the video data that is constituted according to reference current and digital signal by constant current value provides it.Simultaneously, it can be controlled by the charging that appends to the capacitor element on signal wire, the reference current supply lines etc. and any reduction of the caused data driver operating speed of discharge operation, and improves the demonstration response characteristic.Can produce the grading current that has according to from the suitable current value of the video data of the grading current feed circuit that form respectively accordingly with each signal line, can provide each display pixel, and the grade that can realize ideal show.
The 8th embodiment of data driver
Subsequently, explanation is applied to the 8th embodiment of the data driver of the display device relevant with this embodiment.
The data driver of being correlated with this embodiment is identical with the 5th embodiment of above-mentioned data driver, produces circuit by two groups of write currents that form and constitute in each signal line.Each group write current produces that circuit is carried out the generation of the reception of video data and maintenance, write current and according to regularly complementary of scheduled operation and powered operation continuously.Each write current produces circuit and comprises that the write current among the 6th embodiment with data driver produces the identical configuration of circuit.At video data, given voltage (resetting voltage) can be offered signal wire, as designated value.Here, in this embodiment, the composition data driver, thus each that the write current that is produced in two groups produces circuit group the negative reference current with steady state value from single current generator can be offered.
Figure 36 shows the electric wiring plan of configuration of the 8th embodiment of the data driver in the display device relevant with the present invention.
Here, about any equivalent in the foregoing description, adopt identical or equivalent term and from describe, simplify or omit explanation it.
As shown in figure 36, the data driver 130G relevant with this embodiment has following configuration, comprises the configuration identical with the 5th embodiment of above-mentioned data driver.Particularly, data driver 130G comprises anti-phase latch cicuit 133C, shift-register circuit 134C or circuit bank 300C, selects to be provided with circuit 136C and current generator IR.Anti-phase latch cicuit 133C produces noninverting clock signal C Ka and inversion clock signal CKb according to the shift clock signal SFC that provides from system controller 150; Shift-register circuit 134C when displacement enabling signal STR being shifted according to noninverting clock signal C Ka and inversion clock signal CKb, predetermined timing place sequentially export shift signal SR1, SR2, SR3, Circuit bank 300C by or circuit 301,302,303 ... constitute, export publicly from each shift signal SR1, SR2, SR3 ... (after this, for convenience, be described as shift signal SR) and the exclusive disjunction result of the reseting controling signal RST that provides of system controller 150, as going to the timing controling signal CLK that the write current of describing after a while produces circuit group 138C and 138D.Two groups of write currents produce circuit group 138C and 138D according to from each or circuit 301,302,303 ... the timing controling signal of middle output, sequentially receive the video data d0-d3 that from shows signal generation circuit 160, sequentially provides in cycle at each line, light among generation and each display pixel EM produces the corresponding write current Ipix of luminosity, then, via each signal line DL1, DL2, DL3 ... provide (applying) its; Selection is provided with circuit 136C according to the switch-over control signal SEL that provides as data controlling signal from system controller 150, produce and select set-point signal (noninverting signal SLa and the inversion signal SLb of switch-over control signal SEL), so that optionally above-mentioned write current produces among circuit group 138C and the 138D any; And current generator IR (providing and draw the electric current of negative polarity) via constitute each write current that write current produces circuit group 138C and 138D produce circuit PXC1, PXC2, PXC3 ... with PXD1, PXD2, PXD3 ... (after this, for convenience, be called as write current and produce circuit PXC and PXD) and common reference electric current supply lines Ls, constant reference current Iref is provided.
Here, anti-phase latch cicuit 133C, shift-register circuit 134C and selection are provided with each configuration, shift-register circuit 134B and selection of all disposing the anti-phase latch cicuit 133B of the 5th embodiment that equals data driver of circuit 136C circuit 136B are set.
In addition, the write current that each write current feed circuit PXC and PXD have among the 5th embodiment that comprises the data driver that equals shown in Figure 29 produces the configuration of the structure of circuit I Sy, and is equipped with signal latch part 10y, current generation section to divide 20y and designated state that part 40y is set.
Produce among circuit PXC and the PXD at write current, as the reversed-phase output signal d10 of basis from data latching part 10y output with such configuration *-d13 *, when selecting the selection set-point signal of level, divide the write current Ipix that produces among the 20y according to video data d0-d3 in current generation section from selecting to be provided with input the circuit 136C.As a result, the display pixel EM via signal wire DL and write current generation circuit PXC or PXD power supply is set to selection mode.
On the contrary, when when selecting to be provided with circuit 136C and import the selection set-point signal of non-selected level, although receive video data d0-d3 and remain among the data latching part 10y and do not produce write current Ipix, but will power to signal wire DL, and write current produces circuit PXC or PXD is set to non-selected state.
Particularly, selection is provided with circuit 136C and is input to the selection set-point signal (the not inversion signal SLa of switch-over control signal SEL or inversion signal SLb) that two groups of write currents produce circuit group 138C and 138D by suitably being provided with, can two groups write current produce among circuit group 138C and the 138D any be set to selection mode, and can be set to non-selected state by opposite side.
The drive controlling method
Next will explain the operation of display device with reference to the accompanying drawings with above-mentioned configuration.
Figure 37 shows the sequential chart of example of the drive controlling operation of data driver in this embodiment.
In the drive controlling operation of data driver 130G, at first, two groups of write currents that are set to non-selected state in a side produce in the circuit group, signal keeps operating in these write currents and produces that formed each write current produces in circuit (data latching part) in circuit groups, receives also to keep and the corresponding video data d0-d3 of each display pixel EM.Reset operation produces circuit (designated state is provided with part) via each write current the designated state that each write current produces circuit group is set, and given voltage Vr (resetting voltage) is applied to each signal wire DL simultaneously, and stored charge is discharged.The electric current powered operation produces the corresponding write current Ipix of video data d0-d3 that is kept in circuit (current generation section branch) generation and the above-mentioned signal maintenance operation by each write current, offers each display pixel EM in proper order to carry out setting via each signal line DL.In addition, in two groups of write currents generation circuit groups, carry out so a series of setting operations continuously and alternately.
In the drive controlling operation of as shown in figure 37 data driver 130G, at first, provide switch-over control signal SEL from system controller 150.Keep in the operation at signal, circuit 136C is being set according to the shift signal SR1 that exports in proper order from shift-register circuit 134C by selection, SR2, SR3, write current (is for example produced one of circuit group, write current produces circuit group 138C) be set to after the non-selected state, order receives video data d0-d3, with each line (promptly, each signal line DL1, DL2, DL3,) display pixel EM transfer to accordingly and constitute each write current that write current produces circuit group 138C and produce circuit PXC1, PXC2, PXC3,, and in the realization maintenance operation continuously in the cycle of a line.
Subsequently, selecting to be provided with circuit 136C by providing from system controller 150 reset operation of switch-over control signal SEL after selection mode is set, by each write current that produces circuit group 138C at write current produce circuit PXC1, PXC2, PXC3 ... in reseting controling signal RST is provided, receive simultaneously and the corresponding video data d0-d3 of designated state (being equivalent to the blank screen show state).Therefore, with given voltage Vr (resetting voltage) from each write current produce circuit PXC1, PXC2, PXC3 ... be applied to each signal line DL simultaneously, and to append to each signal line DL1, DL2, DL3 ... discharge with the electric charge that is accumulated in the capacitive element of display pixel EM.
Subsequently, produce according to each write current circuit PXC1, PXC2, PXC3 ... the electric current of the video data d0-d3 that the above-mentioned signal of (data latching part) is kept in keeping operating produces in the powered operation, by optionally gathering a plurality of grading currents that are set to have different current ratio, the write current Ipix of the levels of luminosity of each display pixel EM has been specified in generation, and by each signal wire DL1, DL2, DL3 ... it sequentially is provided.
In addition, as shown in figure 37, between two groups of write currents generation circuit group 138C and 138D, alternately carry out such sequence of operations.That is, carry out wherein receive video data and another write current produce circuit 138D be set to selection cycle the signal hold period in, write current produces one of circuit group 138C and is set to the non-selected cycle.After carrying out reset operation, according to utilizing the previous video data that is regularly received, produce and provide grading current, and carry out parallel grading current powered operation.Subsequently, when carrying out next reset operation, write current produces circuit group 138C and is set to selection cycle, and the electric current generation powered operation that another write current produces among the circuit group 138D is set to the non-selected cycle.When carrying out signal maintenance operation, receive this video data.Repeat at write current with alternating sequence and to produce conversion back and forth between the circuit.
Therefore, also be set to be applied to the display device of the data driver 130G relevant, the electric charge that runs up to from reset operation in the capacitive element that appends to signal wire DL or display pixel EM is discharged fully with this embodiment.For this reason, its initialization is at predetermined low power supply status, and afterwards, the video data that can constitute according to reference current and the digital signal by constant current value produces and provide each grading current that will offer display board (display pixel EM).Simultaneously, it can be controlled by the charging that appends to the capacitive element on signal wire, the reference current supply lines etc. and any reduction of the caused data driver operating speed of discharge operation, and improves the demonstration response characteristic.Can produce according to grading current, can offer each display pixel EM, and the grade of can realizing ideal show from the suitable current value of the video data of the grading current feed circuit that form respectively accordingly with each signal line.
In addition, alternately repeat the mode of operation of each write current generation circuit and each signal line is carried out this operation by making two groups of write currents produce circuit (group), and consider that grading current has with the suitably corresponding current value of video data and it can be offered continuously the fact of each display pixel from data driver, the light that can carry out the display pixel of predetermined levels of luminosity apace produces operation, and can further improve demonstration response speed and image quality.
And, in each embodiment of above-mentioned data driver, although data driver has following configuration: in data driver, providing reference current in formed a plurality of write currents generation circuit, provide reference current jointly from single current generator, but the present invention is not limited thereto.It can have constant current source at each data driver.In addition, each grading current that produces circuit at a plurality of grading currents of formed predetermined quantity in single data driver produces circuit, and it can have constant current source.
Next, as the 6th to the 8th above-mentioned embodiment, according to video data grading current is being write display pixel (stray capacitance) before, or by with remaining charge discharge (reset operation) in the capacitive element retention volume of display pixel etc. to predetermined low supply voltage, for the capacitance wiring that appends on signal wire etc., make the configuration of data driver realize following structure: in grading current write operation to display pixel, according to video data, shorten and stablize the required time of proper signal level.
Yet the present invention is not limited to these configurations, and can achieve following technological concept: reset operation is carried out in the configuration according to the pixel-driving circuit that forms each display pixel.After this, will be to its detailed explanation.
Other examples of the configuration of pixel-driving circuit
Figure 38 shows the electric wiring plan as another ios dhcp sample configuration IOS DHCP of the display pixel that can be applicable to display device related to the present invention.
Figure 39 shows the electric wiring plan of another ios dhcp sample configuration IOS DHCP of the display pixel that can be applicable to display device related to the present invention.
Although be suitable for being applied to display device related to the present invention, the configuration of display pixel has in this embodiment adopted above-mentioned first and the data driver of the 5th embodiment, this data driver side also not only is confined to these configurations, and can be equipped with other additional configurations.
In addition, Figure 21 shows the configuration among Figure 38-39, although consider and the basic structure of the corresponding pixel-driving circuit configuration of electric current applying method, added reset mechanism based on above-mentioned technological concept, the basic configuration of pixel-driving circuit is not limited thereto.Comprise that above-mentioned write operation and light produce the sequence of operations step of operation and comprises that being used for light produces the luminescent device of operating as long as this circuit has, can use other circuit arrangement, for example, pixel-driving circuit shown in Figure 16.
As shown in figure 38, the crystal nest of tubes of relevant with this example arrangement pixel-driving circuit DCxa at display pixel EM has the circuit arrangement identical with pixel-driving circuit DCy shown in Figure 21, as mentioned above, it comprises p channel transistor Tr81 and Tr83 and N channel transistor Tr82 and Tr84, and capacitor Cy.The example of this pixel-driving circuit DCxa also comprises N channel transistor Tr85.Except retention volume (capacitor Cx in this example) and organic EL device OEL (optical element), by control terminal (gate terminal) with N channel transistor Tr85 (discharge circuit) with link to each other with the parallel reset line RL that is provided with of sweep trace SL, and in current path (source drain terminal), be connected between contact Nxc and the low supply voltage Vgnd.
In addition, as shown in figure 38, although shown in the configuration N channel transistor Tr85 that will have a reset function be connected between contact Nxc and the low supply voltage Vgnd, the present invention is not limited thereto.As shown in figure 39, can dispose pixel-driving circuit DCxb with the N channel transistor Tr85 that is connected between contact Nxa and the low supply voltage Vgnd.
In addition, in pixel-driving circuit DCxa shown in Figure 38 to 39 and DCxb, although Tr82 is made of the N channel transistor and has the circuit arrangement that control terminal links to each other with sweep trace SL, the operating function in this pixel-driving circuit equates with the operating function of pixel-driving circuit shown in Figure 21.
In such configuration, by applying high level reseting controling signal RST to reset line RL from system controller 150, between the earth potential or pixel-driving circuit DCxb contact Nxa that are connected electrically in pixel-driving circuit DCxa contact Nxc, N channel transistor Tr85 carries out " conducting " operation.Accumulation (maintenance) electric charge in the retention volume (capacitor Cx) of each pixel-driving circuit DCxa that discharges via N channel transistor Tr85 above earth potential and DCxb, and the reset operation of execution display pixel EM.
The drive controlling method
Figure 40 shows the sequential chart of an example of the drive controlling operation in the display device relevant with this embodiment.
Here, the data driver that explanation is had the configuration of first embodiment shown in Figure 17.
By sequentially setting up the following drive controlling operation of carrying out in the display device relevant of operating with this embodiment, described being operating as: at first, before the powered operation of the write current of data driver 130A, to the reset operation that the electric charge that accumulates in the capacitive element that appends to each display pixel EM discharges, carry out the drive controlling operation in the display device relevant with this embodiment; Receive and keep from shows signal produce each write current that circuit 160 offers data driver produce circuit I LA1, ILA2, ILA3 ... the signal of video data keep operation; And the electric current that produces write current Ipix and offer each signal wire DL according to the video data that kept produces powered operation.
As shown in figure 40, the drive controlling in the display device relevant with this embodiment is operated initial advanced horizontal reset operation, this function according to provide via signal wire DL, produce write current from the video data of data driver 130A.By reset line RL, high level reseting controling signal RST is offered the display pixel group line that is set to selection mode from system controller 150, so that write above-mentioned grading current.Simultaneously, formed N channel transistor Tr85 carries out " conducting " operation in each display pixel EM, and the appointment contact Nxc of pixel-driving circuit DCxa and DCxb is linked to each other with earth potential with Nxa.Therefore, electric charge accumulation for the retention volume in the formed capacitive element (capacitor Cx) among pixel-driving circuit DCxa and the DCxb etc., then, is discharged to earth potential.Current potential to each above-mentioned contact Nxc and Nxa in predetermined low level potential state (resetting) carries out initialization.
Subsequently, in the signal identical with above-mentioned each embodiment kept operating, this sequence of operation received and also remains on the video data of carrying out continuously in the line cycle, and in electric current generation powered operation video data was set.All be set to a plurality of grading currents by optionally gathering each, produce write current Ipix, offer display pixel EM in proper order via each signal wire DL based on the current value of the different ratios of the video data of above-mentioned maintenance.
Produce in the operation in subsequent optical, each display pixel EM is by providing light to produce drive current according to the component of voltage that is kept continuously to organic EL device OEL, and is luminous with the luminous grade corresponding to video data.Write write current Ipix simultaneously, and offer each signal wire DL from data driver 130A concurrently, and remain the component of voltage among the capacitor Cx.By being applied to the display pixel group from scanner driver 120A, the electric charge that is accumulated in the capacitive element from above-mentioned reset operation is discharged at the sweep signal of the selection level of sweep trace SL.
Therefore, since can be under predetermined low-potential state to carrying out initialization with the display device that is applied to the display board relevant (display pixel EM) with this embodiment, can to from reset operation, append to the electric charge that is accumulated in the capacitive element on the display pixel EM and carry out ideal and discharge.In addition, can also be according to based on the grading current that video data produced, the electric charge of the appropriate amount that setting will accumulate, and the light that offers organic EL device OEL produces drive current and is set to suitable current value.As a result, simultaneously, can control reduction, and improve and show response characteristic by the caused writing speed to display board of the charging that appends to the capacitive element on the display pixel EM and discharge operation.In addition, can produce operation according to the light that video data is carried out each display pixel EM (organic EL device) with suitable levels of luminosity.
As mentioning in this embodiment, because this configuration is included in the reset mechanism (N channel transistor Tr85 and reset line RL) of stored charge being discharged to before the grading current write operation of display pixel EM (pixel-driving circuit), therefore, reset mechanism in can the omitted data driver (for example, formed designated state is provided with part and or circuit bank in each write current generation circuit shown in Figure 30), circuit arrangement can be simplified, and the miniaturization of display device can be realized.
In addition, thereby below only show when be provided with current polarity make light produce drive current when the direction from the light-emitting component (organic EL device) of the pixel-driving circuit that forms display pixel flows, with the relevant display device of above-mentioned each embodiment, still the present invention is not limited thereto.Can construct the present invention, thereby simultaneously high-potential voltage be linked to each other with the opposite side of luminescent device, make light produce drive current direction at pixel-driving circuit from light-emitting component and flow through by the input/output terminal of anti-phase connection luminescent device.
Second embodiment of display device
Next, in current generating circuit related to the present invention, will explain with reference to the accompanying drawings about in display device, being applied in the embodiment of the pixel-driving circuit that forms in each display pixel that constitutes display board.
Figure 41 shows the profile block scheme of an ios dhcp sample configuration IOS DHCP of second embodiment of display device related to the present invention.
Figure 42 shows the electric wiring plan of an embodiment of the pixel-driving circuit that is applied to the display device among this embodiment.
Figure 43 shows the electric wiring plan of an embodiment of the data driver that is applied to the display device among this embodiment.
Here, about any equivalent in the foregoing description, adopt identical or equivalent term and from describe, simplify or omit explanation it.
As shown in figure 41, briefly, the display device 100C that is correlated with this embodiment comprises the configuration identical with first embodiment of display device shown in Figure 13.Although this configuration comprises display board 110E, scanner driver 120C, data driver 130H, system controller 150 (not shown) and shows signal and produces circuit 160 (not shown) that the pixel-driving circuit DCz in each the display pixel EP that forms display board 110E has different configurations as follows with corresponding data driver 130H.
Particularly, as shown in figure 41, the display board 110E that is applied to this embodiment has following configuration, comprising: a plurality of sweep trace SL, two or more sets signal line group DLz, a plurality of display pixel EP and current generator IR.Especially, this configuration comprises a plurality of a plurality of sweep trace SL that are arranged in parallel, is arranged as a plurality of a group two groups and the current generator IR that organize signal line group DLz (being four in this embodiment) more, be arranged near the intersection point of sweep trace SL and signal line group DLz a plurality of display pixel EP (in Figure 41, this configuration by after a while with pixel-driving circuit DCz and organic EL device OEL (optical element) formation described) and the reference current with constant current value is provided regularly that meet at right angles and intersect with sweep trace SL respectively in display pixel EP.
Here, as shown in figure 41, pixel-driving circuit DCz configuration comprises that light produces driver and organic EL device OEL (optical element).Light produces driver according to being applied to the sweep signal Vsel of each display pixel EP and the level data DP0-DPk (digital signal that provides via signal line group DLz from data driver 130H from scanner driver 120C via sweep trace, in this embodiment, k=3), produce light and produce drive current; And organic EL device OEL (optical element) is according to the current value of the light generation drive current that is provided by pixel-driving circuit DCz, and the light of carrying out predetermined levels of luminosity produces operation.
Pixel-driving circuit
Will be in each embodiment of above-mentioned current generating circuit formed configuration be applied to pixel-driving circuit DCz among this embodiment shown in Figure 42, (for example comprise signal latch part 10z, be equivalent to the signal latch part 10 among Fig. 1) and current generation section divide 20z (for example, the current generation section that is equivalent among Fig. 1 is divided 20A).Signal latch part 10z basis applies regularly from the institute of the sweep signal Vsel of scanner driver 120C, receives and the corresponding output signal of suitable level data DP0-DP3 that comprises level data DP0-DP3 that provides via each signal line group DLz from data driver 130H in one-period separately and simultaneously; And with the corresponding predetermined period of suitable level data DP0-DP3 in, the output that keeps holding signal d10-d13.Current generation section divides the 20z set from a plurality of grading currents that produced based on the reference current Iref that offers each display pixel EP via reference current supply lines Ls, according to the selected given level electric current of above-mentioned holding signal d10-d13; And the corresponding light of the levels of luminosity among generation and each display pixel EP produces drive current, provides it to organic EL device OEL (optical element).In addition, the configuration of pixel-driving circuit DCz equals current generating circuit (with reference to figure 1) related to the present invention.Here, electric current latchs part 10z and has following configuration, comprising: with the configuration of corresponding a plurality of (four groups) latch cicuits of each level data DP0-DP3 and signal latch part 10 shown in Figure 1.In addition, the cathode terminal of organic EL device OEL divides the electric current output contact OUTi of 20z to link to each other with current generation section, and anode terminal links to each other with the voltage contact+V that is connected to predetermined high-potential voltage.
At first, for the drive controlling operation of the organic EL device OEL among the pixel-driving circuit DCz with such configuration, applying high level (selection level) sweep signal Vsel to sweep trace SL when, this operation is regularly synchronous with this.Then, will offer signal line-group DLz by the level data DP0-DP3 that constitutes with the corresponding a plurality of digital signal bits of video data d0-d3 that produce circuit 160 and provide from shows signal by data driver 130H (described after a while).
Therefore, receive level data DP0-DP3 separately and simultaneously, so that hold it in each signal input IN0-IN3 place, contact of the signal latch part 10z of a part that forms pixel-driving circuit DCz.To output to current generation section based on the holding signal d10-d13 of each level data DP0-DP3 and divide 20z.
For example, the light that divides the identical current generation section of 20A to divide 20z to provide institute to obtain and gather with the current generation section among first embodiment of above-mentioned current generating circuit produces a drive current, only selects the grading current of appointment then from a plurality of grading currents of current value with predetermined ratio.Then, according to the signal level of going to the above-mentioned holding signal d10-d13 of organic EL device OEL by electric current output contact OUTi, produce the given level electric current (in this embodiment based on reference current Iref, make light produce drive current and flow through, thereby draw it) in direction from the pixel-driving circuit DCz of organic EL device OEL.
Therefore, the direction of setovering with forward direction according to the light generation drive current of video data d0-d3 (level data DP0-DP3) flows into organic EL device OEL, and organic EL device OEL is luminous with predetermined levels of luminosity.
Data driver
For data driver 130H, for example, shift register 131E has the configuration that is equivalent to embodiment as shown in figure 43.Especially, this configuration comprises latch cicuit 140, output circuit 141, system controller 150 (not shown) and signal generating circuit 160 (not shown).Latch cicuit 140 comprise a plurality of latch partial L D1, LD2, LD3 ... receive separately and sequentially from shows signal and produce a plurality of video data d0-d3 bits that circuit 160 (not shown) provide, and according to from shift signal SR1, the SR2 of shift register 131E, SR3 ... keep it; And output circuit 141 comprises a plurality of switch SW 1, SW2, SW3, carry out following operation: according to the output enable signal WE that from system controller 150 (not shown), exports, concentrate to above-mentioned each display pixel EP via each signal line-group DLz to be provided at a line and to remain on video data d0-d3 in the latch cicuit 140 in the cycle, as level data DP0-DP3.
The drive controlling method
Next will explain the operation of display device with reference to the accompanying drawings with said structure.
Figure 44 shows the sequential chart of an example of the drive controlling operation in the display device of this embodiment.
Figure 45 shows the electric wiring plan of another embodiment of the pixel-driving circuit that is applied to the display device among this embodiment.
At first, as shown in figure 44, drive controlling operation in data driver 130H is set up video data and is kept operation, order receive from shows signal produce circuit 160 offer each that form above-mentioned latch cicuit 140 latch partial L D1, LD2, LD3 ... video data d0-d3, and keep this video data; And level data provides each switch SW 1, SW2, the SW3 of operation via output circuit 141 ..., concentrate to each signal line group DLz the video data d0-d3 that keeps operation to be received by showing be provided.
Here, video data keep sequence of operation ground receive each above-mentioned shift signal SR1 according to order output from shift-register circuit 131E, SR2, SR3 ..., respond each above-mentioned latch partial L D1, LD2, LD3 ... in the display pixel EP displacement of each line after video data d0-d3, and carry out continuously in the cycle at a line and to keep operation.
In addition, provide in the operation in level data, output enable signal WE according to output from system controller 150, by use as level data DP0-DP3 remain on each above-mentioned latch partial L D1, LD2, LD3 ... the video data d0-d3 at place, via each switch SW 1, SW2, SW3 ... concentrate and offer signal line group DLz.Here, the level data that is provided with among the display board 110E provides operation, so as with the applying regularly synchronously of the sweep trace Vsel of the display pixel EP that is used to select specified line.Therefore, in this embodiment, will offer direct display pixel (pixel-driving circuit DCz) from data driver 130E via each the bars line-group DLz that among display board 110E, arranges based on the level data DP0-DP3 (digital signal) of the video data d0-d3 that constitutes by a plurality of digital signal bits.
As shown in figure 44, in the drive controlling operation in display board 110E (display pixel EP), by sweep signal Vsel is applied to the sweep trace SL of specified line (i is capable) from scanner driver 120C, reception provides operation to offer the level data DP0-DP3 of each signal line-group DLz from data driver 130H by above-mentioned level data, and remain among each display pixel EP (pixel-driving circuit DCz) among the formed signal latch part 10z, and will output to current generation section based on the holding signal DP10-DP13 of level data DP0-DP3 and divide 20z.
And as mentioned above, according to reference current Iref and holding signal DP10-DP13, current generation section divides 20z to produce light generation drive current according to video data d0-d3 (level data DP0-DP3), and this electric current is offered organic EL device OEL.Therefore, organic EL device OEL is luminous with predetermined levels of luminosity.
In addition, as shown in figure 41, the display board 110E that will be correlated with this embodiment (pixel-driving circuit DCz) is set to the identical environment shown in each embodiment, has following configuration: a plurality of display pixel EP (pixel-driving circuit DCz) with link to each other with the common reference electric current supply lines Lz of reference current Iref power supply from as shown in figure 44 current generator IR.Owing to selecting each synchronous pixel-driving circuit DCz of timing of the display pixel EP of specified line with sweep trace Vsel being used for of applying, the light that produces simultaneously each organic EL device OEL according to level data DP0-DP3 produces drive current, and the electric current that offers the display pixel EP (pixel-driving circuit DCz) of each line by reference current supply lines Ls is not the reference current Iref self that provides from current generator IR.The quantity (for example, m line) that this electric current will have a display pixel EP (pixel-driving circuit DCz) according to each line is to its almost five equilibrium and the current value (Iref/m) that provides.
Each line that forms display board 110E being carried out the order of a series of above-mentioned drive controlling operations carries out.In addition, keep the light of the organic EL device OEL of each line to produce operation (light produces the powered operation of drive current) continuously by pixel-driving circuit DCz, till applying next sweep signal Vsel.
Therefore, be set to the display device 100C relevant with this embodiment, from data driver 130H via each the signal line group DLz that among display board 110E, is arranged, to directly offer display pixel EP (pixel-driving circuit) by the level data DP0-DP3 that constitutes with the corresponding a plurality of digital signal bits of video data d0-d3, and be set to pixel-driving circuit.Owing to light produces drive current by the simulating signal formation that produces based on the reference current Iref that provides via common reference electric current supply lines Ls from current generator IR (electric current that is made of the reference current Iref that produces the correlated measure five equilibrium of circuit with write current), with wherein provide write current that constitutes display pixel EP and the configuration of in conventional art, often using to compare according to analog current, can improve the effect of signal level reduction, external noise etc. significantly, to offset these negative effects.As direct result of the present invention, can improve signal noise (S/N) ratio, can also produce operation with light, and can realize the raising of image quality with the corresponding suitable levels of luminosity realization organic EL device of video data (light-emitting component).
Except the foregoing description and situation, about with display pixel in light produce the relevant signal wire of operation, because the configuration that it does not make the simulating signal of change signal level flow through, this has alleviated the restriction to the charging of signal wire and the caused operating speed of discharge operation, and the demonstration response characteristic that has improved the display device that comprises data driver is to realize significant image quality.
In the foregoing description relevant with display pixel EP, no matter make the light that is produced by pixel-driving circuit DCz produce the fact that drive current flows through in the direction of drawing from organic EL device OEL side with the corresponding configuration of current drain method, the present invention is not limited to be applied to shown in above-mentioned Fig. 4 to 5 and configuration shown in Figure 45.Therefore, can also use and the corresponding configuration of electric current applying method, wherein provide the light that is produced by pixel-driving circuit DCz to produce electric current, thereby make its direction flow through (pouring in) at the organic EL device OEL that divides 20z from current generation section.And, in the configuration of the display device in the above-described embodiments (with reference to Figure 41), other ends of current generator (+V connects side) link to each other with low-potential voltage (ground voltage), and it is set, thereby can drawing this reference current Iref from the low-potential voltage direction of display board (display pixel EP) side.
Subsequently, another ios dhcp sample configuration IOS DHCP of the display device relevant with this embodiment will be explained.
As mentioned above, the configuration of first or second embodiment of above-mentioned current generating circuit is applied to pixel-driving circuit DCz or DCz ' and makes an explanation.Yet the present invention is not limited thereto, and at pixel-driving circuit DCz or DCz ', can be applied to the configuration among the 3rd or the 4th embodiment of above-mentioned current generating circuit, as other examples of this configuration.When video data constitutes designated value, this circuit can be equipped with organic EL device OEL (optical element), and it is configured so that given voltage Vbk (blank screen display voltage) or the given voltage Vr (resetting voltage) identical with the 4th to the 8th embodiment of above-mentioned data driver is provided.Figure 46 to 47 shows these example display devices and pixel-driving circuit configuration.
Figure 46 shows the profile block scheme of another ios dhcp sample configuration IOS DHCP in the display device of this embodiment.
Figure 47 shows the electric wiring plan of another embodiment of the pixel-driving circuit that is applied to the display device among this embodiment.
Particularly, compare with the configuration of above-mentioned display board 110E shown in Figure 41, for display board 110E ' shown in Figure 46, the outside provides given voltage (blank screen display voltage Vbk and resetting voltage Vr) and it is carried out wiring, so that given voltage is applied to each display pixel EPa.Each display pixel EPa comprises the configuration of the 3rd or the 4th embodiment of the above-mentioned current generating circuit that equals shown in Figure 47, has following circuit arrangement: have the pixel-driving circuit DCza that comprises at the input terminal Vin of given voltage Vbk or Vr.Under these situations of the 4th to the 8th embodiment of above-mentioned data driver, when video data was made of designated value, it provided, goes to the given voltage of organic EL device OEL (optical element) as blank screen display voltage Vbk or resetting voltage Vr.
In above-mentioned each embodiment that applies at 4 bit digital signal of video data, although the example under this situation carries out 2 4The display operation of=16 grades, needless to say, the present invention is not limited thereto, and can be applied to the image demonstration of more grades.
In addition, although explained the situation that current generating circuit related to the present invention is applied to the data driver or the pixel-driving circuit of the display device in the foregoing description, the present invention is not limited to such application example.For example, utilize many light-emitting components to arrange and form printhead.By the electric current with predetermined current value is provided, advantageously, the present invention also is applied to comprise according to the driving circuit of current value at the equipment of the multifunctional element of being scheduled to operate under the driving condition.
The configuration of field effect transistor
Below explanation be can be applicable to the configuration of Thin Film Transistor (TFT) of current generating circuit related to the present invention and the pixel-driving circuit that forms in the display board of display device.
Figure 48 A-48B shows the basic circuit of the N channel thin-film field effect transistor in the conventional arrangement and the figure of voltage-current characteristic.
Figure 49 A-49B shows the basic circuit of the P channel thin-film field effect transistor in the conventional arrangement and the figure of voltage-current characteristic.
For example, as Fig. 3, Fig. 5, Figure 16 and shown in Figure 21, each write current that forms the data driver (current generating circuit) among above-mentioned each embodiment or be set to the pixel-driving circuit (current generation section branch) that forms display board produces circuit and is set to following configuration: pixel-driving circuit is by N raceway groove (N channel-type) or P raceway groove (P channel-type) Thin Film Transistor (TFT) (also being referred to as FET), and is known as TFT when comprise the term film transistor) formation; And current mirror circuit is made of reference current transistor and grading current transistor.
Here, dotted line among Figure 48 B and the 49B shows ideally and is formed for the pixel mirror image circuit that light produce to drive or the film N channel transistor of pixel-driving circuit, and the voltage-current characteristic that shows the required film p channel transistor of the saturated inclination of the voltage Vds between the source drain that is made of the constant drain current in given voltage zone (saturation voltage district).Yet, shown in Figure 48 A and 49A, specialize in order to utilize basic circuit, and in fact shown in the continuous lines of Figure 48 B and 49B, in case drain current shows the saturated inclination that is caused by the foundation of the voltage Vds between the source drain, as shown in the figure, this tilts increases gradually.For example, this has considered the situation of speed in recent years, low-energy-consumption, high integrated etc. favourable improvement.By research and development, the field effect transistor etc. with semiconductor layer configuration of insulator (SOI) silicon-on is rapidly developed.By causing the collision ionization near the isolated area that electric field is concentrated therein, and as the result who flows into (pouring in), be accumulated in the channel region (being equivalent to body region) charge carrier that correspondingly produces (N raceway groove＞have electronics lacks or the n channel transistor and the P raceway groove＞P channel transistor electronics in hole), threshold voltage descends and drain current increases, and thinks that it is based on " being entangled with (kink) " phenomenon (being called as the parasitics that is called as " being entangled with " that is made of threshold voltage shift).
Therefore, according to increasing phenomenon, no longer need the desirable saturation characteristic (voltage-current characteristic) of drain current, and be arranged in the current mirror circuit by the caused drain current of such intertwinement.In current generating circuit,, need the current value ratio of grading current to reference current at required design load.That is, the foregoing description is not set to the ratio of transistorized channel width, and the write current when light produces operation and the current value of light emission drive current be different in transistor, to be used for light emitting drive.Therefore, can produce operation with the light of carrying out based on the suitable levels of luminosity of video data in each display pixel, and can cause the deterioration of image quality.
Afterwards, will be explained in the transistor that is used for optical drive among the pixel driver DCy.Therefore, also will make an explanation with reference to pixel-driving circuit DCy shown in Figure 21.
Figure 50 A-50B shows the contact between the voltage-current characteristic that is used for the transistor (p channel transistor) that light produce to drive, and the current value of the drain current (light generation drive current) that is provided with when write operation and light produce operation.Particularly, because in pixel-driving circuit DCy shown in Figure 21, by applying high level sweep signal Vsel to sweep trace SL when the above-mentioned write operation, p channel transistor Tr81 carries out " ending " operation and N channel transistor Tr82 and Tr84 and carries out " conducting " operation, therefore, make write current Ipix flow into organic EL device OEL via N channel transistor Tr82 and p channel transistor Tr83.At this moment because N channel transistor Tr84 is in " conducting " state, between the gate-source of p channel transistor Tr83 between the voltage Vgs and source drain of (between the Nya-Nyb of contact) the voltage Vds of (between the Nya-Nyc of contact) become identical.This moment, operating point on volt-ampere characteristic curve constituted the ACw in should the zone.For example, Figure 50 A shows saturation characteristic.
On the contrary, when light produces operation, because by applying low level sweep signal Vsel to sweep trace SL, p channel transistor Tr81 carries out " conducting " operation and N channel transistor Tr82 and Tr84 execution " ending " operation, and light produces drive current and flows into organic EL device OEL from the high-potential voltage that links to each other with voltage contact+V via p channel transistor Tr81 and Tr83.Because this moment, N channel transistor Tr84 was in " ending " state, the grid voltage of p channel transistor Tr83 (current potential of contact Nyb) will be in floating charge state (floating condition).For the voltage between the gate-source of p channel transistor Tr83, the current potential during write operation before sweep signal Vsel changes, and it is remained the electric charge that is accumulated in capacitor Cy when above-mentioned write operation.Therefore, shown in Figure 50 A and 50B, at this moment, the operating point on the volt-ampere characteristic curve becomes the ACh on the low-voltage direction (right side of Figure 50 B) that moves on in the zone of saturation, but not operating point ACw.Here, irrelevant according to the change in the zone of saturation from the magnitude of voltage (Vds) that operating point ACw is transformed between operating point ACh and the source drain, and flow through almost constant drain current (Ids).Ideally, when above-mentioned write operation, be provided with, will control the electric current (light generation drive current) that flows into organic EL device OEL by the current value of the electric current that is kept no better than (write current Ipix).
Yet, when its have that drain current (Ids) wherein increases gradually along with the voltage-current characteristic of the p channel transistor Tr83 shown in Figure 49 B and source drain between the absolute value of voltage (Vds) when increasing, the electric current (light generation drive current) that flows into organic EL device OEL set different value of electric current (write current Ipix) in the time of will becoming with write operation.Owing to this reason, can not be according to video data, the light of carrying out each display pixel with suitable levels of luminosity produces operation.
Then, in this embodiment, the kink phenomenon of mentioning in order to control as above, the thin film transistor (TFT) (TFT) with so-called at least body terminal arrangement has been used in configuration of the present invention, by it, the body region of SOI type field effect transistor and the reference current transistor in source region and the current generating circuit and grading current transistor and in pixel-driving circuit, be used for the transistor that light produce to drive and be electrically connected.
The body terminal arrangement
Here, P raceway groove (P channel-type) transistor that detailed description is had the body terminal arrangement.
Figure 51 A-51B shows the synoptic diagram of the surface level configuration of the P channel thin-film transistor with body terminal arrangement.
Figure 52 A-52D shows the synoptic diagram of the cross-sectional configuration of the P channel thin-film transistor with body terminal arrangement.
Here, Figure 51 A shows the planar structure of the active layer that forms on Semiconductor substrate, and Figure 51 B shows the wherein planar structure under the state that forms electrode on the active layer.In addition, Figure 52 A shows the configuration of the A-A cross-sectional surface of the configuration shown in Figure 51 B.Figure 52 B shows the configuration of the B-B cross-sectional surface of the configuration among Figure 51 B.Figure 52 C and 52D show p channel transistor with body terminal arrangement and the circuit of N channel transistor is represented.
Needless to say, the field effect transistor of the body terminal structure shown in having here can have other transistor arrangements, have the device characteristics shown in the example application of disclosed in the present invention current generating circuit and display device, but have the component characteristic of equivalence.
P raceway groove (P channel-type) thin film transistor (TFT) with the body terminal arrangement shown in Figure 51 A-51B and Figure 52 A-52B has following configuration, comprise that knot forms terminal area RT (n+), from channel region Rchn vertically (above-below direction of Figure 51 A) to rotary-inversion axis mutually (horizontal direction of Figure 51 A) projection of source region RS and drain region RD, and pass channel region Rchn (body region), via insulation course insS, form in the N channel semiconductor layer (active layer Rac) that in the whole face side of the silicon of N channel semiconductor substrate sub etc., is constituted and separate active region RS (p+) and drain region RD (p+).
In addition, the top at the active layer Rac shown in Figure 51 B and Figure 52 A-52B comprises monolithic entity terminal electrode EB, has formed ohm contact in source region RS and terminal area RT; Form gate electrode by gate insulator insG on the top of channel region Rchn; And in the RD of drain region, form drain electrode ED ohm contact.Utilize the circuit symbol shown in Figure 52 C to represent to have the N channel transistor of such body terminal arrangement.
Although explained the P channel-type thin film transistor (TFT) with above-mentioned body terminal arrangement, the N channel-type thin film transistor (TFT) with the body terminal arrangement that is configured to shown in Figure 51 A-51B and Figure 52 A-52B is the almost configuration of equivalence.Although formed source region (n+) and drain region (n+) in the active layer that is made of the P channel semiconductor layer that passes channel region, terminal area (p+) has the configuration that forms from the knot of channel region projection.The configuration of gate electrode, drain electrode and body terminal electrode is identical with the situation of above-mentioned p channel transistor.The circuit symbol of utilization shown in Figure 52 D represents to have the N channel transistor of such body terminal arrangement.
Figure 53 A-53B shows the basic circuit of the N channel thin-film transistor with body terminal arrangement and the figure of voltage-current characteristic.
Figure 54 A-54B shows the basic circuit of the P channel thin-film transistor with body terminal arrangement and the figure of voltage-current characteristic.
When using basic circuit that constitutes by the N raceway groove with such body terminal structure (n channel-type) transistor shown in Figure 53 A and Figure 54 A and the voltage-current characteristic in the P raceway groove shown in Figure 53 B and Figure 54 B (p channel-type) thin film transistor (TFT) to verify, in the given voltage zone, the voltage Vds between the source drain ,-(Vds), drain current Ids ,-(Ids) show desirable saturated inclination.
This is because (N raceway groove＞have electronics lacks or the n channel transistor in hole when minority carrier, and P raceway groove＞p channel transistor electronics) when the electronics that boundary vicinity produced of above-mentioned channel region Rchn and drain region RD and electron hole centering flow into source region RS via body terminal electrode EB, controlled the generation of kink phenomenon, thereby controlled accumulation, and alleviated the reduction of the threshold voltage of field effect transistor channel region Rchn.
Therefore, according to the present invention, solution be the field effect transistor that will have such voltage-current characteristic be applied in current mirror circuit that the current generation section of each the foregoing description divides and the pixel-driving circuit, be used for light and produce the transistor that drives.Especially, when in the data driver of current generating circuit related to the present invention, display device, display board etc., being configured, because write current, light generation drive current has and according to the corresponding suitable current value of the electric current that video data kept, perhaps can produce level data.Therefore, can be according to video data, the light of carrying out in each display pixel with suitable levels of luminosity produces operation, and can realize the raising of image quality.
Although described the present invention, should be appreciated that the present invention should not describe details arbitrarily by it and limit with reference to preferred embodiment.
Can not break away from the spirit of its essential feature and come specific implementation the present invention in a variety of forms, therefore, current embodiment only is illustrative but not determinate, this be since scope of the present invention by claims but not limit by the description before it, and drop on the needs of claim and define in all changes or its such needs and the equivalent that defines should contain by claim.

Claims (54)

1, the shows signal that is made of digital signal of a kind of basis is come the display device of displays image information, it is characterized in that, comprising:
Display board (110A) comprises decussate each other many signal line (DL) and multi-strip scanning line (SL) and has near the point of crossing that is arranged in described many signal line and multi-strip scanning line a plurality of display pixels (EM) of optical element;
(120A 120B), is used for the sweep signal order is applied to each signal line, so that the selection mode of each display pixel of each line is set scan drive circuit; And
Signal drive circuit (130A-G) comprises a plurality of current generating circuits (ILA, ILB, ISA, ISB, ISC-F, PXA-D); Described current generating circuit comprises that at least grading current produces circuit (21A-D) and drive current produces circuit; Described grading current produces circuit according to constant predetermined reference current, produce and the corresponding a plurality of grading currents of each shows signal bit, and described drive current produces circuit (22A-D) based on the value that the shows signal of the drive current that is produced is provided to each signal line, produces drive current according to a plurality of grading currents.
2, display device according to claim 1 is characterized in that, each current generating circuit is provided with the signal polarity of drive current, thereby drive current is flow through in the direction of drawing from the display pixel side.
3, display device according to claim 1 is characterized in that, each current generating circuit is provided with the signal polarity of drive current, thereby drive current is flow through pouring on the direction of display pixel.
4, display device according to claim 1 is characterized in that, with each each of a plurality of current generating circuits in the signalization driving circuit accordingly of a plurality of display pixels of each sweep trace of display board.
5, display device according to claim 4 is characterized in that, each current generating circuit provides each the corresponding drive current with a plurality of pixels of each sweep trace simultaneously.
6, display device according to claim 1 is characterized in that, each current generating circuit also comprises signal holding circuit (10,101,102,103), is used for receiving and keeping shows signal.
7, display device according to claim 6 is characterized in that, drive current generation circuit produces drive current according to the value of the shows signal that is kept in signal holding circuit.
8, display device according to claim 6 is characterized in that, signal holding circuit comprises a plurality of latch cicuits, and (LC2 LC3), be used for receiving and keeping each shows signal bit, and output is in response to the output signal of each bit for LC0, LC1.
9, display device according to claim 1 is characterized in that, drive current produces circuit and comprises commutation circuit (Tr26-Tr29, Tr36-Tr39, Tr66-Tr69), be used to respond each bit value of shows signal, from a plurality of grading currents, select grading current.
10, display device according to claim 9 is characterized in that, described current generating circuit also comprises signal holding circuit, is used for receiving and keeping shows signal.
11, display device according to claim 10 is characterized in that, signal holding circuit comprises a plurality of latch cicuits, is used to receive and keep each bit of shows signal, and output is in response to the output signal of each bit;
Commutation circuit is selected grading current, and produces current drives according to the output of a plurality of latch cicuits.
12, display device according to claim 1 is characterized in that, the current value of a plurality of grading currents has by 2 nThe ratio that differs from one another of appointment, n are 0 or 1 or bigger integer.
13, display device according to claim 1 is characterized in that, each grading current produces circuit and comprises that (Tr22-Tr25, Tr32-Tr35 Tr62-Tr65), are used to produce a plurality of grading currents to a plurality of grading current transistors.
14, display device according to claim 13 is characterized in that, transistorized each the transistor size difference of described a plurality of grading currents, and its each control terminal is connected in parallel;
Grading current flows through on the transistorized current path of each grading current.
15, display device according to claim 14 is characterized in that, with by 2 nThe ratio that differs from one another of appointment is provided with the transistorized channel width of each grading current, and n is 0 or 1 or bigger integer.
16, display device according to claim 13 is characterized in that, each grading current produces circuit and comprises generating circuit from reference voltage, is used for producing reference voltage according to reference current.
17, display device according to claim 16 is characterized in that, generating circuit from reference voltage comprises that (Tr21, Tr31 Tr61), are used to produce the reference voltage to control terminal to reference current transistor; Reference current is offered current path between source terminal and drain terminal;
The reference current transistor control terminal is connected to the transistorized control terminal of a plurality of grading currents jointly.
18, display device according to claim 17 is characterized in that, reference current transistor and a plurality of grading current transistor have constituted current mirror circuit.
19, display device according to claim 17 is characterized in that, any reference current transistor and a plurality of grading current transistor have constituted following transistor arrangement at least, comprising:
Channel region (Rchn) in the whole face side of Semiconductor substrate (sub), the semiconductor layer (Rac) that forms by insulation course;
Pass source region (RS) and drain region (RD) that channel region (Rchn) forms;
From channel region vertically to the opposite aixs cylinder of source region and drain region and the terminal area (RT) that forms;
The gate electrode (EG) that on described channel region, forms by gate insulator;
The drain electrode that is electrically connected with the drain region (ED); And
The monolithic entity terminal electrode (EB) that is electrically connected with source region and terminal area.
20, display device according to claim 1 is characterized in that, each grading current produces circuit and also comprises generating circuit from reference voltage, is used for producing reference voltage according to reference current.
21, display device according to claim 20 is characterized in that generating circuit from reference voltage comprises charge storage circuit (C1), is used for the electric charge of memory response in the current component of reference current.
22, display device according to claim 1 is characterized in that, signal drive circuit comprises:
The reference current supply lines is used to provide reference current; And
Wherein produce the structure that circuit provides reference current to a plurality of grading currents by the reference current supply lines;
23, display device according to claim 22 is characterized in that, each grading current produces circuit and comprises that (TS1 TS2), is used to control the power supply state that produces circuit from the reference current supply lines to suitable grading current to power supply control commutation circuit;
Power supply control commutation circuit selectivity is carried out switching controls, thereby any the grading current circuit that only produces circuit to a plurality of grading currents provides reference current.
24, display device according to claim 23 is characterized in that, each current generating circuit comprises signal holding circuit, is used for receiving and keeping shows signal.
25, display device according to claim 24 is characterized in that, the power supply of switching controls control commutation circuit regularly when receiving and keep shows signal and the timing of signal holding circuit synchronous.
26, display device according to claim 1, it is characterized in that, each current generating circuit comprises that also designated state is provided with circuit (30A, 30B), be used for signal wire and be set to given voltage (Vbk, Vr), when shows signal had designated value, described given voltage made optical element drive the assigned operation state that is in.
27, display device according to claim 26 is characterized in that, produces the drive current that is used for selecting according to each shows signal bit grading current;
The shows signal designated value is to have set the value of all grading currents of non-selected state;
Given voltage is the voltage that is used for optical element is driven the state that is arranged on the lowest class.
28, display device according to claim 26 is characterized in that, designated state is provided with circuit and comprises designation number value judgment part (31,33), is used to judge whether shows signal is designated value; And the given voltage applying portion (TN32 TP34), is used for the judged result according to designation number value judgment part, applies given voltage to signal wire.
29, display device according to claim 28 is characterized in that, designation number value judgment part according to the logic of each bit value of the digital signal of shows signal and, judge whether described shows signal is designated value.
30, display device according to claim 1 is characterized in that, each current generating circuit comprises that also (30A 30B), is used for applying predetermined reset voltage (Vr) to signal wire before providing the timing of drive current to signal wire reset circuit.
31, display device according to claim 30, it is characterized in that resetting voltage is at least low-potential voltage, be used for stored charge in the capacitive element on the optical element that appends to display pixel is discharged, and be used for optical element is carried out initialization.
32, display device according to claim 30 is characterized in that, produces the drive current that is used for selecting according to each shows signal bit grading current;
When the shows signal designated value presupposes non-selected a plurality of grading currents whole, apply described resetting voltage.
33, display device according to claim 32 is characterized in that, described reset circuit comprises:
Designation number value judgment part (31,33) is used to judge whether shows signal is designated value; And
(TN32 TP34), is used for the judged result according to designation number value judgment part to the resetting voltage applying portion, applies resetting voltage to signal wire.
34, display device according to claim 33 is characterized in that, designation number value judgment part according to the logic of each bit value of the digital signal of shows signal and, judge whether shows signal is designated value.
35, display device according to claim 1 is characterized in that, the optical element in the display pixel comprises light-emitting component, is used for by the levels of luminosity according to the current value of supply current, realizes that light produces operation.
36, display device according to claim 35 is characterized in that, described optical element comprises organic electroluminescent device.
37, display device according to claim 35 is characterized in that, display pixel comprise at least pixel-driving circuit (DCx, DCy);
Pixel-driving circuit comprises that (Cx Cy), is used to keep the component of voltage in response to the drive current that provides from signal drive circuit to voltage hold circuit; And
Current suppling circuit (Tr73, Tr81, Tr83, Tr91, Tr93 Tr103), is used for the component of voltage that keeps according to voltage hold circuit, provides light emission drive current to light-emitting component, and makes light-emitting component luminous.
According to the described display device of claim 37, it is characterized in that 38, pixel-driving circuit comprises discharge circuit (Tr85), be used for the electric charge in response to voltage hold circuit institute stored voltage component is discharged.
According to the described display device of claim 37, it is characterized in that 39, current suppling circuit comprises the transistor that is used for light emitting drive, be used for providing glow current to light-emitting component;
The transistor that is used for light emitting drive has following transistor arrangement, comprising:
Channel region;
Pass source region and drain region that channel region forms;
From channel region vertically to the opposite aixs cylinder of source region and drain region and the terminal area that forms;
The gate electrode that on channel region, forms by gate insulator;
The drain electrode that is electrically connected with the drain region; And
The monolithic entity terminal electrode that is electrically connected with source region and terminal area;
Described channel region, source region, drain region and terminal area are formed at a semiconductor layer, and described semiconductor layer is formed on the insulation course, and described insulation course is formed at the whole face side of Semiconductor substrate.
40, a kind of driving is used for the method for coming the display device of displays image information according to the shows signal that is made of digital signal in the display board, described display board comprises a plurality of display pixels, has near the optical element of the point of crossing of many signal line and multi-strip scanning line, arranging, it is characterized in that described method comprises:
Reception and maintenance and the corresponding shows signal of a plurality of display pixel;
From a plurality of grading currents that produce accordingly based on constant predetermined reference current and each shows signal bit, the value of shows signal produces drive current according to maintenance; And
Provide drive current to many signal line.
41, according to the described method that is used to drive display device of claim 40, it is characterized in that the current value of a plurality of grading currents has by 2 nThe ratio that differs from one another of appointment, n are 0 or 1 or bigger integer.
According to the described method that is used to drive display device of claim 40, it is characterized in that 42, described generation drive current step comprises: with select accordingly in response to the grading current of each bit value of shows signal and gather.
43, according to the described method that is used to drive display device of claim 40, it is characterized in that, the signal polarity of drive current is set, thereby drive current is flow through in the direction of drawing from display pixel.
44, according to the described method that is used to drive display device of claim 40, it is characterized in that, the signal polarity of drive current is set, thereby drive current is flow through pouring on the direction of display pixel.
45, according to the described method that is used to drive display device of claim 40, it is characterized in that the optical element in the display pixel comprises light-emitting component, be used for, realize that light produces operation by levels of luminosity according to the current value of supply current.
46,, it is characterized in that described light-emitting component element comprises organic electroluminescent device according to the described method that is used to drive display device of claim 45.
47, according to the described method that is used to drive display device of claim 45, it is characterized in that, also comprise:
Keep and the corresponding component of voltage of drive current;
Make light-emitting component component of voltage luminous, that voltage hold circuit kept according to being used for, provide light emission drive current to light-emitting component.
48, according to the described method that is used to drive display device of claim 40, it is characterized in that, also comprise:
Judge whether shows signal is designated value;
When concluding that shows signal is designated value, apply the given voltage that is used to make the display pixel driving be in the assigned operation state and be applied to signal wire.
49, according to the described method that is used to drive display device of claim 48, it is characterized in that,, produce drive current by selecting grading current according to each shows signal bit;
Designated value is according to shows signal whole value of non-selected each grading current therefrom;
Given voltage is the voltage that is used for optical element is driven the state that is arranged on the lowest class.
50, according to the described method that is used to drive display device of claim 40, it is characterized in that, also comprise: timing place before applying drive current to each signal wire applies predetermined reset voltage to signal wire.
51, according to the described method that is used to drive display device of claim 50, it is characterized in that, described resetting voltage is at least low-potential voltage, is used for initialization is carried out in each load, and discharges to appending in the capacitive element in each load stored charge.
52, according to the described method that is used to drive display device of claim 51, it is characterized in that, by selecting grading current to produce drive current according to each shows signal bit;
When shows signal becomes the designated value that presupposes non-selected all grading currents, apply resetting voltage.
According to the described method that is used to drive display device of claim 52, it is characterized in that 53, described resetting voltage applies step and also comprises:
Judge whether shows signal is designated value;
When concluding that shows signal is designated value, apply resetting voltage to signal wire.
54, according to the described method that is used to drive display device of claim 40, it is characterized in that, also comprise: timing place before applying drive current to each signal wire, discharge to appending in the capacitive element on the optical element in the display pixel stored charge.
CNB2003801024018A 2002-10-31 2003-10-29 The method of display device and driving display device Expired - Fee Related CN100541580C (en)

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