CN100517700C - image sensor packaging structure - Google Patents
image sensor packaging structure Download PDFInfo
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- CN100517700C CN100517700C CNB200710089689XA CN200710089689A CN100517700C CN 100517700 C CN100517700 C CN 100517700C CN B200710089689X A CNB200710089689X A CN B200710089689XA CN 200710089689 A CN200710089689 A CN 200710089689A CN 100517700 C CN100517700 C CN 100517700C
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- 238000004806 packaging method and process Methods 0.000 title claims abstract description 12
- 239000000758 substrate Substances 0.000 claims abstract description 105
- 230000004308 accommodation Effects 0.000 claims description 22
- 238000005516 engineering process Methods 0.000 claims description 10
- 239000011521 glass Substances 0.000 claims description 5
- 239000000565 sealant Substances 0.000 claims description 5
- 238000010586 diagram Methods 0.000 description 9
- 238000000034 method Methods 0.000 description 8
- 238000012360 testing method Methods 0.000 description 8
- 239000004065 semiconductor Substances 0.000 description 7
- 239000003990 capacitor Substances 0.000 description 6
- 239000013078 crystal Substances 0.000 description 6
- 238000012856 packing Methods 0.000 description 6
- 230000000295 complement effect Effects 0.000 description 5
- 230000001788 irregular Effects 0.000 description 5
- 238000013461 design Methods 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 239000011469 building brick Substances 0.000 description 3
- 229910044991 metal oxide Inorganic materials 0.000 description 3
- 150000004706 metal oxides Chemical class 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 230000008901 benefit Effects 0.000 description 2
- 230000002950 deficient Effects 0.000 description 2
- 238000011161 development Methods 0.000 description 2
- 230000018109 developmental process Effects 0.000 description 2
- 230000008034 disappearance Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000004100 electronic packaging Methods 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 239000012530 fluid Substances 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012536 packaging technology Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000012797 qualification Methods 0.000 description 1
- 238000012827 research and development Methods 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- Solid State Image Pick-Up Elements (AREA)
- Transforming Light Signals Into Electric Signals (AREA)
Abstract
一种影像感应器的封装结构，包括基板、透镜模块及底盖。其中，此基板具有上表面及下表面，且下表面制作有数个无源组件，并在上表面设置有一芯片，接着将透镜模块套合于基板上且包覆芯片，然后将底盖连接于基板的下表面且包覆无源组件。
An image sensor packaging structure includes a substrate, a lens module and a bottom cover. The substrate has an upper surface and a lower surface, and a plurality of passive components are made on the lower surface. A chip is arranged on the upper surface, and then the lens module is mounted on the substrate and covers the chip, and then the bottom cover is connected to the lower surface of the substrate and covers the passive components.
Description
Technical field
The invention relates to a kind of image sensor package structure, particularly relevant for a kind of CMOS camera lens module (CMOS Camera Module; CCM) passive block is caused irregular problem to solve passive block at substrate back by a bottom is set.
Background technology
Indispensable computer, mobile phone, digital camera and LCD etc. in people's life now, none is not the Related product of semi-conductor industry, its relevant peripheral product is various especially, the rich potentiality and the importance that demonstrate electronics industry.In recent years, under the demand of people for the lifting rapidly of electronic product function and diversification, portable and light and handyization, its packaging technology dealer has broken away from traditional technology and towards high precision technological developments such as high power, high density, light, thin and microminiaturizations, except above-mentioned trend, Electronic Packaging still need possess high-reliability, thermal diffusivity is good and necessary characteristic such as low manufacturing cost, with the challenge in the face of launch time-histories and life cycle.
In numerous electronic products, the most in vogue with audio-visual multimedia again, and the release of products such as digital camera, digital photography and image scanner makes image digitization become inevitable trend.Wherein important key part and component is exactly image sensor (Image Sensor).This image sensor is to be a kind of semiconductor chip, it can be converted to electronic signal with light signal, and this semiconductor chip and comprise a photosensory assembly, such as a complementary matal-oxide semiconductor (Complementary Metal-OxideSemiconductor, CMOS).In order to cooperate of the development of CMOS image sensor, therefore how chip wherein had light and handy and best effect, still the emphasis that develops for WeiLai Technology in portable product market.
Yet in the encapsulation technology of chip,, thin, short, little trend light and the chip package technology that develops out at product, it mainly is the arrangement mode that utilizes the face array, go up configuration a plurality of chip mats (pad) on the active surface of chip (active surface), and utilize and on chip mat, form projection, then utilize this projection to be electrically connected to a substrate.It should be noted that because chip package can be applicable to the chip-packaging structure of high pin number, and have plurality of advantages such as the package area of dwindling and shortening signal transmission path, make the chip package technology be widely used in the Chip Packaging field at present.
In addition for the electrical design of the integral body that meets chip-packaging structure, more configurable a plurality of passive blocks on the surface of the substrate of chip package, such as capacitor (capacitor), inductor (inductor) and resistor (resistor) etc., and these passive blocks more can pass through the internal wiring in the crystal-coated packing substrate plate, and are electrically connected to chip or other electronic building brick.In other words, chip is can be via the internal wiring of projection and crystal-coated packing substrate plate, and is electrically connected to these passive blocks.
Seeing also shown in Figure 1ly, is the encapsulating structure that discloses known a kind of image sensor, and this image sensor 1 mainly comprises substrate 10, several passive blocks 11, chip (chip) 12 and lens module 13.
Wherein substrate 10 has upper surface 101 and lower surface 102, and these passive blocks 11 are to fix (Surface Mount Technology with the surface; SMT) lower surface 102 in substrate 10 is being covered in the structure installing fully.Then the upper surface 101 to chip 12 and substrate 10 carries out routing to constitute electric connection, and its chips 12 has photosensory assembly, and it is positioned on the chip 12.At last lens module 13 is combined on the substrate 10, and is to constitute confined space with substrate 10 and chip 12.Therefore when light passes through the camera lens of lens module 13, and can shine on photosensory assembly and and work, and then convert electric signal to light.
Because having, the overall dimensions of present encapsulating structure more does the little trend that heals; but making number because of passive block has increasing phenomenon it seems; above-mentioned known techniques is because of being arranged at passive block the lower surface of substrate; cause the evenness of base lower surface not good; and then make this encapsulating structure at last when carrying out module testing; regular meeting causes the signal test to go wrong because of the out-of-flatness of the lower surface of substrate, and has influenced the test yield of whole encapsulating structure.
Therefore the people is arranged is the side that passive block is arranged at substrate for this reason, solves the passive block number too much and be arranged at the irregular problem of base lower surface.But because of passive block is arranged at side is to cause the substrate size of this encapsulating structure to become big, therefore also can't solve the above-mentioned problem that occurs.
For the related personnel who is engaged in image sensor manufacturing and research and development, there's no one who doesn't or isn't be devoted to the improvement of passive block technology, cause irregular problem in the hope of solving known techniques because of passive block places the lower surface of the substrate of CCM, cause the signal testing non-defective unit of CCM image sensor to reach stable purpose.
Summary of the invention
Purpose of the present invention promptly is that a kind of image sensor package structure is being provided, and is applied to CMOS camera lens module (CMOS Camera Module; CCM) passive block is by adding bottom to solve passive block in the not good problem of evenness that substrate back is caused.
The encapsulating structure of a kind of image sensor of the present invention comprises substrate, chip, several passive blocks, lens module and bottom.Wherein, substrate has a upper surface and a lower surface, and chip is the upper surface that is arranged at substrate, and several passive blocks also are arranged at the lower surface of this substrate.Lens module is sleeved on the substrate and defines first accommodation space, and this chip is to be positioned at first accommodation space, and bottom is connected in the lower surface of substrate, and defines second accommodation space, and those passive blocks are to be positioned at second accommodation space.
In one embodiment of this invention, wherein passive block is by surperficial technique for fixing (SMT), disposes and be electrically connected to the lower surface of substrate.
In one embodiment of this invention, chip is to connect (wire bonding) by routing, is electrically connected to the upper surface of substrate.Perhaps, be electrically connected to the upper surface of substrate with Flip Chip.
In one embodiment of this invention, wherein lens module comprises lens barrel, camera lens and microscope base, and microscope base is to be set up on the substrate, and microscope base is carried on lens barrel, and lens barrel and support lens are when light passes through on the lens lighting chip, chip will work to light, and convert electric signal to.
In one embodiment of this invention, its chips more comprises photosensory assembly, with so that this chip light is worked.And this photosensory assembly is to can be complementary metal oxide silicon (complementarymetal-oxide semiconductor; CMOS, or can be charge coupled device (CCD).
In one embodiment of this invention, lens module more comprises filter, is set up between camera lens and the chip.And this filter is to can be glass or infrared ray low pass filter (IR low pass filter).
In another embodiment of the present invention, it comprises lens module, substrate and connector the encapsulating structure of image sensor.Wherein the bottom of lens module is provided with accommodation space, and is provided with an opening at a side, and the upper surface of substrate is provided with chip, its lower surface is provided with several passive blocks, wherein this substrate can insert in this accommodation space, and connector is that opening combines therewith, makes substrate package in inside of lens module.
In another embodiment of the present invention, more comprise sealant, be disposed between the opening of connector and lens module, in order to opening portion is attached on the connector.
In another embodiment of the present invention, wherein passive block is by surperficial technique for fixing (SMT), disposes and be electrically connected to the lower surface of substrate.
In another embodiment of the present invention, its chips is to connect (wire bonding) by routing, is electrically connected to the upper surface of this substrate, perhaps utilizes Flip Chip to be electrically connected to the upper surface of substrate.
In another embodiment of the present invention, connector is to be electrically connected to external printed circuit board.
In another embodiment of the present invention, chip more comprises photosensitive area, corresponding to lens module, with so that chip light is worked.
In another embodiment of the present invention, wherein lens module more comprises filter, is set up between camera lens and the chip.And this filter is to can be glass or infrared ray low pass filter (IR low passfilter).
In order further to understand feature of the present invention and technology contents, see also following about detailed description of the present invention and accompanying drawing, yet appended graphic only provide with reference to and the explanation usefulness, be not to be used for the present invention is limited.
Description of drawings
Fig. 1 is the schematic diagram that illustrates the encapsulating structure of known a kind of image sensor;
Fig. 2 a is that the passive block that illustrates the encapsulating structure of image sensor of the present invention is arranged at the schematic diagram on the substrate;
Fig. 2 b is that the chip that illustrates the encapsulating structure of image sensor of the present invention is arranged at the schematic diagram on the substrate;
Fig. 2 c is that the lens module of encapsulating structure that illustrates the image sensor of the first embodiment of the present invention is arranged at the schematic diagram on the substrate;
Fig. 2 d is that the bottom of encapsulating structure that illustrates the image sensor of the first embodiment of the present invention is arranged at the schematic diagram on the substrate;
Fig. 3 a is that the passive block of encapsulating structure that illustrates the image sensor of the second embodiment of the present invention is arranged at the schematic diagram on the substrate;
Fig. 3 b is that the connector of encapsulating structure that illustrates the image sensor of the second embodiment of the present invention is arranged at the schematic diagram on the substrate;
Fig. 3 c is that the chip of encapsulating structure that illustrates the image sensor of the second embodiment of the present invention is arranged at the schematic diagram on the substrate; And
Fig. 3 d is that the lens module of encapsulating structure that illustrates the image sensor of the second embodiment of the present invention is arranged at the schematic diagram on the substrate.
The primary clustering symbol description
1,2,3 image sensors
10,20,30 substrates
101,201,301 upper surfaces
102,202,302 lower surfaces
203 first accommodation spaces
204 second accommodation spaces
11,21,31 passive blocks
12,22,32 chips
13,23,33 lens modules
231,331 camera lenses
232,332 lens barrels
233,333 microscope bases
24 bases
25,35 filters
303 connectors
304 fluid sealants
Embodiment
The present invention is the encapsulating structure that discloses a kind of image sensor, and is applied to CMOS camera lens module (CMOS Camera Module; CCM) passive block is by adding a bottom solving passive block in the not good problem of evenness that substrate back is caused, and then the test passes rate problem of solution encapsulating structure.Shown in relevant of the present invention being described in detail as follows.
First embodiment:
According to Fig. 2 a～d, be the encapsulating structure that has shown the image sensor of the disclosed CMOS camera lens module of the present invention (CCM).As shown in FIG., the encapsulating structure of this image sensor 2 comprises substrate 20, chip 22, several passive blocks 21, lens module 23 and bottom 24.Wherein, substrate 20 has upper surface 201 and lower surface 202.Chip 22 is the upper surfaces 201 that are arranged at substrate 20, again several passive blocks 21 and be arranged at the lower surface 202 of this substrate 20.Then lens module 23 is sleeved on the substrate 20 and defines first accommodation space 203, and this chip 22 is to be positioned at first accommodation space 203, and bottom 24 is connected in the lower surface 202 of substrate 20, then define second accommodation space 204, and those passive blocks 21 are to be positioned at second accommodation space 204.
, shown in Fig. 2 a, be to utilize surperficial technique for fixing (SMT) at the lower surface 202 of substrate 20 generally, disposed and electrically connected the lower surface 202 of a plurality of passive blocks 21 in substrate 20 for the electrical design of the integral body that meets chip-packaging structure.Wherein such as capacitor (capacitor), inductor (inductor) and resistor (resistor) etc., and these passive blocks 21 are the internal wiring and a pair of outer contacts that can pass through in the crystal-coated packing substrate plate, and are electrically connected to chip or other electronic building brick.
Then shown in Fig. 2 b, chip 22 is arranged at the upper surface 201 of substrate 20, change speech, chip 22 is can be via the internal wiring of projection and crystal-coated packing substrate plate 20, and is electrically connected to these passive blocks 21.As shown in this embodiment, chip 22 is to connect the upper surface 201 that (wire bonding) is electrically connected to substrate 20 via routing.
Shown in Fig. 2 c, be that lens module 23 is assembled on the substrate 20, the lens module 23 among the embodiment comprises lens barrel 232, camera lens 231 and microscope base 233, microscope base 233 is to be set up on the substrate 20, and microscope base 233 is carried on lens barrel 232, lens barrel 232 and support lens 231.Wherein impinge upon on the core shooting sheet 22 when light passes through lens, chip 22 will work to light, and convert electric signal to.Its chips 22 more comprises photosensitive area, corresponding to lens module 23, with so that 22 pairs of light of this chip work.And this photosensory assembly is to can be complementary metal oxide silicon (complementarymetal-oxide semiconductor; CMOS) or charge coupled device (CCD).
Moreover, shown in Fig. 2 d, be sleeved on the substrate 20 above-mentioned lens module 23 and coating chip 22, and constitute first accommodation spaces 203 with substrate 20 and be a confined space.Then bottom 24 is connected in the lower surface 202 of substrate 20 and coats passive block, wherein the bottom of bottom is required to be smooth bottom surface, and be " ㄇ " type structure, the side of this " ㄇ " type structure is to have a draw-in groove respectively, can snap in the grab that base plate bottom pre-sets, and in order to fixing this substrate 20 bottom 24 therewith, and the lower surface 202 of substrate 20 therewith bottom 24 also can form this second accommodation space 204.Wherein lens module 23 is to be the lens module of focusing automatically.And comprise the automatic focusing driver that is arranged in second accommodation space 204.
Person more, substrate 20 has first location hole, and lens module 23 has corresponding dowel, and lens module 23 is that the clamping via the dowel and first location hole is arranged on the substrate 20.Wherein bottom 24 has more second location hole, and utilizes dowel to penetrate first location hole and be engaged in second location hole, with fixed lens module 23, substrate 20 and bottom 24.
Second embodiment:
According to Fig. 3 a～d, be the encapsulating structure that has shown the image sensor 3 of disclosed another CMOS camera lens module (CCM) of the present invention.As shown in FIG., the encapsulating structure of image sensor comprises lens module 33, substrate 30 and connector 303.Wherein the bottom of lens module 33 is provided with accommodation space, and be provided with an opening at a side, and the upper surface of substrate 30 is provided with chip 32, its lower surface is provided with several passive blocks 31, wherein this substrate 30 can insert in this accommodation space, connector 303 is that opening combines therewith, makes substrate 30 be packaged in lens module 33 inside.
As described in the first embodiment, generally for the electrical design of the integral body that meets chip-packaging structure, shown in Fig. 3 a, substrate 30 has upper surface 301 and lower surface 302, and lower surface 302 is to be manufactured with several passive blocks 31, and the lower surface 302 of substrate 30 is to utilize surperficial technique for fixing (SMT), has disposed and electrically connected a plurality of passive blocks 31 on the lower surface 302 of substrate 30.Wherein such as capacitor (capacitor), inductor (inductor) and resistor (resistor) etc., and these passive blocks 31 are can be by the internal wiring in the crystal-coated packing substrate plate, and are electrically connected to chip 32 or other electronic building brick.
Shown in Fig. 3 b, be a side that connector 303 is arranged at the upper surface 301 of substrate 30, and this connector 303 is to can be soft board connector (connect with FPC) to constitute then.
Shown in Fig. 3 c, chip 32 is arranged at the upper surface 301 of substrate 30, change speech, chip 32 is can be via the internal wiring of projection and crystal-coated packing substrate plate, and is electrically connected to these passive blocks 31.In the present embodiment, chip 32 is to connect (wire bonding) via routing to be electrically connected on the upper surface 301 of substrate 30.
Shown in Fig. 3 d, the bottom of lens module 33 is to be provided with accommodation space, and be provided with an opening at a side, this opening is to cooperate connector 303 positions on the substrate 30 to be provided with, with so that substrate 30 can insert in this accommodation space, and connector 303 opening therewith combines, and makes substrate 30 be packaged in lens module 33 inside.And the passive block 31 of lower surface 302 also can be coated in the space of this bottom.Wherein lens module 33 more comprises a draw-in groove, and substrate 30 is to be connected in this draw-in groove.
Last and between the opening of connector 303 and lens module 33, coat sealant 304 and make this opening be attached on this connector 303.And sealant 304 is to can be UV cured solid (UV glue).This outconnector 303 is to be electrically connected to the external printed circuit board (not shown).
In sum, image sensor of the present invention, compared to known image sensor, be that the back side (lower surface) of the substrate that solved has produced the not good problem of evenness because of passive block setting, and then also can solve the not good shortcoming of signal testing qualification rate of inductor.Image sensor of the present invention by embedding a bottom and coat those passive blocks, and makes the bottom of test be kept the usefulness of its planarization as its electrics connection in first embodiment, more can thereby not cause signal to test the generation of fraction defective.In addition in a second embodiment, because of a side opening of scioptics module snaps in and coats substrate and passive block, and make the sealing of this accommodation space by connector, and the bottom surface that reaches the inductor of institute of the present invention demand has the benefit of planarization, to solve the disappearance that above-mentioned known techniques is brought.
In addition because known techniques is that the design that passive block is arranged at the side of substrate is arranged, solve the passive block number too much and be arranged at the irregular problem of base lower surface.But can cause the substrate size of this encapsulating structure to become big because of passive block is arranged at side, therefore image sensor of the present invention not only can not make this assembling structure strengthen, and has also solved the irregular disappearance of substrate back (lower surface) simultaneously.
Though the present invention's preferred embodiments illustrates as above, be not only to terminate in the foregoing description with the invention entity in order to limit the present invention's spirit.So the modification of being done in not breaking away from spirit of the present invention and scope all should be included in the claim scope.
Claims (10)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB200710089689XA CN100517700C (en) | 2007-03-27 | 2007-03-27 | image sensor packaging structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB200710089689XA CN100517700C (en) | 2007-03-27 | 2007-03-27 | image sensor packaging structure |
Publications (2)
| Publication Number | Publication Date |
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| CN101026149A CN101026149A (en) | 2007-08-29 |
| CN100517700C true CN100517700C (en) | 2009-07-22 |
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| CNB200710089689XA Active CN100517700C (en) | 2007-03-27 | 2007-03-27 | image sensor packaging structure |
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Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2015026946A (en) * | 2013-07-25 | 2015-02-05 | 株式会社東芝 | Camera module |
| KR20180054799A (en) * | 2015-11-27 | 2018-05-24 | 차이나 와퍼 레벨 씨에스피 씨오., 엘티디. | Image sensing chip packaging structure and method |
| CN108269781A (en) * | 2018-03-27 | 2018-07-10 | 苏州晶方半导体科技股份有限公司 | The encapsulating structure and packaging method of a kind of chip |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6683795B1 (en) * | 2002-04-10 | 2004-01-27 | Amkor Technology, Inc. | Shield cap and semiconductor package including shield cap |
| CN1591885A (en) * | 2003-08-25 | 2005-03-09 | 株式会社瑞萨科技 | Manufacturing method of solid-state image sensing device |
| CN1601752A (en) * | 2003-09-22 | 2005-03-30 | 株式会社瑞萨科技 | Method for manufacturing solid-state image sensing device |
| CN1606158A (en) * | 2003-06-11 | 2005-04-13 | 三星电子株式会社 | CMOS device type image sensor module |
| US6952046B2 (en) * | 2002-06-19 | 2005-10-04 | Foster-Miller, Inc. | Electronic and optoelectronic component packaging technique |
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2007
- 2007-03-27 CN CNB200710089689XA patent/CN100517700C/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6683795B1 (en) * | 2002-04-10 | 2004-01-27 | Amkor Technology, Inc. | Shield cap and semiconductor package including shield cap |
| US6952046B2 (en) * | 2002-06-19 | 2005-10-04 | Foster-Miller, Inc. | Electronic and optoelectronic component packaging technique |
| CN1606158A (en) * | 2003-06-11 | 2005-04-13 | 三星电子株式会社 | CMOS device type image sensor module |
| CN1591885A (en) * | 2003-08-25 | 2005-03-09 | 株式会社瑞萨科技 | Manufacturing method of solid-state image sensing device |
| CN1601752A (en) * | 2003-09-22 | 2005-03-30 | 株式会社瑞萨科技 | Method for manufacturing solid-state image sensing device |
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| CN101026149A (en) | 2007-08-29 |
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