CN100499125C - Semiconductor device - Google Patents
Semiconductor device Download PDFInfo
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- CN100499125C CN100499125C CN 200610090383 CN200610090383A CN100499125C CN 100499125 C CN100499125 C CN 100499125C CN 200610090383 CN200610090383 CN 200610090383 CN 200610090383 A CN200610090383 A CN 200610090383A CN 100499125 C CN100499125 C CN 100499125C
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
- H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
- H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
- H01L2224/02165—Reinforcing structures
- H01L2224/02166—Collar structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05553—Shape in top view being rectangular
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
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- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
To provide a highly reliable semiconductor device in which a semiconductor element can be provided under a pad. The semiconductor device comprises a semiconductor layer 10 having an element forming region 10A and an isolation region 20 provided around the element forming region 10A, an element 30 formed in the element forming region 10A, an interlayer insulation layer 60 provided above the semiconductor layer 10, and an electrode pad 62 of rectangular plan view having short and long sides provided above the interlayer insulation layer 60 and at least partially overlapping the element 30 wherein a predetermined range of the semiconductor layer 10 located on the outside of vertical extension of the short side of the electrode pad 62 is an element keep-out region 12.
Description
Technical field
The present invention relates to semiconductor device.
Background technology
In the past, when semiconductor device such as the below of pad (laying) configuration MOS transistor because the stress in when welding etc. tend to damage the characteristic of semiconductor device such as MOS transistor, on semiconductor chip, on vertical view, see and separate the district that pad formation portion is set and is formed with semiconductor device.Becoming more meticulous and also configuring semiconductor device of the integrated and below that urgently is desirably in pad along with semiconductor chip in recent years.Open an example that discloses such technology in the 2002-319587 communique the spy.
Patent document 1: the spy opens the 2002-319587 communique.
Summary of the invention
The object of the present invention is to provide and a kind of semiconductor device and the high semiconductor device of reliability can be set below electronic pads.
(1) semiconductor device of the present invention comprises: have device and form the district and be arranged on the semiconductor layer that this device forms district's device separation region on every side; Be formed on described device and form the interior device in district; Be arranged on the interlayer insulating film above the described semiconductor layer; And the electronic pads that on vertical view, repeats with a described device part, the top and flat shape that this electronic pads is arranged on described interlayer insulating film is the rectangular electronic pads with minor face and long limit; Wherein, in described semiconductor layer, the vertical lower of the described minor face of described electronic pads prescribed limit toward the outer side is the device exclusion area.
In semiconductor device of the present invention, at least a portion of semiconductor layer that is positioned at the below of electronic pads is that device forms the district, in the regulation district of locating toward the outer side from the electronic pads minor face device exclusion area is set.In the regulation district of locating toward the outer side from the minor face of electronic pads because of form electronic pads be easy to generate strain from and cause stress easily.Therefore on being configured in this interlayer insulating film above district, be easy to generate crackle, the occasion of semiconductor device such as MOS transistor for example is set in this district, just may become a reason of the deterioration in characteristics that makes MOS transistor.Therefore, in semiconductor device of the present invention, be by the district of this regulation is avoided described problem as the device exclusion area, and be positioned at electronic pads below semiconductor layer on device be set form the district, even the also no problem local configuring semiconductor device of semiconductor device is set under electronic pads.That is to say, according to the present invention, below electronic pads, even place that semiconductor device also can not exert an influence to reliability configuring semiconductor device energetically is set, and on the other hand, thinking that the place of infringement reliability does not dispose semiconductor device, can provide whereby and try hard to improve the semiconductor device that becomes more meticulous with reliability.
In the present invention, so-called device region is meant the district of various devices such as forming MIS transistor, diode and resistance.In addition, in the present invention, when mentioning the specific B layer (hereinafter referred to as " B layer ") that is arranged on above the specific A layer (hereinafter referred to as " A layer "), the top occasion that the occasion of B layer directly is set and the B layer is set across other layer on the A layer that is included in the A layer.
The semiconductor device relevant with the present invention can adopt following embodiment.
(2) in the semiconductor device relevant with the present invention, described device exclusion area can be the scope that has the distance of 1.0 μ m to 2.5 μ m from the vertical lower of the described minor face of described electronic pads toward the outer side.
(3) in semiconductor device of the present invention, comprise passivation layer, described passivation layer be positioned at described electronic pads above, has the opening that at least a portion of making this electronic pads is exposed, wherein, described device exclusion area can be the scope that has the distance of the thickness that is equivalent to described passivation layer from the vertical lower of the described minor face of described electronic pads toward the outer side.
(4) in the semiconductor device relevant, can comprise the lug boss that is arranged on the described opening with the present invention.
(5) semiconductor device relevant with the present invention comprises: have device and form the district and be arranged on the semiconductor layer that this device forms the device separation region around the district; Be formed on described device and form the interior device in district; Be arranged on the interlayer insulating film above the described semiconductor layer; And the electronic pads that is arranged on the top of described interlayer insulating film and on vertical view, repeats with described device; Wherein, in described semiconductor layer, be the device exclusion area from the vertical lower prescribed limit toward the outer side of the end of described electronic pads.
In the semiconductor device relevant with the present invention, the semiconductor layer that is positioned at the electronic pads below is a device region, in the regulation district toward the outer side, end from electronic pads the exclusion area is set.That is to say, according to the present invention, has identical advantage with the semiconductor device of described record, below electronic pads, even place that semiconductor device also can not exert an influence to reliability configuring semiconductor device energetically is being set, and thinking have the place of infringement reliability not dispose semiconductor device, just can provide the semiconductor device of trying hard to improve the degree of becoming more meticulous and reliability whereby.
(6) in the semiconductor device relevant with the present invention, described device exclusion area is the scope that has 1.0 μ m to 2.5 μ m distances from the vertical lower of described electrode tip toward the outer side.
(7) in the semiconductor device relevant with the present invention, also comprise passivation layer, described passivation layer be positioned at described electronic pads above, have the opening that at least a portion of making this electronic pads is exposed; Wherein, described device exclusion area can be the scope that has the distance of the thickness that is equivalent to described passivation layer from the below of the end of described electronic pads toward the outer side.
(8) in the semiconductor device relevant, can also comprise the lug boss that is arranged on described opening with the present invention.
(9) in the semiconductor device relevant with the present invention, described device can be a transistor.
(10) in the semiconductor device relevant with the present invention, described device exclusion area can be the exclusion area of low voltage drive transistor (low voltage excitation transistor).
(11) in the semiconductor device relevant, can in described device exclusion area, high voltage transistor be set with the present invention.
Description of drawings
Fig. 1 is the schematic diagram of the explanation semiconductor device relevant with first embodiment.
Fig. 2 is the schematic diagram of the explanation semiconductor device relevant with first embodiment.
Fig. 3 is the schematic diagram of the explanation semiconductor device relevant with first embodiment.
Fig. 4 is the schematic diagram of the explanation semiconductor device relevant with second embodiment.
Fig. 5 is explanation and the schematic diagram of the semiconductor device of the variation of first and second embodiment.
Fig. 6 is explanation and the schematic diagram of the semiconductor device of the variation of first and second embodiment.
Embodiment
An example of embodiments of the invention is described with reference to the accompanying drawings.
1. first embodiment
Fig. 1 is the profile of the pattern ground expression semiconductor device relevant with present embodiment, Fig. 2 be pattern be illustrated in the vertical view of the relation of the shape of electronic pads in the semiconductor device relevant and exclusion area with present embodiment.Fig. 3 is used to illustrate that device forms the vertical view of district 10A, and in addition, the section of Fig. 1 is the profile along the X-X line of Fig. 2.
As shown in Figure 1, relevant with present embodiment semiconductor device has semiconductor layer 10.Can use the single crystal silicon substrate as semiconductor layer 10, this semiconductor layer (SOI:Siliconon Insulator: Silicon-On-Insulator) be arranged on the insulating barrier, and this semiconductor layer is silicon layer, germanium layer, and the substrate of germanium-silicon layer.
Device isolation insulating barrier 20 is set on semiconductor layer 10.Device isolation insulating barrier 20 can pass through STI method, LOCOS method and half flush type LOCOS method and form.In addition, figure 1 illustrates the device isolation insulating barrier 20 that forms by the STI method.By device isolation insulating barrier 20 is set like this, just can delimits the device that forms device and form district 10A and device exclusion area 12.Device forms district 10A and will be described later, and is arranged on the district of electronic pads below.Device exclusion area 12 is the grey area among Fig. 2, is the zone from the end prescribed limit toward the outer side of electronic pads of semiconductor layer 10, also will describe this district afterwards.In addition, relevant with present embodiment semiconductor device is also distinguished 10B in the arranged outside device formation of device exclusion area 12.
(Metal Insulator Semicondctor: Metal-Insulator-Semi-Conductor) transistor 30 to be arranged on the MIS that the low voltage drive of insulating barrier is not set on the compensating basin on device formation district 10A.And on device formation district 10B, also form district 10A MIS transistor 40 is set similarly with device.MIS transistor 30 comprises: gate insulator 32, be arranged on the gate electrode 34 on the gate insulator 32 and be arranged on impurity range (doped region) 36 on the semiconductor layer 10.Impurity range 36 is as source area or drain region.MIS transistor 40 has same structure with MIS transistor 30, comprises gate insulator 42, gate electrode 44 and impurity range 46, is the transistor that the low voltage drive of insulating barrier is not set on the compensating basin.In addition, it is the district that surrounded by device isolation insulating barrier 20 on vertical view as shown in Figure 3 (district that represents with oblique line) that device among so-called the present invention forms district 10A, also is like this and form on the district 10B at device.
The interlayer insulating film 50 and the interlayer insulating film 60 that on MIS transistor 30,40, are set in turn cover MIS transistor 30,40 and are provided with.Interlayer insulating film 50 and interlayer insulating film 60 can be with known general materials.Setting has the wiring layer 52 of the pattern of regulation on interlayer insulating film 50, is electrically connected by the impurity range 36 of contact layer 54 with wiring layer 52 and MIS transistor 30.
The semiconductor device relevant with present embodiment also has passivation layer 70 as shown in Figure 1, and formation makes the opening 72 that at least a portion of electronic pads 62 is exposed on passivation layer 70.Opening 72 also can only make the central area of electronic pads 62 expose as depicted in figs. 1 and 2.That is, can form passivation layer 70 for the circumference of coated electrode pad 62.Passivation layer can be used for example SiO
2, formation such as SiN, polyimide resin.In addition, in the semiconductor device relevant, when speaking of electronic pads the district that comprises that opening 72 is provided with present embodiment, and the width district also broader than wiring portion.
The semiconductor device relevant with present embodiment is provided with lug boss 80 at least in opening 72.Promptly lug boss 80 is set on the face in exposing of electronic pads 62.In the semiconductor device relevant, illustrate and form lug boss 80 so that it reaches the situation on the passivation layer 70 with present embodiment.Lug boss 80 can form one or more layers, and can form by metals such as gold, nickel or copper, and the profile of lug boss is not particularly limited, also can be to form rectangle (containing square and rectangle) or circle.The profile of lug boss 80 also can be littler than electronic pads 62 in addition.At this moment lug boss 80 also can be only with the overlapping district of electronic pads 62 in form.
In addition, though do not illustrate, also can on the orlop of lug boss 80, the barrier layer be set.The barrier layer is to be used to prevent both diffusion usefulness of electronic pads 62 and lug boss 80.The barrier layer can form one or more layers.Also can form the barrier layer by sputtering method.In addition, the barrier layer can also have the function of the connecting airtight property that improves electronic pads 62 and lug boss 80.The barrier layer also can have tungsten titanium (TiW) layer.Under situation about being made of multilayer, the uppermost surface on barrier layer also can be the metal level (for example Au layer) that makes the plating power supply usefulness that lug boss 80 separates out.
The scope of device exclusion area 12 can be used as from the end of electronic pads 62 scope that (with opening 72 opposite sides) toward the outer side has the distance of the thickness that is equivalent to passivation layer 70.For example can be used as the scope that has the distance of 1.0 μ m to 2.5 μ m from the end of electronic pads 62 toward the outer side.It is described to provide against the reasons are as follows of district's scope of 12 like this.
At first, because of being set, electronic pads 62 can on the interlayer insulating film 60 at the place, end of electronic pads 62, cause stress.Then as shown in Figure 1, because of being set, the stress that continues that has been arranged on the lug boss 80 on the electronic pads 62 and will have been caused by the internal stress of lug boss 80 is applied on the interlayer insulating film.Interlayer insulating film 50,60 is subjected to these stress influence, and often cracks from the position (end of electronic pads 62) that produces these stress.Such crackle often reaches undermost interlayer insulating film, and the characteristic that is arranged on the semiconductor device in this district is degenerated.If the MIS transistor for example is set, then can causes the deterioration of gate insulator etc., and cause leakage current.
In addition, passivation layer 70 is not on all identical face of apparent height disposed thereon, and it is poor to produce different ladders along with the difference of electronic pads 62 shapes certainly.Because this ladder is poor, such as mentioned above, for example when carrying out the COF installation, causing strain concentrating easily because of its contact, joint when being arranged on connecting line (lead-in wire) on the film and being connected with lug boss 80, therefore also can become the reason that on interlayer insulating film 50,60, causes crackle, and this ladder difference produces toward the outer side and in the position of the distance with the thickness that roughly is equivalent to passivation layer 70 in the end from electronic pads 62 easily.Here it is will be by considering above-mentioned problem, the reason of the scope of regulation device exclusion area 12.
In the semiconductor device relevant with present embodiment, the semiconductor layer that is positioned at electronic pads 62 belows is that device forms district 10A, in the district that stipulates laterally from the end of electronic pads 62 device exclusion area 12 is set.Thereby, the zone of stipulating laterally from the end of electronic pads 62 is easy to generate stress because being easy to generate strain, so crackle takes place on being configured in this interlayer insulating film 50,60 above device exclusion area 12 easily, the occasion of semiconductor device such as MOS transistor for example is set in this district, may becomes the reason that the characteristic that makes MOS transistor degenerates.Therefore, in the semiconductor device relevant with present embodiment, the problems referred to above just can be avoided in the device exclusion area 12 of the scope by setting this regulation.In addition, the semiconductor layer 10 that is positioned at electronic pads 62 belows is formed district 10A as device, even the also no problem local configuring semiconductor device of semiconductor device is set for 62 times at electronic pads.Promptly, according to present embodiment, below electronic pads, even place that semiconductor device also can not influence reliability configuring semiconductor device energetically is set, and thinking can the infringement reliability the place do not dispose semiconductor device, the semiconductor device that can try hard to become more meticulous and can keep reliability can be provided whereby.
In addition, also handlebar constitutes the occasion of the contact layer of gate electrode 34 as the wiring that is used for for example being connected with MIS transistor 40 with other device, also can be formed on the device exclusion area 12 as the part contact layer of this wiring usefulness.
2. second embodiment
Then the second embodiment of the present invention is described with reference to Fig. 4.Fig. 4 is the profile of the pattern ground expression semiconductor device relevant with second embodiment of the invention.In the semiconductor device relevant with second embodiment, this point that semiconductor device is set in device exclusion area 12 is the semiconductor device different example related with first embodiment.In the following description, just describe with the related semiconductor device dissimilarity of first embodiment.
The semiconductor device relevant with second embodiment has device and forms district 10A and be arranged on its device exclusion area 12 on every side as shown in Figure 4.In the semiconductor device relevant with present embodiment, though not shown in Fig. 4, the semiconductor device related with first embodiment is identical, also forms device in the outside of device exclusion area 12 and forms district 10B.
In the semiconductor device relevant, high voltage bearing MOS transistor is set on device exclusion area 12 with present embodiment.Specifically, be to be provided with to have the MOS transistor 100 of LOCOS collocation structure.MOS transistor 100 is arranged in the semiconductor layer 10, and has: the compensation insulating barrier 22 of the electric field that is used to decay; Be arranged on the gate insulator 102 on the semiconductor layer 10; Be arranged on the part and the gate electrode 104 on the gate insulator 102 of compensation insulating barrier 22 and be arranged on impurity range 106 on the semiconductor layer in the outside of grid 104 as source area or drain region.Setting is the conduction type same with impurity range 106 below compensation insulating barrier 22, and the low compensated impurity district 108 of doping content.
In the related semiconductor device of present embodiment, the part of MOS transistor 100 inscapes is set on the semiconductor layer 10 of device exclusion area 12.The end of the gate electrode 104 of MOS transistor 100 is arranged on the compensation insulating barrier 22.That is to say that decision is not provided with in device exclusion area 12 end of gate electrode 104 is configured in such structure above the semiconductor 10 across thin insulating barrier, the ground floor of this structure is a conductive layer.At this, the problem when just on device exclusion area 12 the MIS transistor 30 with the structure that is arranged on the device region being set under the situation of supposition describes.MIS transistor 30 is different with MOS transistor 100, and the end with gate electrode 34 is arranged on the structure on the semiconductor layer 10.Therefore, on the semiconductor layer 10 of the position, end of gate electrode 34, be easy to generate stress.As described in first embodiment, be easy to generate crackle on the interlayer insulating film 50,60 on device exclusion area 12, thereby cause the deterioration of film easily.This influence often has influence on the end of the gate electrode 34 of stress generation always, can cause the deterioration of gate insulator 32.And must cause leakage current in the MIS transistor.
In addition, according to the semiconductor device relevant with second embodiment, because the end of configuration gate electrode 104 on the compensation insulating barrier 22 on the device exclusion area 12, thus can not make semiconductor layer 10 produce stress as described above, deterioration that can suppressor grid insulating barrier 102.Therefore, so long as have the semiconductor device of regulation structure, not only can in the device below being arranged on electronic pads 62 forms district 10A, dispose this semiconductor device, can also in device exclusion area 12, dispose this device, thereby can further improve the level of becoming more meticulous.So just can make from the number increase of the semiconductor chip of a semiconductor wafer acquisition, and can reduce manufacturing cost.
In addition, though be that the situation that MIS transistor 100 just is set in device exclusion area 12 describes in Fig. 4, not limited by this, also comprise the situation of the part of the formation that MOS transistor 100 is set, in the case, also can be the transistor of the MOS of one-sided collocation structure.
Variation
Variation below with reference to Fig. 5 explanation semiconductor device relevant with second embodiment with first embodiment.The feature of this variation is the rectangular shape this point that being shaped as of lug boss 80 has minor face and long limit, and Fig. 5 is the vertical view of the position relation of pattern ground expression electronic pads 62 and device exclusion area 12.In addition, in the following description, be only just to describe with the dissimilarity of the related semiconductor device of first embodiment and second embodiment.
At the semiconductor device relevant lug boss 80 is set on the opening on the electronic pads 62 72 as shown in Figure 1 and Figure 4 with this variation.In this variation, electronic pads 62 has rectangular shape.And opening 72 is set on the part on the electronic pads 62.Lug boss 80 is set on opening 72.Lug boss 80 has the figure littler than electronic pads 62, and preferably as shown in Figure 5, during from vertical view, this lug boss 80 preferably is arranged on the inboard of electronic pads.In this variation, device exclusion area 12 is arranged on from the zone toward the outer side, minor face end of electronic pads 62.According to this mode, for example when installing with the TAB technology, the bearing of trend that is arranged on the connecting line (lead-in wire) 13 on the film of being made up of polyimide resin is during along the direction on the long limit of electronic pads 62, and following advantage is arranged.At this moment electronic pads 62 is in the state to the bearing of trend tension of connecting line, and particularly the short brink at electronic pads 62 produces strain.Therefore, as mentioned above, cause especially easily in the end of the minor face of electronic pads 62 the such problem of crackle takes place on interlayer insulating film 50,60.In this variation,, can forbid really causing that the low place of reliability is provided with semiconductor device by device exclusion area 12 being arranged on the short brink of electronic pads 62.In addition, because on the semiconductor layer below the long limit of electronic pads 62, device exclusion area 12 is not set,, can provide the degree of becoming more meticulous high semiconductor device so can on the semiconductor layer below the long limit of electronic pads 62, semiconductor device be set.
Particularly as shown in Figure 6, realizing on the semiconductor chip 200 that becomes more meticulous opening 72 and lug boss 80 being made rectangle, be the formation that a lot of openings 72 are set, this presses for often.In this variation,, become more meticulous and the high semiconductor device of reliability by device exclusion area 12 being set in suitable district, also can providing even have the semiconductor device of the electronic pads 62 (lug boss 80) of such rectangular shape.
In addition, though in the above-described embodiment, be to illustrate the situation that constitutes and between this is two-layer, be provided with one deck wiring layer 52 by two-layer interlayer insulating film 50,60, but not limited by this, also can be stacked more than three layers the interlayer insulating film and having of (more than or equal to three layers) structure with the corresponding wiring layer of the number of plies of this interlayer insulating film is set between all interlayer insulating films.
The present invention is not subjected to the qualification of the above embodiments, also has various possible distortion.For example the present invention comprises the formation identical in fact with explanation formation in an embodiment (for example, identical formations such as function, method and result, perhaps purpose and the formation that comes to the same thing).In addition, the present invention comprises the formation of the nonessential part of the formation of replacing and illustrating in an embodiment.The present invention also comprises the formation of the same action effect of formation that produces and illustrate in an embodiment or can reach the formation of same purpose.The present invention also comprises the formation of additional known technology on the formation that illustrates in an embodiment.
Description of reference numerals
10 semiconductor layer 10A, 10B device form the district
12 device exclusion areas, 20 device isolation insulating barriers
22 compensation insulating barriers 30,40 MIS transistors
32,42 gate insulators 34,44 gate electrodes
36,46 impurity ranges, 50 interlayer insulating films
52 wiring layers, 60 interlayer insulating films
62 electronic padses, 62 electronic padses
70 passivation layers, 72 openings
80 lug bosses, 100 MIS transistors
102 gate insulators, 104 gate electrodes
106 impurity ranges, 108 compensated impurity districts
Claims (9)
1. semiconductor device is characterized in that comprising:
Semiconductor layer has device and forms the district and be arranged on described device formation district device separation region on every side;
Device is formed on described device and forms in the district;
Interlayer insulating film is arranged on above the described semiconductor layer; And
Electronic pads, be arranged on described interlayer insulating film above, and flat shape is the rectangle with minor face and long limit, in the above electronic pads of vertical view and the repetition of a described device part;
Wherein, in described semiconductor layer, be the device exclusion area from the vertical lower prescribed limit toward the outer side of the described minor face of described electronic pads,
Described device exclusion area is the scope that has 1.0 μ m to 2.5 μ m distances from the vertical lower of the described minor face of described electronic pads towards the outside.
2. semiconductor device is characterized in that comprising:
Semiconductor layer has device and forms the district and be arranged on described device formation district device separation region on every side;
Device is formed on described device and forms in the district;
Interlayer insulating film is arranged on above the described semiconductor layer; And
Electronic pads, be arranged on described interlayer insulating film above, and flat shape is the rectangle with minor face and long limit, in the above electronic pads of vertical view and the repetition of a described device part;
Wherein, in described semiconductor layer, be the device exclusion area from the vertical lower prescribed limit toward the outer side of the described minor face of described electronic pads,
Described semiconductor device also comprises:
Passivation layer, described passivation layer be positioned at described electronic pads above, have the opening that at least a portion of making described electronic pads is exposed,
Wherein, described device exclusion area is the scope that has the distance of the thickness that is equivalent to described passivation layer from the vertical lower of the described minor face of described electronic pads toward the outer side.
3. semiconductor device according to claim 2 is characterized in that also comprising: lug boss, described lug boss is arranged on the described opening.
4. semiconductor device is characterized in that comprising:
Semiconductor layer has device and forms the district and be arranged on described device formation district device separation region on every side;
Device is formed on described device and forms in the district;
Interlayer insulating film, be arranged on described semiconductor layer above; And
Electronic pads, be arranged on described interlayer insulating film above, and on vertical view, repeat with described device;
Wherein, in described semiconductor layer, be the device exclusion area from the vertical lower prescribed limit toward the outer side of the end of described electronic pads,
Described device exclusion area is the scope that has 1.0 μ m to 2.5 μ m distances from the vertical lower of described electrode tip toward the outer side.
5. semiconductor device is characterized in that comprising:
Semiconductor layer has device and forms the district and be arranged on described device formation district device separation region on every side;
Device is formed on described device and forms in the district;
Interlayer insulating film, be arranged on described semiconductor layer above; And
Electronic pads, be arranged on described interlayer insulating film above, and on vertical view, repeat with described device;
Wherein, in described semiconductor layer, be the device exclusion area from the vertical lower prescribed limit toward the outer side of the end of described electronic pads,
Described semiconductor device also comprises:
Passivation layer, described passivation layer be positioned at described electronic pads above, have the opening that at least a portion of making this electronic pads is exposed;
Wherein, described device exclusion area is the scope that has the distance of the thickness that is equivalent to described passivation layer from the below of the end of described electronic pads toward the outer side.
6. semiconductor device according to claim 5 is characterized in that also comprising: lug boss, described lug boss is arranged on the described opening.
7. according to any one described semiconductor device in the claim 1 to 6, it is characterized in that: described device is a transistor.
8. according to any one described semiconductor device in the claim 1 to 6, it is characterized in that: described device exclusion area is the transistorized exclusion area of low voltage drive.
9. semiconductor device according to claim 8 is characterized in that: in described device exclusion area high voltage transistor is set.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2005197926 | 2005-07-06 | ||
| JP2005197926 | 2005-07-06 | ||
| JP2006074731 | 2006-03-17 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1893075A CN1893075A (en) | 2007-01-10 |
| CN100499125C true CN100499125C (en) | 2009-06-10 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 200610090383 Expired - Fee Related CN100499125C (en) | 2005-07-06 | 2006-07-05 | Semiconductor device |
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| Country | Link |
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| JP (1) | JP5477599B2 (en) |
| CN (1) | CN100499125C (en) |
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| US20080173904A1 (en) * | 2007-01-22 | 2008-07-24 | Taiwan Semiconductor Manufacturing Co., Ltd. | CMOS image sensors with a bonding pad and methods of forming the same |
| JP6219695B2 (en) * | 2013-11-27 | 2017-10-25 | 京セラ株式会社 | WIRING BOARD AND SEMICONDUCTOR DEVICE HAVING THE SAME |
| EP3155666B1 (en) | 2014-06-16 | 2021-05-12 | Intel IP Corporation | Metal on both sides with clock gated power and signal routing underneath |
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| JP4232584B2 (en) * | 2002-10-15 | 2009-03-04 | 株式会社デンソー | Semiconductor device |
| JP2004207509A (en) * | 2002-12-25 | 2004-07-22 | Matsushita Electric Ind Co Ltd | Semiconductor device and manufacturing method thereof |
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2006
- 2006-07-05 CN CN 200610090383 patent/CN100499125C/en not_active Expired - Fee Related
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| JP5477599B2 (en) | 2014-04-23 |
| JP2012235160A (en) | 2012-11-29 |
| CN1893075A (en) | 2007-01-10 |
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