CN100484122C - Clock signal converting circuit between V35 interface and time division multiplex interface - Google Patents
Clock signal converting circuit between V35 interface and time division multiplex interface Download PDFInfo
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- CN100484122C CN100484122C CNB031213502A CN03121350A CN100484122C CN 100484122 C CN100484122 C CN 100484122C CN B031213502 A CNB031213502 A CN B031213502A CN 03121350 A CN03121350 A CN 03121350A CN 100484122 C CN100484122 C CN 100484122C
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Abstract
A clock signal transfer circuit of V35 interface and CDM interface includes a frequency division phase-locked locked loop, a V35 clock selection module, a frequency division unit and a frequency multiplication phase-locked loop, among which, the frequency division phase-locked loop inputs the V35 interface working clock signals phase-locked and frequency-divided by clock source and provided by the opposite device into the V35 clock selective module, the output signal of which is sent to the frequency division unit, the first signal from it is sent to the multiplied phase-locked loop to output a CDM interface working clock signal, and the second frequency division signal from the frequency division unit is the CDM interface synchronous positioning clock signal. The local device can use the clocks provided by the local clock source or opposite clock source.
Description
Technical field
The present invention relates to the telecommunications access technology, specifically, relate to the conversion circuit of clock signal between V35 interface and the time division multiplexing interface.
Background technology
In the telecommunications access device, the V35 interface is widely used as a kind of general external interface technology.At device interior, the V35 interface module is communicated by letter with Service Processing Module and is used the Time Division Multiplexing bus communication usually.TDM is the data flow of 2.048M, is divided into 32 time slots, and each time slot is corresponding to the data of 64K.V35 is the data flow of N*64K, N=(1-32), i.e. 64K to 2.048M, 1-32 the time slot of corresponding TDM respectively.Therefore, need carry out the clock of V35 interface and TDM interface or the conversion of data.
Referring to shown in Figure 1, Fig. 1 is the V35 interface and the TDM interface conversion schematic diagram of prior art.When TDM when the V35 interface sends data, TDM is undertaken buffer memory to the transmission double-port random memory access (DPRAM) 101 that data write field programmable gate array (FPGA) inside by being used for synchronized positioning clock 8K and work clock 2.048M, and each cycle, (8K) write the data of several slots.The work clock N*64K that the V35 interface is selected with V35 clock selection module 103 reads out data from sending DPRAM 101, deliver to opposite equip. through after the level transferring chip 106.With send just on the contrary, the data that the N*64K of the work clock that the V35 interface is selected with V35 clock selection module 103 brings opposite equip. write reception DPRAM 102.TDM reads out from the reception DPRAM 102 of FPGA inside by being used for synchronized positioning clock 8K and work clock 2.048M, and each cycle is read the data of several slots.
Among the figure, the conversion of the clock of prior art is as follows: the 2.048M clock of local terminal equipment produces the N*64K clock through frequency dividing phase-locked loop module 104 backs, and gives V35 clock selection module 103.The N*64K clock that the V35 clock selection module is selected to produce from the N*64K clock of V35 interface or from phase-locked loop according to the veneer mode of operation is as the reception of DPRAM 102 and the tranmitting data register of DPRAM 101.Wherein, be actually opposite equip. from the clock of V35 interface the tranmitting data register of local terminal equipment is directly returned, the clock source of really not using the opposite end to establish to provide.The 2.048M clock of local terminal equipment produces 8K synchronized positioning clock through frequency division module 105, as the send-receive clock of TDM interface.
Because all clocks of V35 interface and TDM interface conversion must be produced by same clock source, could guarantee that the data volume of each period T DM transmitting-receiving is consistent with V35 transceive data amount, thereby guarantee that conversion is normal.And can see from the conversion of top clock, owing to can not convert N*64K clock to TDM work clock 2.048M from opposite equip., the 2.048M clock of TDM interface can only be supplied with by local terminal equipment, the clock that can not use clock source, opposite end to provide, so can only use the clock source of local terminal equipment, just can only be operated under data transmission set (DCE) pattern.
Summary of the invention
The object of the present invention is to provide the conversion circuit of clock signal between a kind of V35 interface and the time division multiplexing interface, so that the clock that local terminal equipment both can use local terminal equipment clock source to provide, the clock that also can use opposite equip. clock source to provide.
The present invention is achieved through the following technical solutions:
Conversion circuit of clock signal between a kind of V35 interface and the time division multiplexing interface, comprise frequency dividing phase-locked loop 104, V35 clock selection module 103, wherein, the V35 interface work clock signal that will be obtained from the clock source phase-locked frequency demultiplication of 104 pairs of local terminal equipment of frequency dividing phase-locked loop, and input to V35 clock selection module 103 respectively from the V35 interface work clock signal that opposite equip. provides, this conversion circuit of clock signal also comprises frequency unit 100 and frequency multiplication phase-locked loop 108, the output signal of described V35 clock selection module 103 is delivered to frequency unit 100, first fractional frequency signal of frequency unit 100 frequency divisions output is delivered to frequency multiplication phase-locked loop 108, frequency multiplication phase-locked loop 108 is with the phase-locked back output of this first fractional frequency signal frequency multiplication time division multiplexing interface work clock signal, and second fractional frequency signal of frequency unit 100 outputs is a time division multiplexing interface synchronized positioning clock signal.
Preferably, described frequency unit 100 is a frequency division module 109, and first fractional frequency signal of its output and time division multiplexing interface synchronized positioning clock signal frequency are identical or different.
Preferably, described frequency unit also comprises three frequency division module 110, clock signal from frequency multiplication phase-locked loop 108 inputs to this frequency division module, this frequency division module is exported fractional frequency signal feedback and is inputed to frequency multiplication phase-locked loop 108, and the frequency of this fractional frequency signal is the required frequencies of frequency multiplication phase-locked loop 108 feedback signals.
Preferably, the frequency of described first fractional frequency signal is a time division multiplexing interface synchronized positioning clock signal frequency.
The present invention also provides the conversion circuit of clock signal between a kind of V35 interface and the time division multiplexing interface, comprise frequency dividing phase-locked loop (104), V35 clock selection module (103), wherein, the V35 interface work clock signal that will be obtained the clock source phase-locked frequency demultiplication of local terminal equipment from frequency dividing phase-locked loop (104), and input to V35 clock selection module (103) respectively from the V35 interface work clock signal that opposite equip. provides, this conversion circuit of clock signal also comprises frequency unit (100) and frequency multiplication phase-locked loop (108), described frequency unit (100) comprises first frequency division module (107) and second frequency division module (105), first frequency division module (107) will be first fractional frequency signal from the output signal frequency division of V35 clock selection module (103), and input to frequency multiplication phase-locked loop (108); Second frequency division module (105) will be the output of time division multiplexing interface synchronized positioning clock signal from the clock signal frequency division of frequency multiplication phase-locked loop (108).
Preferably, the frequency of described first fractional frequency signal is a time division multiplexing interface synchronized positioning clock signal frequency.
Preferably, described frequency unit also comprises three frequency division module (110), clock signal from frequency multiplication phase-locked loop (108) inputs to this frequency division module, this frequency division module is exported fractional frequency signal feedback and is inputed to frequency multiplication phase-locked loop (108), and the frequency of this fractional frequency signal is the required frequency of frequency multiplication phase-locked loop (108) feedback control signal.
Preferably, the fractional frequency signal of described second frequency division module (105) output also feeds back and inputs to described frequency multiplication phase-locked loop (108).The fractional frequency signal of described second frequency division module 105 outputs also feeds back and inputs to described frequency multiplication phase-locked loop 108.
The present invention is by setting up frequency unit 100, with V35 interface work clock frequency division is a fixing fractional frequency signal, with this fixedly fractional frequency signal to carry out frequency multiplication by frequency multiplication phase-locked loop 108 phase-locked, obtain TDM interface work clock, obtain TDM interface synchronized positioning clock by the output of frequency unit 100 frequency divisions, solved the problem that converts the TDM work clock from the V35 interface work clock of opposite equip. to, thereby make the clock that circuit for switching between two clocks both can use local terminal equipment clock source to provide, the clock that also can use opposite equip. clock source to provide, therefore local terminal equipment both can be operated under the DCE pattern, also can be operated under the data terminal equipment (DTE) pattern, make the access device that uses the V35 interface use more flexible, convenient.The present invention has done simple improvement on the basis of existing clock circuit, with low cost.
Description of drawings
Fig. 1 is the V35 interface and the TDM interface conversion schematic diagram of prior art;
Fig. 2 is V35 interface of the present invention and TDM interface conversion circuit schematic diagram;
Fig. 3 is the V35 interface and the TDM interface conversion circuit schematic diagram of the embodiment of the invention 1;
Fig. 4 is the V35 interface and the TDM interface conversion circuit schematic diagram of the embodiment of the invention 2.
Embodiment
Because existing circuit for switching between two clocks can not convert the clock from opposite equip. to the work clock of TDM interface, at this defective, at the inner frequency division module that increases of FPGA, to carry out frequency division from the V35 interface work clock N*64K that opposite equip. provides, at frequency multiplication phase-locked loop of the outside increase of FPGA, generate the work clock of TDM interface simultaneously to utilize described frequency division module.
Referring to shown in Figure 2, Fig. 2 is V35 interface of the present invention and TDM interface conversion circuit general illustration.The TDM interface is identical with the prior art process with the transfer process of V35 interface data, is to change by the DPRAM buffer all, and the work clock of TDM interface, synchronized positioning clock and V35 interface work clock are delivered to DPRAM respectively.The acquisition of above-mentioned clock signal is such: from the V35 interface work clock of frequency dividing phase-locked loop module 104 output, and input to V35 clock selection module 103 respectively from the V35 interface work clock that opposite equip. provides; The clock signal of V35 clock selection module 103 outputs is delivered to frequency unit 100 and is carried out frequency division, and first fractional frequency signal that this frequency unit 100 will be exported inputs to frequency multiplication phase-locked loop 108, produces TDM work clock signal by this frequency multiplication phase-locked loop 108 and exports respectively; And the frequency of second fractional frequency signal of frequency unit output is a TDM synchronized positioning clock signal frequency.
Embodiment 1:
Referring to shown in Figure 3, Fig. 3 is the V35 interface and the TDM interface conversion circuit schematic diagram of the embodiment of the invention 1.Frequency unit 100 is a frequency division module 109, this frequency division module 109 can be a TDM synchronized positioning clock signal with the V35 interface work clock N*64K frequency division from 103 outputs of V35 clock selection module directly, the first fractional frequency signal frequency that is frequency division module 109 outputs is identical with the second fractional frequency signal frequency, be TDM synchronized positioning clock signal frequency, the frequency multiplication phase-locked loop with above-mentioned fractional frequency signal carry out frequency multiplication phase-locked after, generate TDM interface work clock signal.
Certainly, the first fractional frequency signal frequency and the second fractional frequency signal frequency of frequency division module 109 outputs also can be inequality, as long as the first fractional frequency signal frequency is the approximate number of time division multiplexing interface working clock frequency.
Embodiment 2:
Referring to shown in Figure 4, Fig. 4 is the V35 interface and the TDM interface conversion circuit schematic diagram of the embodiment of the invention 2.Frequency unit 100 is first frequency division module 107 and second frequency division module 105, wherein, first frequency division module 107 will be that first fractional frequency signal inputs to frequency multiplication phase-locked loop 108 from the signal frequency split of V35 clock selection module 103, be consistent from same clock source and phase place of the synchronized positioning clock that guarantees the TDM interface and work clock, avoid the shake of the fractional frequency signal of first frequency division module, 107 outputs, the TDM interface work clock of frequency multiplication phase-locked loop module 108 outputs is delivered to second frequency division module 105, export second fractional frequency signal by second frequency division module, 105 frequency divisions, the frequency of this fractional frequency signal is the synchronized positioning clock frequency, and exports DPRAM to.
For making frequency multiplication phase-locked loop 108 locking phases more stable, also can set up three frequency division module 110, in order to generate the feedback signal of frequency multiplication phase-locked loop 108, this three frequency division module 110 will be carried out frequency division from the clock signal of frequency multiplication phase-locked loop 108 outputs, frequency division output and feedback input to frequency multiplication phase-locked loop 108, and the frequency of this fractional frequency signal is specifically determined by phase-locked loop.In addition, for the frequency of the fractional frequency signal that makes frequency division module output identical as far as possible, reduce the complexity of FPGA circuit, preferably, the first fractional frequency signal frequency of first frequency division module, 107 frequency divisions output is identical with the second fractional frequency signal frequency of second frequency division module, 105 frequency divisions output, is TDM synchronized positioning clock signal frequency, and, output second fractional frequency signal of second frequency division module 105 feeds back to frequency multiplication phase-locked loop 108, shown in Fig. 4 dotted line, at this moment can not need the three frequency division module.
From the foregoing description as seen, because the V35 interface work clock from V35 clock selection module 103 can be the clock that local terminal equipment clock source produces, it also can be clock from opposite equip., thereby realized to guarantee that TDM interface work clock is identical with the clock source of V35 interface work clock to the work clock and the synchronized positioning clock that convert the TDM interface from the clock of opposite equip. to.
The above only is preferred embodiment of the present invention, and in order to restriction the present invention, for example, described first fractional frequency signal can not be the fractional frequency signal of other frequencies, as long as this fractional frequency signal can frequency multiplication be the TDM work clock.
Claims (8)
1, the conversion circuit of clock signal between a kind of V35 interface and the time division multiplexing interface, comprise frequency dividing phase-locked loop (104), V35 clock selection module (103), wherein, the V35 interface work clock signal that will be obtained the clock source phase-locked frequency demultiplication of local terminal equipment from frequency dividing phase-locked loop (104), and input to V35 clock selection module (103) respectively from the V35 interface work clock signal that opposite equip. provides, it is characterized in that
This conversion circuit of clock signal also comprises frequency unit (100) and frequency multiplication phase-locked loop (108), the output signal of described V35 clock selection module (103) inputs to frequency unit (100), first fractional frequency signal of frequency unit (100) frequency division output inputs to frequency multiplication phase-locked loop (108), frequency multiplication phase-locked loop (108) output time division multiplexing interface work clock signal, second fractional frequency signal of frequency unit (100) output is a time division multiplexing interface synchronized positioning clock signal.
2, conversion circuit of clock signal according to claim 1 is characterized in that, described frequency unit (100) is a frequency division module (109).
3, conversion circuit of clock signal according to claim 1 and 2 is characterized in that, the frequency of described first fractional frequency signal is a time division multiplexing interface synchronized positioning clock signal frequency.
4, conversion circuit of clock signal according to claim 1 and 2, it is characterized in that, described frequency unit also comprises three frequency division module (110), clock signal from frequency multiplication phase-locked loop (108) inputs to this frequency division module, this frequency division module is exported fractional frequency signal feedback and is inputed to frequency multiplication phase-locked loop (108), and the frequency of this fractional frequency signal is the required frequency of frequency multiplication phase-locked loop (108) feedback control signal.
5, the conversion circuit of clock signal between a kind of V35 interface and the time division multiplexing interface, comprise frequency dividing phase-locked loop (104), V35 clock selection module (103), wherein, the V35 interface work clock signal that will be obtained the clock source phase-locked frequency demultiplication of local terminal equipment from frequency dividing phase-locked loop (104), and input to V35 clock selection module (103) respectively from the V35 interface work clock signal that opposite equip. provides, it is characterized in that
This conversion circuit of clock signal also comprises frequency unit (100) and frequency multiplication phase-locked loop (108), described frequency unit (100) comprises first frequency division module (107) and second frequency division module (105), first frequency division module (107) will be first fractional frequency signal from the output signal frequency division of V35 clock selection module (103), and input to frequency multiplication phase-locked loop (108); Second frequency division module (105) will be the output of time division multiplexing interface synchronized positioning clock signal from the clock signal frequency division of frequency multiplication phase-locked loop (108).
6, conversion circuit of clock signal according to claim 5 is characterized in that, the frequency of described first fractional frequency signal is a time division multiplexing interface synchronized positioning clock signal frequency.
7, conversion circuit of clock signal according to claim 5, it is characterized in that, described frequency unit also comprises three frequency division module (110), clock signal from frequency multiplication phase-locked loop (108) inputs to this frequency division module, this frequency division module is exported fractional frequency signal feedback and is inputed to frequency multiplication phase-locked loop (108), and the frequency of this fractional frequency signal is the required frequency of frequency multiplication phase-locked loop (108) feedback control signal.
8, conversion circuit of clock signal according to claim 5 is characterized in that, the fractional frequency signal of described second frequency division module (105) output also feeds back and inputs to described frequency multiplication phase-locked loop (108).
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| Application Number | Priority Date | Filing Date | Title |
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| CNB031213502A CN100484122C (en) | 2003-03-26 | 2003-03-26 | Clock signal converting circuit between V35 interface and time division multiplex interface |
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| CNB031213502A CN100484122C (en) | 2003-03-26 | 2003-03-26 | Clock signal converting circuit between V35 interface and time division multiplex interface |
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| CN1533112A CN1533112A (en) | 2004-09-29 |
| CN100484122C true CN100484122C (en) | 2009-04-29 |
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Families Citing this family (7)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101159535B (en) * | 2007-10-26 | 2010-06-02 | 中兴通讯股份有限公司 | Clock signal regulating device and method thereof |
| CN101188600B (en) * | 2007-12-20 | 2010-06-23 | 烽火通信科技股份有限公司 | A system and method for realizing mutual conversion between the single-bit high-speed user line and High-Way |
| CN101710858A (en) * | 2009-11-23 | 2010-05-19 | 中兴通讯股份有限公司 | Method for selecting clock source and data communication equipment |
| CN101859395A (en) * | 2010-05-14 | 2010-10-13 | 中兴通讯股份有限公司 | Information transmission realization method and system, main control equipment and intelligent card |
| CN108696716A (en) * | 2017-04-07 | 2018-10-23 | 上海峰宁信息科技股份有限公司 | A kind of timing reconstruction processing method and module for data image signal |
| CN109818624B (en) * | 2019-01-29 | 2023-06-02 | 成都德芯数字科技股份有限公司 | Signal processing method and device |
| WO2022198604A1 (en) * | 2021-03-25 | 2022-09-29 | 华为技术有限公司 | Multi-chip apparatus and electronic device |
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