CN100476673C - Electric power bias circuit with negative feedback - Google Patents

Abstract

The invention relates to electrical source biasing circuit with negative feedback. It includes biasing generating circuit, mirror image branch circuit, feedback branch circuit, current output branch circuit. The biasing generating circuit is formed by electrical source I1, I2, NOMS tube n1, n2, used to generate bias current. The mirror image branch circuit is formed by PMOS tube p1 and NMOS tube n3, used to image the current to output branch circuit. The feedback branch circuit is formed by electrical source I3, equivalent switch, used to generate current feedback quantity, adjust bias current. The current output branch circuit is formed by PMOS tube p5, used to output stable bias current. The invention fixes the indifferent bias on the fixed value, can stabilize output bias current, and reduce source voltage sensitivity better compared with the existing current bias circuit. It inducts negative feedback, makes output bias current have higher precision by adjusting current in bias generating circuit.

Description

Power supply bias circuit with negative feedback

Technical Field

The invention belongs to the field of analog integrated circuits, and particularly relates to a power supply bias circuit with negative feedback, which can effectively provide bias current irrelevant to a power supply.

Background

With the development of society, the performance requirements of consumer electronic products are higher and higher. This is also increasingly demanding on the performance of corresponding consumer ICs. The role of the bias circuit is mainly to provide the other working modules with appropriate bias currents for determining the quiescent operating point of the amplifier. High quality bias circuits are often required within integrated circuits to provide a stable bias current. For multi-channel integrated op-amps, even mutual crosstalk between adjacent channels needs to be considered, since a common bias circuit is basically used.

The existing bias circuit irrelevant to the power supply generally adopts a bias circuit irrelevant to the power supply, which is formed by MOS (metal oxide semiconductor) tubes with different sizes, uniquely determines the current value by adding a resistor at a source electrode, and drives the circuit to get rid of a degenerate bias point by additionally adding a starting tube or a starting circuit. This not only has low power independent suppression capability, but also introduces excessive starting tubes.

In the classic book "analog CMOS integrated circuit design", the classic book of pichia radura, published by the seian university of transportation publication 2003, translated by chen gui lu, et al, page 311 teaches a power supply bias circuit, but there is no feedback circuit, so the power supply rejection ratio cannot reach a higher precision, so that it still cannot meet the requirements in high precision applications. And it needs extra starting circuit, and the cost performance of overall structure is not high.

Disclosure of Invention

The invention aims to provide a power supply bias circuit with negative feedback, which has the capability of independent work, occupies small area and can effectively improve the dynamic performance of the circuit.

The invention provides a power supply bias circuit with negative feedback, which comprises a bias generating circuit, a mirror image branch circuit, a feedback branch circuit and a current output branch circuit, wherein the bias generating circuit comprises a bias generating circuit, a current output branch circuit and a feedback control circuit; wherein,

the bias generating circuit is used for generating bias current irrelevant to a power supply, and consists of current sources I1 and I2, NMOS tubes n1 and n2, the NMOS tubes n1 and n2 form a current mirror structure, and the grid width and the width-length ratio of the current mirror structure are equal; one end of the current source I1 is connected with a high level Vcc, and the other end is connected with the drain of n 1; one end of the current source I2 is connected with a high level Vcc, and the other end is connected with the drain electrode of an NMOS tube n2 and is connected into the mirror image branch; the grid electrode of the NMOS transistor n1 is connected with the grid electrode of the NMOS transistor n2 and is connected with the drain electrode of the NMOS transistor n 2; the sources of the NMOS transistors n1 and n2 are grounded; the mirror image branch circuit is used for mirroring the current in the bias generation circuit and mirroring the current to the current output branch circuit; the mirror image branch consists of a PMOS tube p1 and an NMOS tube n 3; the source electrode of the PMOS tube p1 is connected with a high level Vcc, the grid electrode of the PMOS tube p1 is connected with the drain electrode, is connected with the current output branch and is connected to the drain electrode of the NMOS tube n 3; the width-length ratio of the NMOS transistor n3 to the NMOS transistor n2 is equal, the grid electrode of the NMOS transistor n3 is connected with the drain electrode of the NMOS transistor n2, and the source electrode of the NMOS transistor n3 is grounded;

the feedback branch circuit is used for generating current feedback quantity and adjusting the magnitude of bias current in the bias generation circuit; the feedback branch consists of a current source I3 and an equivalent switch SW; one end of the current source I3 is connected with a high level Vcc, the other end is connected with one end of the SW, and the other end of the SW is connected with the drain electrode of an NMOS tube n2 in the bias generating circuit;

the current output branch circuit is used for outputting stable bias current and consists of a PMOS (P-channel metal oxide semiconductor) tube p 2; the source of the PMOS tube p2 is connected with a high level Vcc, the grid is connected with the grid of the PMOS tube p1 in the mirror branch, and the drain outputs a bias current.

The power supply bias circuit stabilizes the bias irrelevant to the power supply at a fixed value, and compared with the existing power supply bias circuit, the structure can better stabilize the output bias current and reduce the sensitivity to the power supply voltage. Compared with the existing bias, the bias generating circuit does not adopt the existing method of equalizing the currents of the left branch and the right branch, current compensation is carried out on the branches of the bias generating circuit through the feedback loop, the currents of the two branches are equal, and meanwhile, the feedback loop can play a role in inhibiting the mismatch of the branches. The invention introduces a negative feedback concept, keeps the current at a certain value by adjusting the current in the bias generating circuit, enhances the stability of the bias current and ensures that the output bias current has higher precision.

Drawings

FIG. 1 is a schematic diagram of a negative feedback bias circuit according to the present invention;

fig. 2 is a circuit diagram of an embodiment of the present invention.

Detailed Description

As shown in fig. 1, the power supply bias circuit with negative feedback of the present invention includes a bias generating circuit 1, a mirror branch 2, a feedback branch 3 and a current output branch 4, and the operation principle of the circuit is explained below.

Mirror currents generated by current sources I1 and I2 respectively flow through an NMOS transistor n1 and an NMOS transistor n2, when currents in the NMOS transistor n1 and the NMOS transistor n2 are equal, SW is switched off, the mirror currents pass through a PMOS transistor p1, and the NMOS transistor n3 is mirrored to the PMOS transistor p2 to be output; when I1 and I2 are unequal, the switch SW is turned on, I3 flows into the NMOS transistor n2, and the current flowing through the NMOS transistor n2 is compensated, so that the current flowing through the NMOS transistor n1 is equal to the current flowing through the NMOS transistor n 2. The compensated current in the NMOS transistor n2 passes through the PMOS transistor p1, and the NMOS transistor n3 is mirrored to the PMOS transistor p2 for output.

As shown in fig. 2, the bias circuit with negative feedback of the present invention includes a bias generating circuit 1, a mirror branch 2, a feedback branch 3 composed of a sampling and adjusting branch, a current output branch 4 and an output control signal 5. Wherein, a part of the feedback branch circuit and a part of the bias generating circuit form a starting circuit. The bias generating circuit 1 is composed of resistors R1 and R2, a PMOS transistor p3, a PMOS transistor p4, an NMOS transistor n1, and an NMOS transistor n 2. One end of R1 is connected with high-level Vcc, the other end is connected with the source electrode of PMOS tube p3, PMOS tube p3 is diode-connected, and the grid electrode and the drain electrode are connected and then connected with the grid electrode of PMOS tube p4 and the drain electrode of NMOS tube n 1; one end of the R2 is connected with a high-level Vcc, the other end is connected with the source electrode of a PMOS tube p4, the grid electrode of a PMOS tube p4 is connected with the grid electrode of a PMOS tube p3, the drain electrode is connected with the grid electrode and the drain electrode of an NMOS tube n2 connected with a diode, the grid electrode of an NMOS tube n1, the grid electrode of an NMOS tube n3 and the emitter electrode of a triode Q1 connected with a diode.

The mirror branch 2 is composed of a PMOS tube p1 and an NMOS tube n3, wherein the source electrode of the PMOS tube p1 is connected with a high level Vcc, the grid electrode is connected with the drain electrode and then connected with the drain electrode of the NMOS tube n3, and the grid electrode of the PMOS tube p2 of the current output module is connected in parallel. The gate of the NMOS transistor n3 is connected to the gate of the NMOS transistor n2 in the bias generation circuit, and the source of the NMOS transistor n3 is grounded.

The feedback branch 3 comprises a sampling branch and an adjusting branch, the sampling branch is composed of a PMOS tube p5, a resistor R4 and a resistor R5, the width-to-length ratio of the PMOS tube p5 to the PMOS tube p1 is m: 1(m is in the range of 2-10, generally 2 or 4), and the ratio is set to be 4: 1. The source of the PMOS transistor p5 is connected to high level Vcc, the gate is connected to the gate of the PMOS transistor p1, and the drain is connected to one end of the resistor R4. The other end of the resistor R4 is connected with one end of the resistor R5 and is connected to the grid of the NMOS transistor n4 in the adjusting branch, and the other end of the resistor R5 is grounded. The regulating branch circuit consists of a resistor R3, an NMOS transistor n4 and a triode Q1. One end of the resistor R3 is connected with a high level Vcc, and the other end is connected with the drain of the NMOS tube n4 and the base and the collector of the triode Q1, and is connected with the output control signal module. The gate of the NMOS transistor n4 is connected to the end of the sampling branch where the resistor R5 and the resistor R4 are connected, and the source of the NMOS transistor n4 is grounded. The emitter of the transistor Q1 is connected with the grid of the NMOS transistor n2 in the bias generation module, and the collector of the transistor Q1 is connected with the base and is connected with the output control signal module and one end of R3.

The current output module 4 is composed of a PMOS tube p2, the source electrode of the PMOS tube p2 is connected with a high level Vcc, the grid electrode of the PMOS tube p2 is connected with the grid electrode and the drain electrode of the PMOS tube p1 in the mirror image branch, and the drain electrode of the PMOS tube p2 outputs bias current.

The control signal module 5 comprises an inverter INV1, an input end of the inverter INV1 is connected to the drain of the NMOS transistor n4, one end of R3 is connected to the base and collector of the Q1, and an output end of the inverter INV1 outputs a control signal CTRL _ OUT.

The resistor R3, the triode Q1 and the NMOS tube n2 form a starting loop, and when the power supply is just powered on, current flows through the path resistor R3, the triode Q1 and the NMOS tube n2, so that the circuit starts to work. The current In the PMOS transistor p4 flows through the NMOS transistor n2, and the current mirrors the drain current In2 In n2 to the NMOS transistor n1 through the diode-connected NMOS transistor n2, and the width-to-length ratio of the NMOS transistor n2 is the same due to the NMOS transistor n1, so that In1 is equal to In 2. Id2 is mirrored In1 again In a PMOS tube p4 by a diode-connected PMOS tube p3, the width-to-length ratio of the PMOS tube p4 is the same due to the PMOS tube p3, the resistance of R1 is not equal to R2, Ip3 is not equal to Ip4, and the current magnitude of Ip3 and Ip4 is given by the following formula

P 3-V for PMOS tube_gs3＝V_dd-I_n1·R₁-V_x

P 4-V for PMOS tube_gs4＝V_dd-I_n2·R₂-V_x

And the PMOS tubes p3 and p4 work in a saturation region,

for the PMOS transistor p3, <math> <mrow> <msub> <mi>I</mi> <mrow> <mi>p</mi> <mn>3</mn> </mrow> </msub> <mo>=</mo> <mfrac> <mn>1</mn> <mn>2</mn> </mfrac> <msub> <mi>&mu;</mi> <mi>p</mi> </msub> <msub> <mi>C</mi> <mi>ox</mi> </msub> <mfrac> <mi>W</mi> <mi>L</mi> </mfrac> <msup> <mrow> <mo>(</mo> <mo>-</mo> <msub> <mi>V</mi> <mrow> <mi>gs</mi> <mn>3</mn> </mrow> </msub> <mo>+</mo> <msub> <mi>V</mi> <mi>Tp</mi> </msub> <mo>)</mo> </mrow> <mn>2</mn> </msup> </mrow> </math>

for the PMOS transistor p4, <math> <mrow> <msub> <mi>I</mi> <mrow> <mi>p</mi> <mn>4</mn> </mrow> </msub> <mo>=</mo> <mfrac> <mn>1</mn> <mn>2</mn> </mfrac> <msub> <mi>&mu;</mi> <mi>p</mi> </msub> <msub> <mi>C</mi> <mi>ox</mi> </msub> <mfrac> <mi>W</mi> <mi>L</mi> </mfrac> <msup> <mrow> <mo>(</mo> <mo>-</mo> <msub> <mi>V</mi> <mrow> <mi>gs</mi> <mn>4</mn> </mrow> </msub> <mo>+</mo> <msub> <mi>V</mi> <mi>Tp</mi> </msub> <mo>)</mo> </mrow> <mn>2</mn> </msup> </mrow> </math>

so Ip4 < Ip 3. If Q1 is not present, In2 ═ Ip4, In2 is mirrored In1, In1 decreases, and as such, the current In NMOS n1, PMOS p3, NMOS n2, and PMOS p4 decreases gradually and finally approaches zero. To avoid this, Q1 can provide a current component to compensate for the drain In2 of NMOS transistor n2, so that I_n2＝I_p4+I_B1The current in the bias body is maintained stable.

In the mirror image branch, the ratio of the width-to-length ratio of the NMOS transistor n3 to the NMOS transistor n2 in the bias generation branch is 1: 1, the current in the NMOS transistor n2 is mirrored into the NMOS transistor n3, the current in the NMOS transistor n2 is further mirrored into the PMOS transistor p5 through the PMOS transistor p1 connected with a diode, and the current in the PMOS transistor p5 is four times that in the NMOS transistor n2 due to the fact that the ratio of the width-to-length ratio of the PMOS transistor p5 to the PMOS transistor p1 is 4: 1.

In the feedback branch, the current in the PMOS pipe p5 is four times larger than that in the NMOS pipe n2, and the adjustment sensitivity is increased. The change of the current in the NMOS transistor n2 causes the change of the current in the PMOS transistor p5, so that the voltage drop on the R5 changes, and the gate voltage of the NMOS transistor n4 changes. After the gate voltage of the NMOS transistor n4 is changed, the current In4 In the NMOS transistor n4 is changed, and the current In R3 is basically kept unchanged, because the current In R3 is equal to

$I_{\mathrm{<figure-callout\; id="3"\; label="R"\; filenames="C20071005240800101.png,C20071005240800102.png"\; state="\{\{state\}\}">R</figure-callout>}3}=\frac{V_{\mathrm{cc}}-(V_p+V_{\mathrm{gs}\left(n2\right)}+V_{\mathrm{be}})}{R_3}$

The current variation in the NMOS transistor n4 causes a compensated current component I_B1Thereby causing a change in the current in the NMOS transistor n 2.

In the phase inverter of the control signal module, the width-to-length ratio of the PMOS tube is large and 4-6 times of the width-to-length ratio of the N tube of the NMOS tube in the phase inverter, so that the overturning threshold value of the phase inverter is small, when the N4 of the NMOS tube is switched on, the drain voltage of the N4 of the NMOS tube is small, the inversion can be carried out, a high-level control signal is output, otherwise, when the N4 of the NMOS tube does not work, the output of the phase inverter is zero level, and other modules are switched off.

As shown In fig. 2, when In2 is increased by an undesirable component al relative to In1,

I′_n2＝I_n2+ΔI

I′_n2the PMOS transistor p1 and the PMOS transistor p2 are mirrored into the PMOS transistor p2 through an NMOS transistor n3

I_p4＝4I′_n2，

Therefore, the gate voltage of n4 increases by Δ V — Δ I · R5, and the current in n4 increases

ΔI_n4＝ΔV·g_m(n4)

Because of the fact that

I_B1+I_n4＝I_R3

$I_{R3}=\frac{V_{\mathrm{cc}}-(V_p+V_{\mathrm{gs}\left(n2\right)}+V_{\mathrm{be}})}{{\mathrm{<figure-callout\; id="3"\; label="R"\; filenames="C20071005240800101.png,C20071005240800102.png"\; state="\{\{state\}\}">R</figure-callout>}}_3}$

I_B1Decrease of Delta I_n4The current in the NMOS transistor n2 becomes

ΔI″_n2＝I_n2+ΔI-ΔI₁₃

＝I_n2+ΔI-ΔI_n3

＝I_n2+ΔI-4ΔI·R₅·g_m(n4)

Suitably selected R₅，g_m(n4)Can make the feedback reach the best effect.

The bias circuit of the invention adopts four MOS tubes and two resistors to form the main body of the bias circuit, which generates bias current irrelevant to the power supply, and the mirror loop and the feedback loop provide a current component for the bias main body circuit irrelevant to the power supply, thereby playing a stabilizing role for the bias current generated by the bias generating circuit. By adjusting the magnitudes of R4, R5, and R3, the magnitude of the current component fed back can be controlled, and the output can be stabilized.

After each parameter of the bias circuit is set, the circuit can independently work in the chip under the condition of power supply. Generally, the bias circuit is used for providing bias current for other modules at the beginning of chip power-on, so that the stability of the performance of the bias circuit is crucial to the chip. When the starting circuit starts the bias circuit to work, the circuit quickly enters a normal working state through the current mirror.

Claims (4)

1. A power supply bias circuit with negative feedback is characterized in that: the circuit comprises a bias generating circuit (1), a mirror image branch circuit (2), a feedback branch circuit (3) and a current output branch circuit (4);

the bias generating circuit (1) is used for generating bias current irrelevant to a power supply, and consists of current sources I1 and I2 and NMOS tubes n1 and n2, wherein the NMOS tubes n1 and n2 form a current mirror structure, and the grid width and the width-length ratio of the current mirror structure are equal; one end of the current source I1 is connected with a high level Vcc, and the other end is connected with the drain of n 1; one end of the current source I2 is connected with a high level Vcc, and the other end is connected with the drain electrode of an NMOS tube n2 and is connected into the mirror image branch (2); the grid electrode of the NMOS transistor n1 is connected with the grid electrode of the NMOS transistor n2 and is connected with the drain electrode of the NMOS transistor n 2; the sources of the NMOS transistors n1 and n2 are grounded;

the mirror image branch circuit (2) is used for mirroring the current in the bias generating circuit (1) and mirroring the current to the current output branch circuit (4); the mirror image branch (2) consists of a PMOS tube p1 and an NMOS tube n 3; the source electrode of the PMOS tube p1 is connected with a high level Vcc, the grid electrode thereof is connected with the drain electrode, and the PMOS tube p1 is connected with the current output branch (4) and is connected to the drain electrode of the NMOS tube n 3; the width-length ratio of the NMOS transistor n3 to the NMOS transistor n2 is equal, the grid electrode of the NMOS transistor n3 is connected with the drain electrode of the NMOS transistor n2, and the source electrode of the NMOS transistor n3 is grounded;

the feedback branch (3) is used for generating current feedback quantity and adjusting the bias current in the bias generation circuit (1); the feedback branch (3) consists of a current source I3 and an equivalent switch SW; one end of the current source I3 is connected with a high level Vcc, the other end is connected with one end of the SW, and the other end of the SW is connected with the drain electrode of an NMOS tube n2 in the bias generating circuit (1);

the current output branch (4) is used for outputting stable bias current, and the current output branch (4) consists of a PMOS (P-channel metal oxide semiconductor) tube p 2; the source electrode of the PMOS pipe p2 is connected with a high level Vcc, the grid electrode of the PMOS pipe p1 in the mirror branch circuit (2) is connected with the grid electrode, and the drain electrode outputs bias current.

2. The power supply bias circuit with negative feedback of claim 1, wherein: the specific realization circuit of the bias generating circuit (1) is composed of resistors R1 and R2, PMOS tubes p3 and p4 and NMOS tubes n1 and n2, and the width-length ratios of the PMOS tubes p3 and p4 are the same; one end of the resistor R1 is connected with a high-level Vcc, the other end is connected with the source electrode of a PMOS tube p3, the PMOS tube p3 is in diode connection, and the grid electrode and the drain electrode of the PMOS tube p4 are connected and then connected with the grid electrode of the PMOS tube p4 and the drain electrode of an NMOS tube n 1; one end of the resistor R2 is connected with a high-level Vcc, the other end is connected with the source electrode of a PMOS tube p4, the grid electrode of the PMOS tube p4 is connected with the grid electrode of the PMOS tube p3, the drain electrode is connected with the grid electrode and the drain electrode of an NMOS tube n2 connected with a diode, the grid electrode of an NMOS tube n1, the grid electrode of an NMOS tube n3 and the emitter electrode of a triode Q1 connected with the diode.

3. The power supply bias circuit with negative feedback of claim 1 or 2, wherein: the specific implementation circuit of the feedback branch circuit (3) comprises a sampling branch circuit and an adjusting branch circuit, wherein the sampling branch circuit consists of a PMOS (P-channel metal oxide semiconductor) tube p5, a resistor R4 and a resistor R5, the width-length ratio of the PMOS tube p5 to the PMOS tube p1 is m: 1, and the value range of m is 2-10; the source electrode of the PMOS tube p5 is connected with a high level Vcc, the grid electrode is connected with the grid electrode of the PMOS tube p1, and the drain electrode is connected with one end of a resistor R4; the other end of the resistor R4 is connected with one end of a resistor R5 and is connected to the grid of an NMOS transistor n4 in the adjusting branch circuit, and the other end of the resistor R5 is grounded; the adjusting branch consists of a resistor R3, an NMOS tube n4 and a triode Q1; one end of the resistor R3 is connected with a high level Vcc, and the other end is connected with the drain electrode of an NMOS tube n4 and the base electrode and the collector electrode of the triode Q1 and is connected with an output control signal module; the grid electrode of the NMOS tube n4 is connected with one end of the sampling branch circuit, which is connected with the resistor R5 and the resistor R4, and the source electrode of the NMOS tube n4 is grounded; the emitter of the transistor Q1 is connected with the grid of the NMOS transistor n2 in the bias generation module, and the collector of the transistor Q1 is connected with the base and is connected with the output control signal module and one end of R3.

4. The power supply bias circuit with negative feedback of claim 3, wherein: m is 2 or 4.

Images