CN100452331C - Bare chip building block packaging method - Google Patents
Bare chip building block packaging method Download PDFInfo
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- CN100452331C CN100452331C CNB2006101354263A CN200610135426A CN100452331C CN 100452331 C CN100452331 C CN 100452331C CN B2006101354263 A CNB2006101354263 A CN B2006101354263A CN 200610135426 A CN200610135426 A CN 200610135426A CN 100452331 C CN100452331 C CN 100452331C
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- square formation
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Abstract
A modular-packaging method of bare chips includes collecting bare chips to be square array and filling waster chip at blank position, placing said array on base plate of at least 3-layer printed circuit board, cutting out square hole at middle of clamp plate and sheathing said clamp plate at external of square array, covering top plate then setting square array upside down to take off base plate, coating conductive glue at chip back then covering base plate and baking them to form a flat plate, using photo-resist to fill seams, finalizing metal connections and sticking on top plate.
Description
Technical field
The present invention relates to a kind of new type integrated circuit package module, especially relate to the building block packaging method that a plurality of integrated circuit bare chips and integrated circuit bare chip and other film resistor electric capacity and quartz crystal oscillator need be carried out the high-density packages occasion.
Background technology
Traditional integrated circuit (IC) chip and the connection between the chip are to realize by the metal line of printed circuit board (PCB) (PCB), following 3 kinds of ways are adopted in connection between semiconductor chip and the printed circuit board (PCB) usually: 1, chip (bonding) is linked on the metal outer lead framework by ' group is fixed ', encapsulate with ambroin, more packaged integrated circuit block is welded on the printed circuit board (PCB); 2, bare chip is directly linked on the printed circuit board (PCB) by ' group is fixed ', gone up the black glue of insulation again; 3, upside-down mounting welding is about to chip and tips upside down on the printed circuit board (PCB), interconnects with the special metal salient point of making on the chip.
More than 3 kinds of encapsulation technologies commonly used all have serious technological deficiency.Preceding 2 kinds of methods are because semiconductor chip surface and printed circuit board surface not in one plane, need (bonding) realize the connection between chip and the printed circuit board (PCB) by ' group is fixed '.' group is fixed ' (bonding) technology at first need make the pressure welding point (pad) of 100 μ m * 100 μ m sizes on chip, line carries out ultrasonic bond or thermocompression bonding one by one again, and pressure welding point and outer lead are coupled together.The present system integration (SOC) chip pin number is up to hundreds of, and the pressure welding point on the chip has taken very big area, badly influences the qualification rate and the production efficiency of product by the operation of root line pressure weldering.Though the 3rd kind of upside-down mounting welding do not need to pursue the operation of root line pressure weldering, the welding of the aligning of the making of metal salient point and back-off chip is all very complicated on the chip.
Samsung Electronics Co., Ltd provides a kind of method and formed wafer and chip for preparing integrated circuit (IC) chip in the application for a patent for invention of publication number for CN1728370.This method comprises a plurality of cross baths of formation on the semiconductor wafer that has a plurality of contact pads thereon, and uses electric insulation layer to fill cross bath.The electric insulation layer composition is limited at least the first and second through holes therein, and described first and second through holes extend in first of cross bath.Cross the chip connection electrode with the and second respectively and fill first and second through holes.Subsequently, be a plurality of integrated circuit (IC) chip by cutting the electric insulation layer of wearing in the cruciform pattern with the semiconductor wafer scribing, the electric insulation layer in the described cruciform pattern and the location overlap of cross bath.
Samsung Electronics Co., Ltd provides a kind of relate to LCD drive integrated circuit chip and encapsulation in the application for a patent for invention of publication number for CN1773353.Output pad on the integrated circuit (IC) chip is arranged along the first long limit, and arranges along the second long limit that has the input pad.The output pad is connected with corresponding output pattern on being formed on basement membrane top and bottom face.All output patterns can be by the first long limit.On the other hand, the output pattern that is connected with output pad on the second long limit can pass through minor face.These patternings form effective pad and arrange, and do not increase the size of TAB encapsulation, and can reduce chip size.
Samsung Electronics Co., Ltd provides a kind of integrated circuit (IC) chip encapsulation and manufacture method thereof with ring-shaped silicon decoupling capacitor in the application for a patent for invention of publication number for CN1773699, comprise: circuit substrate, it comprises upper surface, lower surface and a plurality of bondings of being formed on the described upper surface refer to; At least one IC chip, it is arranged on the described upper surface of described circuit substrate and comprises a plurality of first I/O (I/O) terminals and a plurality of the 2nd I/O terminal; Decoupling capacitor, definite periphery that its described upper surface upper edge at described circuit substrate centers on described IC chip extends at least in part; A plurality of first bonding leads, it refers to the described bonding that a described I/O terminal of described IC chip is electrically connected to described circuit substrate; And a plurality of second bonding leads, its described the 2nd I/O terminal with described IC chip is electrically connected to described decoupling capacitor, wherein said decoupling capacitor comprises formation a plurality of bonding welding pads thereon and a plurality of connecting paths that are formed on wherein, wherein said bonding welding pad is connected to described second bonding lead, and wherein said connecting path is electrically connected to described bonding welding pad the described upper surface of described circuit substrate.
International Business Machine Corporation (IBM) provides a kind of apparatus and method that are used for the cooling semiconductor integrated circuit Chip Packaging in the application for a patent for invention of publication number for CN1790705, relate to a kind of be used for the microchannel refrigerating module be integrated in comprise a plurality of high-performance IC chips high density electronic module (for example Chip Packaging, system-level assembly module etc.) in apparatus and method.Electronic module is designed to, and the integrated refrigerating module (or coldplate) of high-performance (high power) IC chip next-door neighbour is provided with so that heat extraction effectively.In addition, comprise that the electronic module with the very big silicon carrier of a plurality of chip surface area mounted thereto is designed to, integrated silicon refrigerating module positive engagement on the back side of this chip to increase the structural intergrity of silicon carrier.
Summary of the invention
Problem such as the objective of the invention is to that the volume that exists at the existing integrated circuits chip encapsulation technology is big, complex process, qualification rate and production efficiency are on the low side, provide a kind of be applicable to the brand-new bare chip building block packaging method that a plurality of integrated circuit bare chips and integrated circuit bare chip and other electrical sheet resistance electric capacity and quartz crystal oscillator etc. need be carried out the high-density packages occasion (
BAre-
DIes
BUilding
BLock Technology, BDBB).
Technical scheme of the present invention is that the packaging technology with the processing technology of printed circuit board (PCB) and bare chip is integrated, the intermediate layer of at least 3 layer printed circuit boards is made and the bare chip same thickness, the centre hollows out into square, the bare chip of needs encapsulation is placed in the square that hollows out as the building blocks sample is crowded, with the optical semiconductor carving technology metal wire on bare chip and the printed circuit board (PCB) is coupled together, force together multilayer board is sticking, becoming not have group's high-density packages product of (bonding) calmly again.
The present invention includes following steps:
1) the device bare chip that needs is placed on the same printed circuit board (PCB) tightly bears against together as building block is direct, be spliced into the rectangle square formation, not having the blank space of chip to use with blank fills with the identical useless chip of shape dimensional thickness, form the identical rectangle silicon chip square formation of filling up jam-packed of thickness, be placed on the base plate at least 3 layer printed circuit boards.
2) clamping plate of selecting for use an identical centre with silicon wafer thickness to hollow out allow the positive place of silicon chip square formation surface and clamping plate at grade, and described clamping plate are the intermediate plate of at least 3 layer printed circuit boards.
3) top board with at least 3 layer printed circuit boards covers, and with silicon chip square formation back-off, takes off base plate, coats conducting resinl at the silicon chip back side, and base plate is buckled after coating insulating cement again in the clamping plate back side, and base plate and top board are clamped, and described top board adopts printed circuit board (PCB).
4) after clamping plate and base plate cling, carry out baking processing, allow silicon chip square formation substrate and sole plate metal layer form good Ohmic contact, simultaneously clamping plate and base plate are cemented.
5) after baking was finished, silicon chip square formation and clamping plate were to rely on to be linked to be one flat plate with the base plate, more with photoresist or insulating material the slit between the slit between silicon chip and silicon chip and clamping plate is filled and floating transition.
6) according to the lithography process method of semiconductor chip carry out between chip and the chip, metal interconnected processing between chip and the clamping plate.
7) after interconnection is finished,, promptly finish with the product of bare chip building block encapsulation with sticking the building of top board of protection usefulness.
Described printed circuit board (PCB) can adopt the common printed circuit board material, and size should be bigger slightly than silicon chip square formation, and outer shape determines according to application need, and except that clamping plate thickness should be with silicon wafer thickness be identical, the thickness of all the other each plates does not have specific (special) requirements.
In step 1), described bare chip can be a plurality of integrated circuit bare chips, also can be integrated circuit bare chip and other thin-film component chip, such as electrical sheet resistance electric capacity and quartz crystal oscillator etc.That is to say that this encapsulation way is applicable to the various components and parts that can carry out the top-level metallic interconnection with semiconductor technology processing.
In step 2) in, described allow silicon chip square formation surface and clamping plate positive locate to be meant at grade select clamping plate identical for use with silicon wafer thickness, in the middle of clamping plate, dig out a rectangle square hole big or small on an equal basis with the silicon chip square formation, be enclosed within the outside of silicon chip square formation, or clamping plate are cut apart with a knife or scissors by the diagonal of square hole, with silicon chip square formation jam-packed, allow the positive place of silicon chip square formation surface and printed circuit board (PCB) clamping plate at grade with the two halves plate of cutting apart with a knife or scissors.
In step 6), described device chip is integrated circuit (IC) chip or integrated circuit (IC) chip and thin-film component chip.
Because it is different that metal layer thickness on the printed circuit board (PCB) and the metal layer thickness on the silicon chip require, external metal line on base plate, clamping plate and the top board needs carry out preprocessing by the printed circuit board (PCB) processing method in advance, the photoetching top layer wiring after the bonding baking of bare chip is finished mainly solve between the chip and chip and printed circuit board (PCB) between be connected.In order to reduce the photoetching position error between the different processing batch, the scribing cutting of bare chip must be very accurate, thereby guarantee the same size of bare chip.The thickness of different chips also will be unified, such as adopting 250 μ m, and 300 μ m, standard thicknesses such as 350 μ m, otherwise will influence the quality of the photoetching that interconnects.
Compare with the existing integrated circuits chip encapsulation technology, outstanding advantage of the present invention is:
1, since chip and chip, chip and printed circuit board (PCB) directly interconnect at grade, so realized chip etc. plane high-density packages and the shortest interconnection line;
2, owing to adopt useless sheet square to fill the building blocks method of chip square formation white space, therefore simplify technology, improved the operability of invention;
3, because the chip that adopts simple and reliable metal line photoetching process to replace complicated poor efficiency ' is helped to decide ' (bonding) and the flipchip bump welding, therefore greatly reduce packaging cost, improved the qualification rate and the automaticity of product;
4, owing to adopt the two halves clamping plate that separate by diagonal, therefore guaranteed the reregistration precision of product with chip building blocks square formation jam-packed;
5,, therefore make the top-level metallic wiring disconnected bar can not occur and to the phenomenon of substrate short circuit owing to adopt photoresist or insulating material that the slit between chip chamber and chip and the clamping plate is filled and led up;
6, semiconductor chip processing and the two kinds of technologies of printed circuit board (PCB) processing that need pass through of original electronics new product, because the present invention is with a kind of semiconductor chip processing technology with its unification, therefore shorten the process of manufacture of electronic product, helped the design and the realization of system integrated chip (SOC);
7, because the pressure welding point on the chip is mainly used in ' group is fixed ' and wafer test, and the present invention has cancelled chip ' group is fixed ', therefore just can not want pressure welding point for the chip that does not need wafer test, thereby reduces area of chip;
8, when carrying out the top layer wiring with photoetching process, the line hole can be drawn from the optional position of chip, the outer signal line is not necessarily leaveed no choice but from chip internal around to four peripheries of chip or on the fixing pressure welding point, this provides convenience for exit at the cabling of chip internal;
9, owing to the interconnection line that has shortened greatly between chip chamber, chip and printed circuit board (PCB), the size of the output driving tube on the chip can reduce even cancel greatly, thereby has improved the speed of chip, has reduced the power consumption of chip, has dwindled chip area;
10, owing to do not have Plastic Package, chip back directly to stick on the sole plate metal film, therefore heat radiation is very good;
11, eliminated unsettled metal crimp bonding wire in the Chip Packaging after, it is frivolous, short and small that product becomes, and is specially adapted to portable product and military use.
Description of drawings
Fig. 1 is the structural representation of the embodiment of the invention 1 (the video storage card of band USB interface).
Fig. 2 is the circuit theory diagrams of the embodiment of the invention 2 (human heart periodic monitor device).
Fig. 3 is the planar structure schematic diagram of the embodiment of the invention 2 (human heart periodic monitor device).
Embodiment
Following examples will the present invention is further illustrated.
Embodiment 1: the video storage card of band USB interface.
The inner FLASH memory that comprises a USB interface chip, a microcontroller chip and 8 512M X 8 of this card.Can download movies from network by USB interface and computer, exist in the FLASH memory on the card.Card is inserted on the portable MP4 video player then and watches with oneself.Adopt manufacturing process of the present invention following (referring to Fig. 1):
1) the FLASH memory bare chip 2～9 of 8 512M * 8 and USB interface control chip 10, a microcontroller chip 11 are carried out cordwood system type by Fig. 1 and be spliced into the rectangle square formation, the blank space that does not have chip is for filling useless sheet 12, filling useless sheet 12 is to use with blank to be filled in the blank space that does not have chip with the identical useless chip of shape dimensional thickness, form the identical rectangle silicon chip square formation of filling up jam-packed of thickness, be placed on the base plate 1 in the multilayer board.
2) select clamping plate identical 13 for use with silicon wafer thickness, a rectangle square hole big or small on an equal basis with the silicon chip square formation is dug out in the centre, be enclosed within the outside of silicon chip square formation, also clamping plate 13 can be cut apart with a knife or scissors by the diagonal of square hole, with silicon chip square formation jam-packed, allow silicon chip square formation surface and clamping plate 13 positive places at grade with the two halves plate of cutting apart with a knife or scissors.
3) cover top board 14, with silicon chip square formation back-off, take off base plate 1, coat conducting resinl at the silicon chip back side, base plate 1 is buckled after coating insulating cement again in clamping plate 13 back sides, and base plate 1 and top board 14 are clamped.
4) after clamping plate 13 and base plate 1 cling, carry out baking processing, allow silicon chip square formation substrate and base plate 1 metal level form good Ohmic contact.
5) after baking was finished, silicon chip square formation and clamping plate 13 serve as that support is linked to be one flat plate with base plate 1, more with photoresist or insulating material the slit of 13 on the slit between silicon chip and silicon chip and clamping plate is filled and floating transition.
6) according to the lithography process method of integrated circuit (IC) chip carry out between chip and the chip, metal interconnected between chip and the clamping plate 13.
7) after interconnection is finished, on printed circuit board (PCB), have only simple 4 usb signal lines.Build the top board 14 of protection usefulness is sticking, put the metal shell of USB interface, promptly finish with the 4GB video storage card of the band USB interface of bare chip building block encapsulation.
Embodiment 2: human heart periodic monitor device (referring to Fig. 2 and Fig. 3).
In order to monitor the heart of patients with coronary heart disease under different activities, patient need carry 24 hours complicated heart monitors, gives the inconvenience of living of patient's the Bath band of wearing the clothes.Microcontroller chip MCU, the quartz crystal oscillator Y1, electrical sheet resistance (R1 and R2), thin slice electric capacity (C1, C2 and C3) and the pressure sensor chip U1 that adopt the present invention that the accurate timing necessary for monitoring is wanted make microsheet, originally the timing monitor board of 17mm * 34mm of making of routine techniques is reduced into the microsheet of area 7mm * 7mm, thickness 1mm, can be attached to chest throughout the year or inserts subcutaneous.In case symptom such as miocardial infarction take place patient, can send alarm signal automatically.Adopt manufacturing process of the present invention as follows:
1) microcontroller bare chip MCU, pressure sensing chip U1 and 3 thin slice electric capacity (C1, C2 and C3) that need be placed on the same printed circuit board (PCB) are close together with two electrical sheet resistance (R1 and R2) and quartz crystal oscillator Y1, be stained with insulating cement at the chip chamber that needs mutually insulated, be spliced into the rectangle square formation, the blank space that does not have chip is for filling useless sheet U2, fill useless sheet U2 and be with blank with the identical useless chip of shape dimensional thickness, be filled in the blank space that does not have chip, form the identical rectangle silicon chip square formation of filling up of thickness, be placed on the base plate in the multilayer board.In Fig. 3, the A port is for detecting output, and the B port is sense command.
2) select a printed circuit board (PCB) identical with silicon wafer thickness (being called clamping plate) for use, a rectangle square hole big or small on an equal basis with the silicon chip square formation is dug out in the centre, is enclosed within the outside of silicon chip square formation, allows the positive place of silicon chip square formation surface and printed circuit board (PCB) clamping plate at grade.
3) cover printed circuit board (PCB),, take off base plate, coat conducting resinl, coat insulating cement behind and between the element at the element of needs and base plate insulation at the silicon chip back side with silicon chip square formation back-off as top board.Because MCU chip, pressure sensing chip and three thin slice electric capacity and two electrical sheet resistance and quartz crystal oscillator are by different manufacturers production, thickness can be different, may be in thin chip back shimming or the levelling of overbrushing glue, and then buckle base plate, base plate and top board are clamped.
4) after clamping plate and base plate cling, carry out baking processing, allow nude film square formation substrate and sole plate metal layer form good Ohmic contact.
5) after baking was finished, nude film square formation and clamping plate were to rely on to be linked to be one flat plate with the base plate, more with photoresist or insulating material the slit between the slit between silicon chip and silicon chip and clamping plate is filled and floating transition.
6) take off top board, according to the lithography process method of integrated circuit (IC) chip carry out between chip and the chip, metal interconnected between chip and the printed circuit board (PCB) clamping plate.
7) after interconnection is finished, the top film of protection usefulness is substituted top board build (, can not do top board) with the chip square formation is sticking, promptly finish with the human heart periodic monitor device product that bare chip building block encapsulates with hard printed circuit board (PCB) because of pressure sensor is arranged.This thin slice is processed into fillet for four jiaos, in order to avoid scratch skin, volume only has the tablet size, uses very convenient.Required minicell and warning indication can be external.
Claims (2)
1. bare chip building block packaging method is characterized in that may further comprise the steps:
1) the device bare chip that needs is placed on the same printed circuit board (PCB) tightly bears against together as building block is direct, be spliced into the rectangle square formation, there do not have the blank space of chip to use to be measure-alike and fill with the useless chip of described device bare chip consistency of thickness with blank shape, form the identical rectangle silicon chip square formation of filling up jam-packed of thickness, be placed on the base plate at least 3 layer printed circuit boards;
2) select clamping plate identical with silicon wafer thickness for use, a rectangle square hole big or small on an equal basis with the silicon chip square formation is dug out in the centre, is enclosed within the outside of silicon chip square formation, allows the positive place of silicon chip square formation surface and printed circuit board (PCB) clamping plate at grade, or
Clamping plate are cut apart with a knife or scissors by the diagonal of square hole, with silicon chip square formation jam-packed, allowed the positive place of silicon chip square formation surface and printed circuit board (PCB) clamping plate at grade with the two halves plate of cutting apart with a knife or scissors;
3) cover printed circuit board (PCB) as top board, with silicon chip square formation back-off, take off base plate, coat conducting resinl at the silicon chip back side, base plate is buckled after coating insulating cement again in the clamping plate back side, and base plate and top board are clamped, and described top board adopts printed circuit board (PCB);
4) after clamping plate and base plate cling, carry out baking processing, allow silicon chip square formation substrate and sole plate metal layer form good Ohmic contact, simultaneously clamping plate and base plate are cemented;
5) after baking was finished, silicon chip square formation and clamping plate were to rely on to be linked to be one flat plate with the base plate, more with photoresist or insulating material the slit between the slit between silicon chip and silicon chip and clamping plate is filled and floating transition;
6) according to the lithography process method of device chip carry out between chip and the chip, metal interconnected processing between chip and the clamping plate;
7) after interconnection is finished,, promptly finish with the product of bare chip building block encapsulation with sticking the building of top board of protection usefulness.
2. bare chip building block packaging method as claimed in claim 1 is characterized in that in step 1), and described bare chip is at least 1 integrated circuit bare chip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2006101354263A CN100452331C (en) | 2006-12-31 | 2006-12-31 | Bare chip building block packaging method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2006101354263A CN100452331C (en) | 2006-12-31 | 2006-12-31 | Bare chip building block packaging method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101000876A CN101000876A (en) | 2007-07-18 |
| CN100452331C true CN100452331C (en) | 2009-01-14 |
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| Application Number | Title | Priority Date | Filing Date |
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| CNB2006101354263A Expired - Fee Related CN100452331C (en) | 2006-12-31 | 2006-12-31 | Bare chip building block packaging method |
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| CN (1) | CN100452331C (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN107369678A (en) * | 2016-05-13 | 2017-11-21 | 北京中电网信息技术有限公司 | A kind of system-in-a-package method and its encapsulation unit |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5723906A (en) * | 1996-06-07 | 1998-03-03 | Hewlett-Packard Company | High-density wirebond chip interconnect for multi-chip modules |
| US5818108A (en) * | 1993-06-08 | 1998-10-06 | Alcatel N.V. | High-density, highly reliable integrated circuit assembly |
| US6066513A (en) * | 1998-10-02 | 2000-05-23 | International Business Machines Corporation | Process for precise multichip integration and product thereof |
| US20030068839A1 (en) * | 2001-10-04 | 2003-04-10 | Culuris Allen Chris | Forming solder walls and interconnects on a substrate |
| CN1453868A (en) * | 2002-04-23 | 2003-11-05 | 海力士半导体有限公司 | Multi-chip package and producing method thereof |
-
2006
- 2006-12-31 CN CNB2006101354263A patent/CN100452331C/en not_active Expired - Fee Related
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5818108A (en) * | 1993-06-08 | 1998-10-06 | Alcatel N.V. | High-density, highly reliable integrated circuit assembly |
| US5723906A (en) * | 1996-06-07 | 1998-03-03 | Hewlett-Packard Company | High-density wirebond chip interconnect for multi-chip modules |
| US6066513A (en) * | 1998-10-02 | 2000-05-23 | International Business Machines Corporation | Process for precise multichip integration and product thereof |
| US20030068839A1 (en) * | 2001-10-04 | 2003-04-10 | Culuris Allen Chris | Forming solder walls and interconnects on a substrate |
| CN1453868A (en) * | 2002-04-23 | 2003-11-05 | 海力士半导体有限公司 | Multi-chip package and producing method thereof |
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| CN101000876A (en) | 2007-07-18 |
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