CN100451666C - Improved method and apparatus for measuring stability of frequency of time domain signal - Google Patents

Abstract

This invention discloses one method and device to improve time zone signals frequency stability measurement, which comprises the following steps: reference time signals are processed through DDS technique to get stable and accurate circle signals; expending measurement frequency signals range to get better reference signals and signals to be tested at fine time measurement; using DDS unit to process measurement frequency signals; when circle sample time singles come, according to fine time measurement module minimum resolution rate to test signals to be tested with reference time signals minimum phase difference to make the meter work to fulfill frequency signal measurement.

Description

Improved stability of frequency of time domain signal measuring method and device

Technical field

The invention belongs to the frequency stability measurement technology, be specifically related to method and device thereof that a kind of stability of frequency of time domain signal is measured.

Background technology

Frequency stability is to weigh the important indicator of a signal source of clock output frequency signal stability, and on time domain, clock signal frequency can be considered as frequency quantity the continuous function of time t over time, with f (t) expression.Instantaneous frequency when f (t) has also represented time t.In fact, because the difficulty of measuring, instantaneous frequency is a kind of theoretic notion, because all measurements and the frequency stability that relates to all need certain sampling time, measurement result then be an interior average frequency of this sampling time.On time shaft, be starting point, continuously measured signal sampled that each sample count value fi is corresponding with corresponding time point ti, then can obtain the average frequency value in the sampling time with t0 sometime.When being tending towards infinitely small, can obtain the time instantaneous frequency value of each time point.

For the time domain frequency stability that characterizes with formula (1) Allan variance and formula (2) Hadamard variance, need design correspondent frequency measurement mechanism that measured signal is monitored, thereby obtain frequency value corresponding in the corresponding sampling time T, further calculate the correspondent frequency degree of stability by variance.

${\mathrm{\σ}}_y(2,\mathrm{\τ},\mathrm{\τ}{,f}_h)=\sqrt{\frac{1}{2(N-1)}\underset{i=1}{\overset{N-1}{\mathrm{\Σ}}}{[f\left({\mathrm{\τ}}_{i+1}\right)-f\left({\mathrm{\τ}}_i\right)]}^2}---\left(1\right)$

τ is sampling time and sampling period in the formula, shows that Allan variance is the sampling of no gap, f _kBe corresponding difference frequency value in the sampling time, N is for measuring number of times.

$H{\mathrm{\σ}}_y(3,\mathrm{\τ})=\sqrt{\frac{1}{6(m-2)}\underset{k=1}{\overset{m-2}{\mathrm{\Σ}}}{(y_{k+2}-2y_{k+1}+y_k)}^2}---\left(2\right)$

τ is sample time, y _kBe the corresponding difference frequency value that records each sample time, m is for measuring number of times.

Typical number word frequency measuring method is to measure the pulse number of measured signal in the given sampling time (being gate time), and converting draws the frequency of measured signal.The measuring accuracy of this measuring method depends on gate time and measured signal frequency.When the measured signal frequency is low or obtain gate time hour, will produce than mistake.

People had proposed to utilize the edge of tested frequency signal as flip-flop number and " equal precision measurement " method that finishes counting afterwards, because at every turn the beginning in gate time T all is that edge with measured signal is as standard with finishing sample count, so improved the precision of measuring to a certain extent, and measuring accuracy has nothing to do with tested frequency signal frequency size.As shown in Figure 1.

Preset signal strobe (width is T) between high period, the rising edge of first pulse of measured signal, make the counter Enable Pin effective, and respectively to reference time base and measured signal are counted, as T after second, when presetting the gate low level and arriving, this moment, two counters did not stop counting, and two counters cut out simultaneously when the rising edge of always waiting until measured signal subsequently and extremely arrived.Here the time width of enable signal (actual signal strobe) equals the complete cycle number of measured signal just, and this guarantees that just measured signal can both keep the key of constant precision under any frequency condition.

In the equal precision measurement as shown in Figure 1, the frequency of establishing measured signal is Fx, with reference to the time base frequency be fo, in gate time T, counter to measured signal and with reference to the time base counting be respectively N ₁, N ₂, then have:

$f_x=f_0\×\frac{N_1}{N_2}---\left(3\right)$

By formula (3) as can be known, the frequency f x of measured signal with reference to the count value N of timebase frequency fo and two counters ₁, N ₂Relevant.Owing to adopted the equal precision measurement method, so to the count value N of measured signal ₁Can not introduce ± 1 error, promptly one with measured signal along beginning to count as triggering and finish in the actual gate sampling time width of the standard of counting, the count value of measured signal is equal to its complete cycle.And count value N ₂According to measurement scheme shown in Figure 1 the time, be to introduce error, the mechanism that its error produces is as shown in Figure 2.

When the signal strobe triggering is flushed to along the pulse, wait for the rising edge of next measured signal, this enables the corresponding counts device constantly and carries out " beginning counting " and " finishing to count " operation.As shown in Figure 2, enable counter moment point A and B and be flushed to along the pulse with reference to the next one of time-base signal and exist mistiming Δ t ₁, Δ t ₂The size of its concrete difference depends on that measured signal is with reference to time-base signal at A constantly or B phase difference value constantly, and its size neither a constant fixed skew concern that this will cause existing different errors when each sampling, and this also is the reason that produces counting error.For those high stabilities, high-frequency clock frequency source, need further to improve the method for measuring, with mistiming Δ t ₁, Δ t ₂Be reduced to minimum value even be 0, to improve its measuring accuracy.

Summary of the invention

The object of the present invention is to provide a kind of on the basis that keeps existing measuring method characteristic, improve the precision of measurement and the improved stability of frequency of time domain signal method and the device thereof of survey frequency scope, to overcome the above-mentioned shortcoming and defect that prior art exists.

The technical scheme that realizes method of the present invention is: improved stability of frequency of time domain signal measuring method, its method is: reference clock signal is undertaken after frequency division handles by the DDS technology, stablized, accurately normal period sampled clock signal; Simultaneously for widening tested frequency signal measurement range, and in the chronometer time measurement links reference signal and measured signal are utilized the DDS unit that original tested frequency signal is carried out frequency division and are handled than phase cycle preferably in order to obtain; In the periodic sampling clock signal when arriving, judge according to the intrinsic minimum resolution measuring accuracy of chronometer time measurement module whether this phase differential constantly of measured signal and reference clock signal is minimum, when phase differential for hour, enable corresponding counter works.

In time domain frequency signal stable measurement, with reference to adopting the 10MHz clock signal to import usually as canonical reference with the frequency source signal, and the output of the frequency of reference source signal can be seen one as than the stable clock source, by stable reference source clock signal being made the synthetic frequency splitting technology of numeral, can obtain the periodic sampling clock signal of standard.For measured signal, for widening the application measurement range of entire measuring device, satisfy the demand that high-frequency signal is measured, guaranteeing under the impregnable prerequisite of measured signal source inherent stability, the DDS chip and the technology of existing comparative maturity have been introduced in the invention, it is according to the Nyquist sampling, from the phase place of continuous signal

Set out sample of signal, quantification, coding, form a table of natural sines, exist among the EPROM.When synthetic, by changing the frequency control word of phase accumulator, change phase increment, the phase increment difference will cause the difference of the number of sampling in the week.Because of angular frequency

Under the constant situation of sampling frequency, by changing the frequency control word of phase accumulator, the phase place/amplitude quantization of this variation is become digital signal, can obtain the integrated signal that people need by D/A conversion and low-pass filter.Because after the input and output signal to noise ratio (S/N ratio) that it is good, measured signal are handled by DDS, can obtain the suitable and lower signal of frequency of degree of stability and former measured signal.Because in the scheme is the measured signal that the former measured signal frequency division of upper frequency is converted into lower frequency, on using, the DDS chip do not adopt its inner PLL frequency multiplication functions of modules, so can obtain better signal to noise ratio (S/N ratio) output at the DDS output terminal.And,, can obtain point-device periodic signal (as 1.000000000MHz) through behind the frequency division of DDS for the not high tested frequency signal (as 10.123456789MHz) of those accuracy.

For improving the precision of whole measurement, on the basis of " equal precision measurement " method, introduce the chronometer time measurement module, when the periodic sampling clock signal begin/end trigger is when arriving, be not at once measured signal and reference signal to be begun/finish counting, but under the intrinsic minimum measurement accuracy of chronometer time measurement module itself, judge earlier the phase relation of two paths of signals, the rising edge of measured signal and reference signal is overlapped as far as possible.When the rising edge mistiming of measured signal and reference signal was the ns magnitude, the pulse counting method of traditional measurement pulse width was no longer suitable.This is because the pulse that will survey is narrow more, and needed clock frequency is just higher, and is also high more to the performance requirement of chip.Introduced the TDC-GP1 module in apparatus of the present invention.

Realize the present invention's device, as shown in Figure 3: it comprises:

First isolated amplifier: in order to processing to reference clock signal; Its output is connected to external clock input end, the precise time-time-interval measuring unit of DDS frequency unit and counting unit when walking;

Second isolated amplifier: in order to processing to tested frequency signal; Its output is connected to the precise time-time-interval measuring unit and counting unit when walking;

The DDS frequency unit of reference clock signal: handle in order to DDS frequency division to reference clock signal; Its output is connected to processor;

The DDS frequency unit of tested frequency signal: handle in order to the DDS frequency division to tested frequency signal, its output is connected to second isolated amplifier;

Counting unit when walking: receive the output of first isolated amplifier and second isolated amplifier, in order to tested frequency signal and reference clock signal phase differential are differed under the intrinsic minimum resolution measurement precision of chronometer time measurement module itself hour, tested frequency signal and reference clock signal are counted;

Latch unit: in order to latching of counting; Connection processing device, counting unit when walking;

Precise time-time-interval measuring unit: judge that whether the concrete time difference of this moment one group of reference clock signal rising edge and measured signal rising edge reaches the intrinsic minimum resolution measuring accuracy of module, carries out work thereby enable corresponding counter by processor;

Processor: in order to the control and the data processing of signal.

This method be a kind of lighter, method satisfies engineering duty to the stability of frequency of time domain signal Testing requirement intuitively.On the basis of " equal precision measurement ", further improve measuring accuracy, remedy the error that " equal precision measurement " brings.It can be widely used in the frequency stability measurement of time domain frequency signal source, as crystal oscillator, programme-controlled exchange signal source, atomic frequency standard etc.

And this device is formed rationally, and is simple, stable performance.

Description of drawings

Precision count measurement schematic diagrams such as Fig. 1

Fig. 2 equal precision measurement error produces schematic diagram

The improved stability of frequency of time domain signal instrumentation plan of Fig. 3

Fig. 4 TDC-GP1 measuring unit figure

Fig. 5 reference clock signal DDS unit frequency division is handled synoptic diagram

The tested frequency signal DDS of Fig. 6 unit frequency division is handled synoptic diagram

Fig. 7 stability of frequency of time domain signal instrumentation plan

Embodiment

1, reference clock signal f ₀Processing: as shown in Figure 5

Reference clock signal f ₀Through being sent to the external clock input end of DDS1 behind the isolated amplifier 1, as DDS1 work external reference clock, the external communication port of DDS1 is connected to processor simultaneously, in order to the control word order of accepting from processor and two-way data transmission.The actual DDS1 chip internal of selecting for use has 2 48 bit frequency control registers (F0, F1), for this device reference clock signal f ₀Be 10MHz, when not using DDS1 inside PLL double frequency function, during 48 frequency control register F0 full packing 1, DDS1 has the output of 10MHz frequency signal, therefore for obtaining the periodic sampling time signal T (as 1 second, 10 seconds) of standard, need corresponding frequency division numerical value be set to DDS1 medium frequency control register F0, concrete Calculation Method is:

$D=\frac{2^{48}\×f}{f_0}---\left(4\right)$

Wherein, D is the concrete frequency division numerical value of required calculating, f ₀Be reference signal frequency, f in this device ₀Be 10MHz, f is the sampling time signal frequency of required frequency division, is the situation of 1Hz (1 second) and 0.1Hz (10 seconds) for f, and frequency division numerical value D should be 2 ⁴⁸* 10 ^-7Or 2 ⁴⁸* 10 ^-8Concrete sampling time T be the user according to the needs in the actual samples process and by PC end software setting, and frequency division numerical value is after to be processor obtain the sampling time T of user's setting by RS232 serial line interface and PC end communication, using formula (4) calculates.Processor is according to the corresponding serial communication sequential of DDS1, frequency division numerical value D is write DDS1 respective cache device after, obtain final DDS1 end periodic sampling time signal T output.

2, tested frequency signal f _xProcessing: as shown in Figure 6

Tested frequency signal f _xDeliver to two-way DDS processing module respectively through behind the isolated amplifier 3.When the measured signal frequency is up to a hundred million even during the hundreds of megahertz, consider away the restriction of hour counter to tested frequency range, design in the present invention wherein one road DDS2 module is carried out 1/100 frequency division to tested frequency signal and is handled.The external clock input end of DDS2, the reference clock when working as DDS2 are directly sent in measured signal behind isolated amplifier 3.The external communication port of DDS2 is connected to single-chip microcomputer, single-chip microcomputer according to formula (4) obtain 2 ⁴⁸* 10 ^-2Frequency division numerical value writes the DDS2 buffer area by the serial communication sequential, behind 1/100 fen frequency signal that DDS2 obtains, deliver to away hour counter 1 and carry out the coarse frequency measurement, single-chip microcomputer reads 1 pair of latch walk the numerical value of hour counter 1 sampling after, note the frequency numerical value of this moment, multiply by the coarse frequency value F that just can obtain measured signal after 100.

The measured signal of another road process isolated amplifier 3 is sent to the external clock input end of DDS3, the reference clock when working as DDS3.The external communication port of DDS3 is connected to single-chip microcomputer simultaneously, and single-chip microcomputer calculates the frequency division numerical value of using with the DDS3 communication according to formula (4):

Wherein F is by walking the coarse frequency value of the measured signal that hour counter 1 is counted, the single-chip microcomputer computing obtains, f gets 1MHz, and the concrete frequency division numerical value of gained is write the DDS3 buffer area by the serial communication sequential, behind DDS3, obtain the frequency signal of 1MHz, the frequency signal of gained is delivered to again obtained final 1MHz frequency signal output behind the low-pass filtering module.

3, the measurement of tested frequency signal: as shown in Figure 7

1MHz frequency signal and 10MHz reference clock signal that tested frequency signal obtains after handling through DDS frequency unit 2 are delivered to the precise time-time-interval measurement module respectively, and concrete is STOP1 and the START leads ends of delivering to corresponding time process chip.The rising edge of the periodic sampling time signal T that processor obtains after DDS frequency unit 1 is handled according to reference clock signal enables the precise time-time-interval measurement module STOP1 and START two-way frequency signal is carried out phase measurement, and send measurement result to processor processing, measure precision according to the minimum resolution of precise time-time-interval measurement module and judge whether the rising edge of one group of STOP1 and START frequency signal reaches the minimum mistiming, be i.e. measured signal and reference clock signal mistiming Δ t this moment among Fig. 2 ₁, Δ t ₂Minimum stops the surveying work of precise time-time-interval module with preprocessor, and enables away hour counter 2 and walk hour counter 3 to begin counting work.When processor detected the negative edge arrival of periodic sampling time signal T, another enabled the precise time-time-interval measurement module STOP1 and START two-way frequency signal is carried out phase measurement, when judging this mistiming Δ t constantly of two paths of signals ₁, Δ t ₂Hour, processor stops the surveying work of precise time-time-interval measurement module, and enable latch 2 and latch 3 latch the count value of walking hour counter 2 and walking hour counter 3 respectively, after making away hour counter 2 and walk hour counter 3 zero clearings by processor simultaneously and enable the sample count of a new round.In a complete sampling period T, latch 2 and latch 3 preserved walks hour counter 2 and walks the reading value N of hour counter 3 ₁, N ₂Pass to processor, processor passes through the RS232 serial line interface with measurement result N ₁, N ₂Be delivered to the PC end, PC end software obtains corresponding measured signal real-time frequency value y according to formula (3) ₁, y ₂Yi (i=1,2,3......n-1, n are positive integer).Utilize Visual Basic programmed environment and DirectX graph processing technique that measurement result and real-time measured signal are measured curve display on screen at the PC end simultaneously.The result of calculation of measured signal frequency stability obtains according to formula (1) Allan variance or formula (2) Hadamard variance.Need to prove, during calculated rate degree of stability that the real-time frequency value using formula (1) that measures or (2) are concrete, need be divided by the mean value f of measured signal real-time frequency in the result, the computing method of f are that the frequency values of the measured signal in n the sampling period T is done summation averaging.

Above-mentioned precise time-time-interval measurement module adopts the TDC-GP1 module, it is the absolute transmission time of utilizing signal to pass through logic gates to have proposed a kind of new time interval measurement method, measuring principle as shown in Figure 5, the number of the time interval between START signal and the STOP signal by not gate decides, and the transmission time of not gate can accurately be determined by integrated circuit technology.

In the TDC-GP1 module of selecting for use, by its judge this constantly the concrete time difference of one group of reference clock signal (START) rising edge and measured signal (STOP1) rising edge whether reach in the minimum resolution measuring accuracy, be reference clock signal and measured signal this constantly phase differential is hour, thereby enable corresponding counter by processor and carry out work, finally make the meter reading of measured signal in whole sampling period scope and reference signal accurate as far as possible, to improve the precision of whole frequency stability measurement.

Claims (9)

1, a kind of improved stability of frequency of time domain signal measuring method, its method is: reference clock signal is undertaken after frequency division handles by the DDS technology, stablized, accurately normal period sampled clock signal; Simultaneously for widening tested frequency signal measurement range, and in the chronometer time measurement links reference signal and measured signal are utilized the DDS unit that original tested frequency signal is carried out frequency division and are handled than phase cycle preferably in order to obtain; In the periodic sampling clock signal when arriving, judge according to the intrinsic minimum resolution measuring accuracy of chronometer time measurement module whether this phase differential constantly of measured signal and reference clock signal is minimum, when phase differential for hour, enable corresponding counter works.

2, improved according to claim 1 stability of frequency of time domain signal measuring method, it is characterized in that: described chronometer time measuring method adopts TDC-GP 1 module, and it is to utilize signal by the absolute transmission time of logic gates measured signal and reference clock signal phase relation accurately to be measured.

3, improved according to claim 1 stability of frequency of time domain signal measuring method is characterized in that: the DDS unit frequency division of described reference clock signal is handled and is: reference clock signal f ₀Through being sent to the external clock input end of DDS1 behind the isolated amplifier 1, as DDS1 work external reference clock, the external communication port of DDS1 is connected to processor simultaneously, in order to the control word order of accepting from processor and two-way data transmission, processor is according to the corresponding serial communication sequential of DDS1, after frequency division numerical value D write DDS1 respective cache device, obtain final DDS1 end periodic sampling time signal T output.

4, as improved stability of frequency of time domain signal measuring method as described in the claim 3, it is characterized in that: described DDS1 medium frequency control register F0 is provided with corresponding frequency division numerical value, and concrete Calculation Method is: $D=\frac{2^{48}\×f}{f_0};$ Wherein, D is the concrete frequency division numerical value of required calculating, f ₀Be the reference clock signal frequency, f in this device ₀Be 10MHz, f is the periodic sampling clock signal frequency of required frequency division.

5, improved according to claim 1 stability of frequency of time domain signal measuring method, the DDS unit frequency division of tested frequency signal is handled and is: tested frequency signal is delivered to DDS2 and DDS3 processing module respectively through behind the isolated amplifier 3; Wherein one road DDS2 module is carried out the processing of 1/100 frequency division to tested frequency signal, behind 1/100 fen frequency signal that DDS2 obtains, deliver to away hour counter 1 and carry out the coarse frequency measurement, single-chip microcomputer reads 1 pair of latch walk the numerical value of hour counter 1 sampling after, note the frequency numerical value of this moment, multiply by the coarse frequency value F that just can obtain measured signal after 100; Another road is sent to the external clock input end of DDS3 through the measured signal of isolated amplifier 3, reference clock when working as DDS3, behind DDS3, obtain the frequency signal of 1MHz, the frequency signal of gained is delivered to again obtained final 1MHz frequency signal output behind the low-pass filtering module.

6, improved stability of frequency of time domain signal measurement mechanism, it comprises:

First isolated amplifier: in order to processing to reference clock signal; Its output is connected to external clock input end, the precise time-time-interval measuring unit of DDS frequency unit and counting unit when walking;

Second isolated amplifier: in order to processing to tested frequency signal; Its output is connected to the precise time-time-interval measuring unit and counting unit when walking;

The DDS frequency unit of reference clock signal: handle in order to DDS frequency division to reference clock signal; Its output is connected to processor;

The DDS frequency unit of tested frequency signal: handle in order to the DDS frequency division to tested frequency signal, its output is connected to second isolated amplifier;

Counting unit when walking: receive the output of first isolated amplifier and second isolated amplifier, in order to tested frequency signal and reference clock signal phase differential are differed under the intrinsic minimum resolution measurement precision of chronometer time measurement module itself hour, tested frequency signal and reference clock signal are counted;

Latch unit: in order to latching of counting; Connection processing device, counting unit when walking;

Precise time-time-interval measuring unit: judge that whether the concrete time difference of this moment one group of reference clock signal rising edge and measured signal rising edge reaches the intrinsic minimum resolution measuring accuracy of module, carries out work thereby enable corresponding counter by processor;

Processor: in order to the control and the data processing of signal.

7, as improved stability of frequency of time domain signal measurement mechanism as described in the claim 6, it is characterized in that: the DDS frequency unit of described tested frequency signal comprises: the DDS2 module: tested frequency signal is carried out 1/100 frequency division handle, behind 1/100 fen frequency signal that DDS2 obtains, deliver to away hour counter 1 and carry out the coarse frequency measurement, single-chip microcomputer reads 1 pair of latch walk the numerical value of hour counter 1 sampling after, note the frequency numerical value of this moment, multiply by the coarse frequency value F that just can obtain measured signal after 100; The DDS3 module: another road is sent to the external clock input end of DDS3 through the measured signal of isolated amplifier 3, reference clock when working as DDS3, behind DDS3, obtain the frequency signal of 1MHz, the frequency signal of gained is delivered to again obtained final 1MHz frequency signal output behind the low-pass filtering module.

8, as improved stability of frequency of time domain signal measurement mechanism as described in claim 6 or 7, it is characterized in that: counting unit comprises when walking: walk hour counter 1: count in order to 1/100 fractional frequency signal to tested frequency signal; Walk hour counter 2: be used for the stable and accurate measured signal behind the tested frequency signal frequency division is counted; Walk hour counter 3: in order to reference clock signal is counted.

9, as improved stability of frequency of time domain signal measurement mechanism as described in the claim 6, it is characterized in that: further comprising a PC.

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