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CN100447994C - Structure of package - Google Patents

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Publication number
CN100447994C
CN100447994C CNB2004100464290A CN200410046429A CN100447994C CN 100447994 C CN100447994 C CN 100447994C CN B2004100464290 A CNB2004100464290 A CN B2004100464290A CN 200410046429 A CN200410046429 A CN 200410046429A CN 100447994 C CN100447994 C CN 100447994C
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CN
China
Prior art keywords
insulating barrier
conductive layer
encapsulation
buffering area
alloy
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CNB2004100464290A
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Chinese (zh)
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CN1694247A (en
Inventor
杨文焜
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Yupei Science & Technology Co Ltd
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Yupei Science & Technology Co Ltd
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Publication date
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Publication of CN1694247A publication Critical patent/CN1694247A/en
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Publication of CN100447994C publication Critical patent/CN100447994C/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Wire Bonding (AREA)
  • Coils Or Transformers For Communication (AREA)

Abstract

The present invention discloses a structure of wafer level packaging. The structure comprises a first patterned isolation layer, a conductive layer and a second patterned isolation layer. The first patterned isolation layer is formed with a passivation layer of an IC (Integrated Circuit). The conductive layer is configured to have a curved or winding conductive pattern. The second patterned isolation layer is formed over the conductive layer to have a plurality of openings, and contact metal balls can be formed on the openings to electrically couple to a print circuit board.

Description

The structure of encapsulation
Technical field
The present invention is relevant with a kind of wafer encapsulation, particularly encapsulate the structure of (waferlevel packaging) relevant for a kind of wafer form, after this wafer form encapsulating structure can be avoided solder ball and printed circuit board (PCB) combines,, variations in temperature causes the solder ball be full of cracks and the situation of open a way (open) because producing the increasing of displacement pulling force.
Background technology
Early stage leaded package technology has been not suitable for the too high more progressive semiconductor grain of lead-in wire (pins) density.Therefore, new nodule number group (Ball Grid Array:BGA) encapsulation technology is developed, and it can satisfy the package requirements of above-mentioned more progressive semiconductor grain.Above-mentioned nodule number group encapsulation has a benefit, and just its sphere lead-in wire (pins) has the spacing (pitch) of coming for a short time than above-mentioned leaded package, and above-mentioned lead-in wire (pins) is not easy infringement and distortion.In addition, short signal transmission distance can be of value to the lifting frequency of operation to meet the demand of faster efficient.Most encapsulation technology all is earlier the die separation on the wafer to be become other crystal grain, and then at above-mentioned other crystal grain of packaging and testing.In addition, a kind of encapsulation technology that is called wafer form encapsulation (waferlevel package:WLP) can just encapsulate the crystal grain on the above-mentioned wafer before separating other crystal grain.Above-mentioned wafer form encapsulation (wafer level package:WLP) has some benefits, for example: short production cycle (cycle time), lower price and do not need filler (under-fill) or mold (molding).
In addition, employed in the market encapsulation (package) part-structure as shown in Figure 1.The protective layer (passivation) 102 that wherein comprises an insulating barrier 103 and an integrated circuit package 100; the material of above-mentioned insulating barrier 103 can be BCB, the polyimides dielectric materials such as (polyimides) of thickness 5 microns (micron), and the material of protective layer 102 can be polyimides (polyimides) or silicon nitride.Rerouting conductive layer (RDL:redistribution layer) 104 combines with the aluminium pad (Al pads) 101 of above-mentioned insulating barrier 103, integrated circuit package, and the material of above-mentioned rerouting conductive layer 104 can be copper nickel gold (Cu/Ni/Au) alloy of thickness 15 microns (micron).In addition, insulating barrier 105 covers above-mentioned conductive layer 104, and has a plurality of openings in the above-mentioned insulating barrier 105, has a solder ball (solder ball) 106 on each this opening and is beneficial to electrically connect with a printed circuit board (PCB) (PCB) or external device (ED).The material of above-mentioned insulating barrier 105 can be BCB, epoxides (Epoxy) or resin dielectric materials such as (Resin).
Traditional encapsulating structure recited above uses outermost material to strengthen fixedly solder ball 106 usually.Its shortcoming comprises: the conductive layer 104 of sputter (sputter) causes negative effect too by force with the bond strength of insulating barrier 103; When solder ball 106 combined the back and produces pulling force because of variations in temperature with printed circuit board (PCB), stressed district 107 was at the joint of above-mentioned solder ball 106 with conductive layer 104; When the DNP distance widens, cause solder ball 106 be full of cracks and form open circuit (open) because variations in temperature produces the increasing of displacement pulling force.
In view of this, the present invention proposes to change the structure of optimum wafer form encapsulation to improve above disappearance.
Summary of the invention
Purpose of the present invention is for providing the structure of wafer form encapsulation.After wafer form encapsulating structure of the present invention can be avoided solder ball and printed circuit board (PCB) combines,, variations in temperature causes the solder ball be full of cracks and the situation of open a way (open) because producing the increasing of displacement pulling force.
The present invention discloses a kind of structure of wafer form encapsulation, and this structure comprises first insulating barrier of a patterning, and above-mentioned first insulating barrier combines with the protective layer of an integrated circuit package; One conductive layer, above-mentioned conductive layer combine with metal gasket with the protective layer of above-mentioned first insulating barrier, integrated circuit package and produce crooked conductive layer pattern; And, second insulating barrier of a patterning, above-mentioned second insulating barrier combines with this conductive layer, and above-mentioned second insulating barrier has a plurality of openings, forms a contacting metal ball on each opening and is beneficial to electrically connect with a printed circuit board (PCB).
When above-mentioned contacting metal ball combines the back temperature influence and when producing pulling force with printed circuit board (PCB), conductive layer in the fixed area of above-mentioned encapsulating structure can be directly not stressed to the metal gasket of integrated circuit package, and utilize relatively poor combination degree between the conductive layer of above-mentioned bending and first insulating barrier, the extension in the buffering area of above-mentioned encapsulating structure can be strengthened and pulling force is absorbed.
Description of drawings
Fig. 1 is the schematic diagram of traditional wafer form encapsulating structure;
Fig. 2 is the schematic diagram of a wafer form encapsulating structure of the present invention.
Specific implementation method
The present invention discloses back segment (backend) structure of a kind of wafer form encapsulation (wafer level packaging:WLP).The detailed description of the invention is as follows, and it is non-in order to limit the present invention that an explanation is only done in described preferred embodiment.
See also Fig. 2, it is a structural representation of the present invention.Wherein do an explanation with wafer form encapsulation (waferlevel packaging:WLP), non-in order to limit the present invention.The present invention comprises an insulation layer patterned 203 and combines with the protective layer (passivation) 202 of an integrated circuit package 200; the material of above-mentioned insulating barrier 203 can be formed by dielectric material, for example can be BCB, silica gel (SINR), epoxides (Epoxy), polyimides (polyimides) or resin dielectric materials such as (Resin).Above-mentioned insulation layer patterned 203 has a plurality of perforates, and this insulation layer patterned 203 and protective layer 202 zones form stressed district 207, as shown in the figure the zone.And the material of the protective layer of said integrated circuit assembly 200 (passivation) 202 can comprise polyimides (polyimides) and silicon nitride material.
Rerouting conductive layer (RDL:redistribution layer) 204 combines with metal gasket 201 with the protective layer 202 of insulating barrier 203, integrated circuit package 200, produces at least one complications or crooked conductive layer pattern based on above-mentioned insulating layer pattern.The material of above-mentioned conductive layer 204 can be formed by conductive material, for example can be titanium copper (Ti/Cu) alloy or copper nickel gold (Cu/Ni/Au) alloy of thickness 15 microns (micron), above-mentioned titanium copper (Ti/Cu) alloy can utilize sputtering way to form, and copper nickel gold (Cu/Ni/Au) alloy then can utilize plating mode to form.The material of above-mentioned metal gasket 201 can be formed by conductive material, for example aluminium (Al) or copper (Cu).
In addition, an insulating barrier 205 covering protection conductive layers 204, above-mentioned insulating barrier 205 has a plurality of openings, wherein has a contacting metal ball 206 on each opening and is beneficial to electrically connect with a printed circuit board (PCB) (PCB) or external device (ED) (not icon).Above-mentioned contacting metal ball 206 can be formed by conductive material, for example is solder ball (solder ball) 206.The material of above-mentioned insulating barrier 205 can be BCB, silica gel (SINR), epoxides (Epoxy), polyimides (polyimides) or resin dielectric materials such as (Resin).
When above-mentioned solder ball 206 combines the back temperature influence and when producing pulling force with this printed circuit board (PCB); because above-mentioned conductive layer 204 directly combines with protective layer 202; make that protected seam 202 held on to when above-mentioned conductive layer 204 circuits were subjected to variations in temperature, the conductive layer 204 in the fixed area 210 of the above-mentioned encapsulating structure of result can be directly not stressed on the aluminium pad 201 of said integrated circuit assembly 200 interconnect (inter-connector).
In addition, in the buffering area 209 of above-mentioned encapsulating structure, above-mentioned conductive layer 204 directly combines with protective layer 202, makes that conductive layer 204 forms several bendings behind sputter (sputtering).When above-mentioned solder ball (solder ball) 206 combines the back temperature influence and when producing pulling force with this printed circuit board (PCB); because conductive layer 204 is not good with the conjugation of insulating barrier 203; when pulling force can be strengthened and pulling force is absorbed when conductive layer 204 breaks away from protective layer 202 greatly because circuit has bending that it is extended; so can prolong its useful life (life cycle), especially at a distance solder ball 206.
The present invention also comprises an insulation layer patterned 208 and is formed between insulating barrier 203 and the conductive layer 204, to increase the complications of ball lower conductiving layer.The material of above-mentioned insulating barrier 208 can be BCB, silica gel (SINR), epoxides (Epoxy), polyimides (polyimides) or resin dielectric materials such as (Resin).
The major advantage of the structure of wafer form encapsulation of the present invention is as follows: after wafer form encapsulating structure of the present invention can be avoided solder ball and printed circuit board (PCB) combines, cause the solder ball be full of cracks and the situation of open a way (open) because variations in temperature produces the increasing of displacement pulling force; Do not need to use in addition outermost material to strengthen fixedly solder ball.
The present invention illustrates as above that with preferred embodiment so it is not in order to limit the patent right scope that the present invention advocated.Its scope of patent protection when on the accompanying Claim scope and etc. same domain decide.All skill persons who is familiar with this field, in not breaking away from this patent spirit or scope, change of being done or retouching all belong to the equivalence of being finished under the disclosed spirit and change or design, and should be included in the following claim scope.

Claims (10)

1. the structure of an encapsulation is characterized in that comprising:
One device comprises a fixed area and a buffering area at least, and wherein metal gasket is formed at this fixed area, and the conductive layer pattern of tool concaveconvex structure is formed at this buffering area;
First insulating barrier of one patterning, this first insulating barrier is formed on the protective layer of an integrated circuit package, and first insulating barrier of the conductive layer pattern of this concaveconvex structure is positioned at this buffering area;
One conductive layer is covered on this protective layer and this first insulating barrier, produce the conductive layer pattern of this tool concaveconvex structure based on the pattern of this first insulating barrier in this buffering area, and this conductive layer in this buffering area comprises more than one concaveconvex structure; And
One second insulating barrier, this second insulating barrier covers this conductive layer, and this second insulating barrier has a plurality of openings, has a contacting metal ball on each this opening and is beneficial to electrically connect with external device (ED).
2. the structure of encapsulation as claimed in claim 1, it is characterized in that: it combines the back temperature influence and when producing pulling force when this contacting metal ball with printed circuit board (PCB), conductive layer in this buffering area utilizes this concaveconvex structure, with extension distortion or the displacement and pulling force absorbed of the pulling force in this buffering area by this concaveconvex structure, make that the conductive layer in this fixed area can be directly not stressed to the metal gasket of this integrated circuit; The material of this metal gasket is aluminium or copper.
3. the structure of encapsulation as claimed in claim 1, it is characterized in that: the 3rd insulating barrier that more comprises a patterning is formed between this first insulating barrier and this conductive layer, and the material of the 3rd insulating barrier is BCB, silica gel, epoxides, polyimides or resin.
4. the structure of encapsulation as claimed in claim 1, it is characterized in that: wherein the material of this first insulating barrier and this second insulating barrier is BCB, silica gel, epoxides, polyimides or resin.
5. the structure of encapsulation as claimed in claim 1, it is characterized in that: wherein the material of the protective layer of this integrated circuit package is a polyimides; This contacting metal ball is a solder ball.
6. the structure of encapsulation as claimed in claim 1, it is characterized in that: wherein the material of this conductive layer is a metal alloy, this metal alloy is CTB alloy and copper nickel billon; This CTB alloy can utilize sputtering way to form, and this copper nickel billon can utilize plating mode to form; The thickness of this metal alloy is between 10 microns to 20 microns.
7. the structure of an encapsulation is characterized in that comprising:
One device has a fixed area and a buffering area;
One insulation layer patterned, this insulating barrier covers the subregion of a bottom; And
One conductive layer is positioned on this patterned insulation layer, based on the shape of this patterned insulation layer and produce the pattern of complications and pulling force is absorbed;
Wherein metal gasket is formed on this fixed area, and the zigzag pattern that this conductive layer produced is formed on this buffering area.
8. the structure of encapsulation as claimed in claim 7, it is characterized in that: wherein the material of this insulating barrier is BCB, silica gel, epoxides, polyimides or resin.
9. the structure of encapsulation as claimed in claim 7, it is characterized in that: wherein the material of this conductive layer is a metal alloy; This metal alloy is CTB alloy and copper nickel billon; The thickness of this metal alloy is between 10 microns to 20 microns.
10. the structure of encapsulation as claimed in claim 9 is characterized in that: wherein this CTB alloy is to utilize sputtering way to form, and this copper nickel billon is to utilize plating mode to form.
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