CN100433299C - Technology method of anti-ESD integrated SOI LIGBT device unit - Google Patents
Technology method of anti-ESD integrated SOI LIGBT device unit Download PDFInfo
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- CN100433299C CN100433299C CNB2006100509002A CN200610050900A CN100433299C CN 100433299 C CN100433299 C CN 100433299C CN B2006100509002 A CNB2006100509002 A CN B2006100509002A CN 200610050900 A CN200610050900 A CN 200610050900A CN 100433299 C CN100433299 C CN 100433299C
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Abstract
The present invention relates to an SOI LIGBT VLSI technology realizing method for SOI LIGBT device structures of integrated ESD resisting diodes. An SOI LIGBT device manufactured by using the existing method doesn't have an ESD resisting structure and an ESD resisting function. The present invention changes the local oxide isolating technology in a conventional SOI LIGBT VLSI technology realizing method for SOI LIGBT devices into the groove isolating technology so as to realize silicon island isolation. Well doping is adjusted into ion injection well doping technology with reverse doping distribution. Anode short dot doping and cathode doping of ESD resisting diodes are carried out during doping in an n<+> source region, and before doping in a p<+> source region and in an anode region is carried out, low concentration p-type doping is carried out in an anode region. The method adopts the existing SOI LIGBT VLSI technical skill to obviously improve the ESD resisting performance of radio frequency SOI LIGBT devices and the integrated power under the condition of almost no increase in the technical complexity or the technical cost.
Description
Technical field
The present invention relates to the SOI CMOSVLSI process implementation method of the SOI LIGBT device architecture of integrated anti-ESD diode.
Background technology
SOI LIGBT device is owing to its smaller volume, weight, higher working temperature and stronger anti-irradiation ability, lower cost and higher reliability have extensive use as contactless power electronic switching or analog line driver in technology such as intelligent electric power electronics, hot environment power electronics, space power electronics and vehicles power electronics.SOI CMOS VLSI technology because its technical maturity height, dielectric isolation performance are good, isolation technology is simple, be convenient to three-dimensional integrated, be convenient to micro photo-electro-mechanical and power and radio frequency monolithic system integrated, be convenient to improve advantages such as integration density and integrated performance, make at VLSI, fields such as SOC (monolithic integrated system) makes, SPIC (intelligent power integrated system) manufacturing and TDS (three-dimensional integrated system) manufacturing have extensive use.How existing SOI LIGBT device is by SOI CMOS VLSI fabrication techniques, and its process is as follows:
1. the certain depth place forms buried insulating barrier under a side surface of certain conduction type silicon wafer, and this silicon wafer is isolated into two semiconductor regions fully, and wherein, a thicker side is as substrate, and thin side is used to make device and circuit as top silicon surface;
With polished top silicon surface through the oxidation first time, nitrogenize for the first time, etching forms the isolated area window for the first time, adopt LOCOS (carrying out local oxide isolation technology) to remove the silicon fiml in the isolated area, form the isolating oxide layer that isolated insulation layer and buried insulating barrier are combined as a whole, top silicon surface is isolated into several silicon island;
3. enough distances of being separated by on the silicon island then etch and are parallel to each other but perpendicular to the window of isolated insulation layer, mix and the identical impurity of top silicon surface conduction type requirement by window, obtain the higher semiconductor regions identical of a kind of concentration as buffering area, and remove the top silicon surface surface insulation layer with the top silicon surface conduction type;
4. with top silicon surface oxidation for the second time, etching forms and is parallel to each other and perpendicular to the window of isolated insulation layer, wherein half is positioned at buffering area for the third time, second half forms field oxide isolator between two adjacent windows between buffering area.And then carry out thin oxide gate and form gate oxide, the deposit polysilicon, the 4th time etching forms polysilicon gate, field plate and interconnection line, the 5th etching formation trap doping window carries out well region with certain impurities concentration distribution and the anode region that is positioned within the buffering area that trap injection doping and high annealing advance formation and top silicon surface conductivity type opposite then;
5. carry out the 6th etching then and form the interior source area doping window of well region, formation and well region and opposite source area mix and anneal;
6. and then carry out the 7th etching and form well region ohmic contact doping window and anode region ohmic contact doping window, and mix and short annealing forms the ohmic contact heavy doping in these two kinds of zones, conduction type is identical with well region;
7. carry out the 8th etching more then and form contact conductor contact hole window, then carry out metallic film growth or deposit, and carry out etchings formation metal electrode lead-in wire, metal field plate, metal interconnecting wires and pressure welding point nine times;
8. last deposit insulating passivation layer, etching metal crimp solder joint contact window carries out pin pressure welding and encapsulation.
These SOI LIGBT devices do not have integrated anti-ESD structure and function, because its intrinsic MOS (Metal-oxide-semicondutor) structure causes the high-pressure electrostatic more than the kilovolt easily in encapsulation, transportation, assembling and use.If there is not the protection of voltage stabilizing didoe clamper, easily caused the device permanent failure by this high-pressure electrostatic puncture because gate oxide is very thin.It is this because high-pressure electrostatic causes that grid puncture the device permanent failure that is caused and are called electrostatic damage (ESD).At present, business-like SOILIGBT device in use needs external discrete voltage stabilizing didoe to be protected, and has increased volume, weight and cost, and has reduced reliability.
Summary of the invention
The object of the invention is at the deficiencies in the prior art; the process of the SOI LIGBT device cell that a kind of making has self-anti-esd protection function is provided; thereby significantly improve the anti-esd protection performance of SOI LIGBT device oneself; reduce to adopt volume, weight and the cost of the various power electronic systems of this kind device, and improve system reliability.
The present invention includes following steps:
1. the certain depth place forms buried insulating barrier under a side surface of certain conduction type silicon wafer, this silicon wafer is isolated into two semiconductor regions fully, wherein, a thicker side is as substrate, thin side has certain conduction type and doping content distributes, and is used to make device and circuit as top silicon surface.
With polished top silicon surface through the oxidation first time, nitrogenize for the first time, etching forms the isolated area window for the first time, adopt STI (shallow-trench isolation technology)/DTI (deep trench isolation technology) to remove the silicon fiml in the isolated area, form the isolating oxide layer that isolated insulation layer and buried insulating barrier are combined as a whole, top silicon surface is isolated into several silicon island.
3. enough distances of being separated by on the silicon island etch and are parallel to each other but perpendicular to the window of isolated insulation layer, mix and the identical impurity of top silicon surface conduction type requirement by window, obtain the higher semiconductor regions identical of a kind of concentration with the top silicon surface conduction type, as buffering area, and remove the insulating barrier on top silicon surface surface.
4. with top silicon surface oxidation for the second time, etching forms and is parallel to each other and perpendicular to the window of isolated insulation layer, one of them is positioned at buffering area for the third time, another forms field oxide isolator between two adjacent windows between buffering area.Carry out thin oxide gate again and form gate oxide, the deposit polysilicon, the 4th time etching forms polysilicon gate, field plate and interconnection line, the 5th time etching forms trap doping window, carries out reverse trap ion implantation doping and high annealing then and advances the well region with certain impurities concentration distribution and the anode region that is positioned within the buffering area that forms with the top silicon surface conductivity type opposite.
5. carry out the 6th etching then and form the interior source area doping window of well region, form anode in short circuit point doping window and anti-ESD diode cathode doping window within the anode region simultaneously, at n
+Carry out doping of anode in short circuit point and anti-ESD diode cathode when mix in the source region and mix, and carry out short annealing formation n
+The source region, run through the n of p type anode region
+Anode in short circuit point and anti-ESD diode cathode district.
6. and then carry out the 7th etching and form well region ohmic contact doping window and anode region ohmic contact doping window, and mix and short annealing forms the ohmic contact heavy doping in these two kinds of zones, conduction type is identical with well region.
7. carry out the 8th etching more then and form contact conductor contact hole window, then carry out metallic film growth or deposit, and carry out etchings formation metal electrode lead-in wire, metal field plate, metal interconnecting wires and pressure welding point nine times, form the metal interconnecting wires between grid and the anti-ESD diode cathode simultaneously.
8. last deposit insulating passivation layer, etching metal crimp solder joint contact window carries out pin pressure welding and encapsulation.
STI/DTI technology in the step 2 is earlier ready disk oxidation nitrogenize and etching to be formed the silicon nitride mask graph with silicon dioxide resilient coating, then carry out etching groove and form groove with certain depth and side wall inclination angle, then carry out the passivation of slot wedge drift angle again and remove surface damage, carry out trench fill then and form groove isolation construction, and then high annealing in nitrogen, adopt chemico-mechanical polishing to carry out flattening surface more then, remove exposed silicon nitride and remaining exposed silicon nitride afterwards, grow successively at last and remove sacrificial oxide layer.
Integrated power and radio frequency SOI LIGBT device that the inventive method is convenient to adopt existing SOI CMOS VLSI technology to realize having excellent anti ESD performance make the anti-ESD performance of integrated power and radio frequency SOI LIGBT device significantly improve increasing hardly under process complexity and the technology cost condition.
Description of drawings
Fig. 1 is a process chart of the present invention;
Fig. 2 is STI/DTI process flow diagram among the present invention.
Embodiment
As depicted in figs. 1 and 2, the SOICMOS VLSI process implementation method of the SOI LIGBT device architecture of integrated anti-ESD diode may further comprise the steps:
1. the certain depth place forms buried insulating barrier under a side surface of certain conduction type silicon wafer, this silicon wafer is isolated into two semiconductor regions fully, wherein, a thicker side is as substrate, thin side has certain conduction type and doping content distributes, and is used to make device and circuit as top silicon surface.
With polished top silicon surface through the oxidation first time, nitrogenize for the first time, etching forms the isolated area window for the first time, adopt STI (shallow-trench isolation technology)/DTI (deep trench isolation technology) to remove the silicon fiml in the isolated area, form the isolating oxide layer that isolated insulation layer and buried insulating barrier are combined as a whole, top silicon surface is isolated into several silicon island.STI (shallow-trench isolation technology)/DTI (deep trench isolation technology) forms the silicon nitride mask graph with silicon dioxide resilient coating to ready disk oxidation nitrogenize and etching earlier, then carry out etching groove and form groove with certain depth and side wall inclination angle, then carry out the passivation of slot wedge drift angle again and remove surface damage, carry out trench fill then and form groove isolation construction, and then in nitrogen 900 the degree high annealings, adopt chemico-mechanical polishing to carry out flattening surface more then, remove exposed silicon nitride and remaining exposed silicon nitride afterwards, grow successively at last and remove sacrificial oxide layer.
3. enough distances of being separated by on the silicon island then etch and are parallel to each other but perpendicular to the window of isolated insulation layer, mix and the identical impurity of top silicon surface conduction type requirement by window, obtain the higher semiconductor regions identical of a kind of concentration with the top silicon surface conduction type, as buffering area, and remove the insulating barrier on top silicon surface surface.
4. then, with top silicon surface oxidation for the second time, etching forms and is parallel to each other and perpendicular to the window of isolated insulation layer, one of them is positioned at buffering area for the third time, another forms field oxide isolator between two adjacent windows between buffering area.And then carry out thin oxide gate and form gate oxide, the deposit polysilicon, the 4th time etching forms polysilicon gate, field plate and interconnection line, the 5th etching forms trap doping window and anode region silicon dioxide mask doping window, carries out reverse trap then and injects and mix and high annealing advances and forms with the well region with certain reverse impurities concentration distribution of top silicon surface conductivity type opposite and be positioned at anode region within the buffering area.
5. carry out the 6th etching then and form the interior n of well region
+Source area doping window forms anode in short circuit point doping window and anti-ESD diode cathode doping window within the anode region, simultaneously at n
+Carry out doping of anode in short circuit point and anti-ESD diode cathode when mix in the source region and mix, and carry out short annealing formation n
+The source region, run through the n of p type anode region
+Anode in short circuit point and anti-ESD diode cathode district.
6. and then carry out the 7th etching and form well region ohmic contact doping window and anode region ohmic contact doping window, and mix and short annealing forms the ohmic contact heavy doping in these two kinds of zones, conduction type is identical with well region.
7. carry out the 8th etching more then and form contact conductor contact hole window, then carry out metallic film growth or deposit, and carry out etchings formation metal electrode lead-in wire, metal field plate, metal interconnecting wires and pressure welding point nine times, form the metal interconnecting wires between grid and the anti-ESD diode cathode simultaneously.Anti-ESD diode anode passes through p
+Trap contact directly and source electrode at the device layer intraconnection.
8. last deposit insulating passivation layer, etching metal crimp solder joint contact window carries out pin pressure welding and encapsulation.
Claims (2)
1, the process of anti-ESD integrated SOI LIGBT device cell is characterized in that this method may further comprise the steps:
(1) the certain depth place forms buried insulating barrier under a side surface of certain conduction type silicon wafer, this silicon wafer is isolated into two semiconductor regions fully, a wherein thicker side is as substrate, thin side has certain conduction type and doping content distributes, and is used to make device and circuit as top silicon surface;
(2) with polished top silicon surface through the oxidation first time, nitrogenize for the first time, etching forms the isolated area window for the first time, adopt STI/DTI to remove the silicon fiml in the isolated area, form the isolating oxide layer that isolated insulation layer and buried insulating barrier are combined as a whole, top silicon surface is isolated into several silicon island;
(3) enough distances of being separated by on the silicon island etch and are parallel to each other but perpendicular to the window of isolated insulation layer, mix and the identical impurity of top silicon surface conduction type requirement by window, obtain the higher semiconductor regions identical of a kind of concentration with the top silicon surface conduction type, as buffering area, and remove the insulating barrier on top silicon surface surface;
(4) with top silicon surface oxidation for the second time, etching forms and is parallel to each other and perpendicular to the window of isolated insulation layer, one of them is positioned at buffering area for the third time, another forms field oxide isolator between two adjacent windows between buffering area; Carry out thin oxide gate again and form gate oxide, the deposit polysilicon, the 4th time etching forms polysilicon gate, field plate and interconnection line, and the 5th time etching forms trap doping window; Carry out the well region with certain impurities concentration distribution and the anode region that is positioned within the buffering area of reverse trap injection doping and high annealing propelling formation and top silicon surface conductivity type opposite then;
(5) carry out the 6th etching and form the interior source area doping window of well region, form anode in short circuit point doping window and anti-ESD diode cathode doping window within the anode region simultaneously, at n
+Carry out doping of anode in short circuit point and anti-ESD diode cathode when mix in the source region and mix, and carry out short annealing formation n
+The source region, run through the n of p type anode region
+Anode in short circuit point and anti-ESD diode cathode district;
(6) carry out the 7th etching and form well region ohmic contact doping window and anode region ohmic contact doping window, and mix and short annealing forms the ohmic contact heavy doping in these two kinds of zones, conduction type is identical with well region;
(7) carry out the 8th etching and form contact conductor contact hole window, then carry out metallic film growth or deposit, and carry out etchings formation metal electrode lead-in wire, metal field plate, metal interconnecting wires and pressure welding point nine times, form the metal interconnecting wires between grid and the anti-ESD diode cathode simultaneously;
(8) deposit insulating passivation layer, etching metal crimp solder joint contact window carries out pin pressure welding and encapsulation.
2, the process of anti-ESD integrated SOI LIGBT device cell as claimed in claim 1 is characterized in that the concrete grammar of STI/DTI in the described step (2) is successively: a. forms the silicon nitride mask graph with silicon dioxide resilient coating to ready disk oxidation nitrogenize and etching; B. carry out etching groove and form groove with certain depth and side wall inclination angle; C. carry out the passivation of slot wedge drift angle and remove surface damage; D. carry out trench fill and form groove isolation construction; E. high annealing in nitrogen; F. adopt chemico-mechanical polishing to carry out flattening surface; G. remove exposed silicon nitride and remaining exposed silicon nitride; H. grow successively and remove sacrificial oxide layer.
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| CN100433299C true CN100433299C (en) | 2008-11-12 |
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Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102157434B (en) * | 2011-03-10 | 2012-12-05 | 杭州电子科技大学 | Method for manufacturing SOI (silicon on insulator) LIGBT (lateral insulated gate bipolar transistor) device unit with p buried layer and longitudinal channel |
| CN102169831B (en) * | 2011-03-10 | 2013-01-02 | 杭州电子科技大学 | Manufacturing method of silicon-on-insulator lateral insulated-gate bipolar transistor (SOI LIGBT) device unit of lateral channel with positive (p) buried layer |
| CN104795379B (en) * | 2015-04-30 | 2017-06-27 | 南通大学 | Cascade structure inside and outside difference coplanar transmission packaging pin |
| CN116779666B (en) * | 2023-08-22 | 2024-03-26 | 深圳芯能半导体技术有限公司 | IGBT chip with ESD structure and manufacturing method thereof |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6191453B1 (en) * | 1999-12-13 | 2001-02-20 | Philips Electronics North America Corporation | Lateral insulated-gate bipolar transistor (LIGBT) device in silicon-on-insulator (SOI) technology |
| US20040129983A1 (en) * | 2003-01-03 | 2004-07-08 | Micrel, Incorporated | Thick gate oxide transistor and electrostatic discharge protection utilizing thick gate oxide transistors |
| US20040251498A1 (en) * | 2001-11-01 | 2004-12-16 | Zingg Rene Paul | Lateral islolated gate bipolar transistor device |
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- 2006-05-24 CN CNB2006100509002A patent/CN100433299C/en not_active Expired - Fee Related
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6191453B1 (en) * | 1999-12-13 | 2001-02-20 | Philips Electronics North America Corporation | Lateral insulated-gate bipolar transistor (LIGBT) device in silicon-on-insulator (SOI) technology |
| US20040251498A1 (en) * | 2001-11-01 | 2004-12-16 | Zingg Rene Paul | Lateral islolated gate bipolar transistor device |
| US20040129983A1 (en) * | 2003-01-03 | 2004-07-08 | Micrel, Incorporated | Thick gate oxide transistor and electrostatic discharge protection utilizing thick gate oxide transistors |
| US20050139958A1 (en) * | 2003-01-03 | 2005-06-30 | Micrel, Incorporated | Thick gate oxide transistor and electrostatic discharge protection utilizing thick gate oxide transistors |
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Owner name: HAIAN TIANRUN MECHANICAL TECHNOLOGY CO., LTD. Free format text: FORMER OWNER: HANGZHOU ELECTRONIC SCIENCE AND TECHNOLOGY UNIV Effective date: 20140709 |
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Effective date of registration: 20140709 Address after: Eleven Ge Village East of the town of Haian County of Jiangsu Province, Nantong City, 226600 Patentee after: Haian Tianrun Mechanical Technology Co., Ltd. Address before: Hangzhou City, Zhejiang province 310018 Jianggan District Xiasha Higher Education Park No. 2 street Patentee before: Hangzhou Electronic Science and Technology Univ |
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