CN100438037C

CN100438037C - Multistage NROM memory unit and its operation method

Info

Publication number: CN100438037C
Application number: CNB011346256A
Authority: CN
Inventors: 黄俊仁; 周铭宏
Original assignee: Macronix International Co Ltd
Current assignee: Macronix International Co Ltd
Priority date: 2001-11-07
Filing date: 2001-11-07
Publication date: 2008-11-26
Anticipated expiration: 2021-11-07
Also published as: CN1417862A

Abstract

The present invention relates to a memory unit of a multi-level NROM and an operating method thereof. The memory unit can form a nitride layer, a plurality of electric charges can be trapped into the nitride layer to form a plurality of electric charge trapped regions, and the electric charge trapped regions can store the electric charges as bits for storage. The memory unit of a multi-level NROM comprises a first bit and a second bit, wherein the second bit stores the electric charges to form an electric potential barrier which influences the magnitude of the read critical voltage level of the first bit, and the magnitude of the read critical voltage level is set by changing the size of the electric potential barrier. The magnitude of the critical voltage level of the first bit can be unilaterally read only with a fixed bias voltage, and thus, different storage states of the memory unit of a multi-level NROM can be defined.

Description

The memory cell of Multistage NROM and method of operation thereof

Technical field

The invention relates to a kind of multi-level cell memory and method of operation thereof, and particularly relevant for a kind of memory cell and method of operation thereof of Multistage NROM.

Background technology

The limit voltage characteristic of EPROM (EPROM), Electrically Erasable Read Only Memory (EEPROM) and flash memory (Flash ROM) is controlled by the total amount of electric charge that is retained in floating boom (floating gate), therefore its memory cell (memory cell) utilizes different limit voltage scopes to define any rank, limit voltage position, and each different rank, limit voltage position is the different store statuss that are used for defining multi-level cell memory.

Fig. 1 illustrates the structure chart of the memory cell of known flash memory, in Fig. 1, grid 102 parts can be divided into the floating boom of polysilicon (Poly-Silicon) made (Floating Gate) 104, it is in the state of " floating ", and be not connected with any circuit, be usefulness as store charge (Charge); Be used for the control gate (Control Gate) 106 of control data access.

An above-mentioned memory cell generally only to store one, promptly can only be differentiated 0 and 1 two states, and what illustrate as Fig. 2 is that memory cell is differentiated shown in the mode of 0 and 1 two states, when the data of reading cells, grid voltage can be located at V _Read, work as V _ReadV less than the limit voltage of memory cell _T1The time, big electric current the flow through drain electrode and the source electrode of memory cell are arranged this moment, judge that then this state is 1; Work as V _ReadBe V at the limit voltage of memory cell _T1With V _T2Between the time, little electric current the flow through drain electrode and the source electrode of memory cell are arranged this moment, judge that then this state is 0.

But, along with the development of highdensity flash memory structure, what illustrate as Fig. 3 is that memory cell is carried out shown in the mode that four kinds of different conditions differentiate, when carrying out four kinds of different conditions (00,01,10,11) when differentiating, variation that can only the control gate pole tension is set three different benchmark and is read voltage V _R1, V _R2And V _R3, differentiate four kinds of different limit voltages (ThresholdVoltage) (V _T1, V _T2, V _T3, V _T4).Similarly, when the data of reading cells, grid voltage can be located at V _Read, work as V _ReadBe V less than the limit voltage of memory cell _T1The time, maximum current the flow through drain electrode and the source electrode of memory cell are arranged this moment, judge that then this state is 11; Work as V _Read=V _R1Be V at the limit voltage of memory cell _T1With V _T2Between, big electric current the flow through drain electrode and the source electrode of memory cell are arranged time this moment, judge that then this state is 10, all the other states are by that analogy.

In Fig. 1, grid 102 structures from bottom to top are oxide skin(coating) (Oxide) 108, polysilicon layer (being floating boom 104), oxide skin(coating) 110, nitride layer (Nitride) 112, oxide skin(coating) 114 and polysilicon layer (control gate 106) in regular turn, are to need many roads photoetching making technology just can finish so will form grid 102.Moreover, in the stage of flash memory 100 sequencing, the voltage that control gate 106 is added is as flash memory 100 needed bias voltage when sequencing (Program), in order to reduce the voltage that control gate 106 is added, can oxide skin(coating) 108 with floating boom 104 between again more than the manufacture craft of polysilicons, to increase the coupling ratio (Coupling Ratio) of floating boom 104, reduce flash memory 100 needed bias voltage when sequencing.Sometimes, the program (as the hatched example areas among Fig. 1 120) that can implant near the many ions in the zone of drain electrode 118 source electrode 116 respectively, its program is in order to increase (Erase) ability of wiping of flash memory 100.

In sum, if with flash memory as multi-level cell memory, flash memory has all increased the complexity of semiconductor fabrication process in the manufacture craft that forms grid and near the zone of the drain electrode source electrode program how ions are implanted, and has so also increased semi-conductive design and manufacturing cost.

Summary of the invention

Therefore the invention provides a kind of memory cell and method of operation thereof of Multistage NROM, the bias voltage that need only be fixed with the framework of NROM, the monolateral mode that reads is made multi-level cell memory, can reduce the complexity of semiconductor fabrication process, similarly, can reduce semi-conductive design and manufacturing cost.

The invention provides a kind of memory cell and method of operation thereof of Multistage NROM, it can form the mononitride layer, this nitride layer can be absorbed in several electric charges and be absorbed in the zone to form two electric charges, these electric charges are absorbed in the zone can store these electric charges with the position as storage usefulness, the memory cell of Multistage NROM comprises one first, one second, and described this first is absorbed in the zone with this second for these electric charges; Wherein, store these electric charges to form a potential barrier at second, the size on the rank, a primary threshold current position that this potential barrier influence is read, set the size on rank, threshold current position by the size that changes potential barrier, and with the different store status of the memory cell of the size definition Multistage NROM on rank, threshold current position.

For above-mentioned purpose of the present invention, feature and advantage can be become apparent, preferred embodiment cited below particularly, and conjunction with figs. are described in detail below:

Description of drawings

Fig. 1 illustrates the structure chart of the memory cell of known flash memory.

What Fig. 2 illustrated is the mode that a memory cell is differentiated 0 and 1 two states.

What Fig. 3 illustrated is that memory cell is carried out the mode that four kinds of different conditions are differentiated.

Fig. 4 illustrates NROM structure graph of the present invention.

Fig. 5 illustrates the different storage states schematic diagram of the memory cell of flash memory of the present invention.

Label declaration:

100: flash memory 102,408: grid

104: floating boom 106,416: control gate

108,110,114,410,414: oxide skin(coating)

112,412: nitride layer 116: source electrode

118: drain electrode 120: ion implantation region territory

400:NROM 402: substrate

404,406: 418: the first of drain/sources

420: the second

Embodiment

Please refer to Fig. 4, what it illustrated is the NROM structure graph.In Fig. 4, NROM 400 is for having a substrate 402 (for example P type substrate), and a drain/source 404, a drain/source 406 are formed at respectively in the substrate 402, and implant formed N+ ion zone by the N+ ion.Be positioned on the substrate 402, and between drain/source 404 and drain/source 406 is grid 408 structures, wherein grid 408 structures from bottom to top are oxide skin(coating) 410, nitride layer 412, oxide skin(coating) 414 and polysilicon layer (being control gate 416) in regular turn, if when grid 408 and drain/source 406 add high voltage and carry out hot carrier sequencing (Hot carrier program), hot electron will penetrate oxide skin(coating) 410, and be absorbed in nitride layer 412, be absorbed in zone (being second 420) and in nitride layer 412, form an electric charge.

For NROM 400, basically the memory cell of a NROM 400 can respectively store one (promptly first 418 and second 420) between corresponding to drain/source 404 and drain/source 406, but when operating in sequencing in this way and reading, then drain/source 404 must be operated the reversal connection of doing polarity according to it with drain/source 406.And when the data that read wherein, and the current values of flow through drain/source 404 and the drain/source 406 that obtain, can be produced the potential barrier of so-called second effect (2nd-bit effect) because of the position of vicinity after the sequencing, the feasible high electric current that originally should flow through drain/source 404 and drain/source 406 of this potential barrier can descend many.

Therefore, utilize second effect of NROM 400 to realize the memory cell of Multistage NROM of the present invention.When second 420 among the NROM 400 during by sequencing, electric charge penetrates oxide skin(coating) 410 because of hot carrier effect, be absorbed in zone (promptly second 420) and be stored in electric charge, form a surface energy (Surface potential) zone (being potential barrier) that (Pulled-high) drawn high in the part.When the data that read first 418, drain/source 404 end ground connection, connect an appropriate voltage at drain/source 406, change the electric current position standard that reads by the potential barrier that changes second 420, with the accurate position of the potential barrier of telling distinct programization, the multiple case that is used as the memory cell of Multistage NROM stores.

So, in Fig. 4, Multistage NROM 400 is when carrying out sequencing, add a high voltage at grid 408, and add a suitable bias voltage at drain/source 404 and drain/source 406, can be so that Charge Storage be absorbed in zone (promptly second 420) in electric charge, owing to be trapped in the amount of charge difference of nitride layer 412, the size of the potential barrier that forms is just different.Multistage NROM 400 is when reading, add a suitable bias voltage at grid 408, drain/source 404 with drain/source 406 respectively, and the voltage that is added at drain/source 404 and drain/source 406 must be greater than because of second potential barrier that effect produced, just can make the MOS transistor conducting, and electric current flow through drain/source 404 and drain/source 406 are arranged.At the drain/source 404 of the memory cell of NROM 400, drain/source 406 and the control gate 416 suitable bias voltage of cross-over connections respectively, the flow through electric current of 406 of drain/sources 404, drain/source of detecting, because of second effect produces different potential barriers, the electric current of 406 of drain/sources 404, drain/source of then flowing through forms different rank, threshold current position, can read the various states of NROM 400 according to these rank, threshold current position.The different storage states schematic diagram that illustrates the memory cell of Multistage NROM of the present invention as Fig. 5 is an example, and the memory cell of two binary data must have 2 ²Individual state, each state (reaching " 00 " as " 11 ", " 10 ", " 01 ") be rank, a corresponding reference current position all.

Table 1

State	First	Second	Read current value
State	First	Second	Read current value	11	Low	Low	I1
10	Low	High V _t3	I2	11	Low	Low	I1
10	Low	High V _t3	I2	01	Low	High V _t2	I3
00	High V _t1	High/Low(Don’t care)	I4(0)	01	Low	High V _t2	I3

Table 1 is the current potential during with second different conditions and the electric current that is read for first of NROM, and with reference to the icon of Fig. 4, when reading NROM 400 various not coordinatioies rank, first 418 and second 420 must determine simultaneously, when being state " 00 ", then first 418 of sequencing is to high potential V _T1, and second 420 any current potential all can; When being state " 01 ", then second 420 of a sequencing is to high potential V _T2When being state " 10 ", then second 420 of a sequencing is to high potential V _T3When being state " 11 ", then connecing for first 418 and second 420 and be electronegative potential.So, flow through electric current between drain/source 404, the drain/source 406 when being maximum (i.e. electric current I 1 in the table 1) in detecting, then to go out NROM 400 present stored states are " 11 " to decidable; Flow through the electric current of 406 of drain/sources 404, drain/source when being second largest value (i.e. electric current I 2 in the table 1) in detecting, and then to go out NROM 400 present stored states are " 10 " to decidable, and other state by that analogy.

In sum, if with NROM as multi-level cell memory, compare as multi-level cell memory with known flash memory, NROM is simpler in the manufacture craft that forms grid than flash memory in the manufacture craft that forms grid, and NROM does not need the program of many ions implantation near the zone of drain electrode source electrode, as long as the electric current of monolateral reading flow between drain electrode-source electrode just can be judged NROM stored state at present.

Therefore, advantage of the present invention is to make multi-level cell memory with the framework of NROM, can reduce the complexity of semiconductor fabrication process, and can reduce semi-conductive design and manufacturing cost.

In sum, though the present invention with preferred embodiment openly as above, so it is not in order to limit the present invention; anyly be familiar with this operator; without departing from the spirit and scope of the present invention, when can being used for a variety of modifications and variations, so protection scope of the present invention is as the criterion when looking claims.

Claims

1. the memory cell of a Multistage NROM, it is characterized in that: it forms the mononitride layer, this nitride layer can be absorbed in several electric charges and be absorbed in the zone to form two electric charges, and these electric charges are absorbed in the zone can store these electric charges with the position as storage usefulness, and the memory cell of Multistage NROM comprises:

One first;

One has stored one second of these electric charges, and above-mentioned two electric charges are absorbed in the zone respectively as this first and this second;

Wherein, store these electric charges to form a potential barrier at this second, the size on these rank, primary threshold current position that this potential barrier influence is read, set the size on these rank, threshold current position by the size that changes this potential barrier, and with the different store status of the memory cell of the size definition Multistage NROM on these rank, threshold current position.

2. the memory cell of Multistage NROM as claimed in claim 1 is characterized in that: also comprise:

One substrate;

One first drain/source is formed at this substrate;

One second drain/source is formed at this substrate;

One grid is formed on this substrate, between this first drain/source and this second drain/source.

3. the memory cell of Multistage NROM as claimed in claim 2, it is characterized in that: wherein this grid from bottom to top forms one first oxide skin(coating), this nitride layer, one second oxide skin(coating) and a polysilicon layer in regular turn.

4. the memory cell of Multistage NROM as claimed in claim 1, it is characterized in that: wherein this second formed this potential barrier is a limit voltage, the memory cell of this limit voltage decision Multistage NROM is at the needed voltage of conducting.

5. the memory cell of Multistage NROM as claimed in claim 1 is characterized in that: this first is absorbed in the zone with this second for these electric charges.

6. the method for operation of the memory cell of a Multistage NROM, it is characterized in that: this memory cell forms the mononitride layer, this nitride layer can be absorbed in several electric charges and be absorbed in the zone to form two electric charges, and above-mentioned two electric charges are absorbed in the zone respectively as one first and one second, this first and this second can store these electric charges with the usefulness as storage, and the step of the method for operation of the memory cell of Multistage NROM comprises:

Store these electric charges to form a potential barrier at this second;

Set the size on these rank, primary threshold current position by the size that changes this potential barrier;

Different store status with the memory cell of the size definition Multistage NROM on these rank, threshold current position.