CN100438037C - Multi-level NROM memory cell and operation method thereof - Google Patents

Abstract

A Multi-Level NROM memory cell and method of operating the same, wherein a nitride layer is formed to trap a plurality of charges to form a plurality of charge trapping regions for storing the charges as bits for storage, the Multi-Level NROM memory cell comprising a first bit and a second bit. The magnitude of the threshold voltage level is set by changing the magnitude of the potential barrier, and different storage states of the memory cells of the multi-level NROM can be defined by single-side reading of the magnitude of the threshold voltage level of the first bit with fixed bias voltage.

Description

Storage unit of multi-level NROM and operation method thereof

technical field

The present invention relates to a multi-level storage unit and its operating method, and in particular to a multi-level NROM storage unit and its operating method.

Background technique

The threshold voltage characteristics of electrically programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM) and flash memory (Flash ROM) are controlled by the total amount of charge remaining in the floating gate. Therefore, its memory cell uses different threshold voltage ranges to define any threshold voltage level, and each different threshold voltage level is used to define a different storage state of the multi-level memory cell.

Fig. 1 depicts a structural diagram of a memory cell of a known flash memory. In Fig. 1, the gate 102 part can be divided into a floating gate (Floating Gate) 104 made of polysilicon (Poly-Silicon), which is in "floating" The state, but not connected with any circuit, is used as a storage charge (Charge); a control gate (Control Gate) 106 for controlling data access.

The above-mentioned storage unit can generally only store one bit, that is, only two states of 0 and 1 can be distinguished. As shown in FIG. 2, a storage unit distinguishes two states of 0 and 1. When data, the gate voltage will be set at V _read . When V _read is less than the threshold voltage V _t1 of the memory cell, a large current flows through the drain and source of the memory cell at this time, and the state is judged to be 1. ; When V _read is between V _t1 and V _t2 of the threshold voltage of the memory cell, a small current flows through the drain and source of the memory cell at this moment, then it is judged that this state is 0.

However, with the development of the high-density flash memory structure, as shown in FIG. 3, the manner in which the memory cell performs four different state discriminations is shown. When four different states (00, 01, 10, 11) are to be discriminated, It can only control the change of gate voltage to set three different reference read voltages V _r1 , V _r2 and V _r3 to distinguish four different threshold voltages (ThresholdVoltage) (V _t1 , V _t2 , V _t3 , V _t4 ). Similarly, when reading the data of the memory cell, the gate voltage is set at V _read , and when V _read is less than the threshold voltage V _t1 of the memory cell, the maximum current flows through the drain of the memory cell and the source, it is determined that this state is 11; when V _read = V _r1 is between V _t1 and V _t2 of the threshold voltage of the memory cell, a sub-large current flows through the drain and source of the memory cell at this time , then it is determined that this state is 10, and the rest of the states are deduced by analogy.

In FIG. 1 , the structure of the gate 102 from bottom to top is an oxide layer (Oxide) 108, a polysilicon layer (that is, a floating gate 104), an oxide layer 110, a nitride layer (Nitride) 112, and an oxide layer 114. and the polysilicon layer (the control gate 106 ), so many photolithography processes are required to form the gate 102 . Furthermore, at the stage of programming the flash memory 100, the voltage applied to the control gate 106 is used as the bias voltage required by the flash memory 100 during programming (Program). In order to reduce the voltage applied to the control gate 106, the oxide Another polysilicon manufacturing process is added between the layer 108 and the floating gate 104 to increase the coupling ratio of the floating gate 104 to reduce the bias voltage required for programming the flash memory 100 . Sometimes, an additional ion implantation procedure is added to the regions near the drain 118 and the source 116 (such as the hatched region 120 in FIG. 1 ), the procedure is to increase the erasing (Erase) capability of the flash memory 100 .

To sum up, if flash memory is used as a multi-level storage unit, the manufacturing process of flash memory for forming the gate and an additional ion implantation procedure in the area near the drain and source will increase the complexity of the semiconductor manufacturing process. , which also increases the design and manufacturing costs of the semiconductor.

Contents of the invention

Therefore, the present invention provides a multi-level NROM storage unit and its operation method. The NROM structure only needs to be fixed with a bias voltage, and the multi-level storage unit can be made by unilateral reading, which can reduce the complexity of the semiconductor manufacturing process. Degree, likewise, can reduce the design and manufacturing cost of semiconductors.

The present invention provides a multi-level NROM memory cell and its operation method, which can form a nitride layer, and this nitride layer can trap several charges to form two charge trapping regions, and these charge trapping regions can store these charges to As a bit for storage, the memory cell of the multi-level NROM includes a first bit and a second bit, and the first bit and the second bit are these charge trapping regions; wherein these charges are stored in the second bit To form a potential barrier, this potential barrier affects the size of a threshold current level of the first bit read, the size of the threshold current level is set by changing the size of the potential barrier, and the threshold current level The size of the level defines the different memory states of the memory cells of the multi-level NROM.

In order to make the above-mentioned purposes, features, and advantages of the present invention more comprehensible, the preferred embodiments are specifically cited below, together with the accompanying drawings, and are described in detail as follows:

Description of drawings

FIG. 1 is a structural diagram of a storage unit of a known flash memory.

FIG. 2 shows a method for distinguishing two states of 0 and 1 for a memory cell.

FIG. 3 illustrates the manner in which the memory cell performs four different state discriminations.

FIG. 4 is a diagram illustrating the NROM structure of the present invention.

FIG. 5 is a schematic diagram of different storage states of the storage unit of the flash memory of the present invention.

Label description:

100: flash memory 102, 408: gate

104: floating grid 106, 416: control grid

108, 110, 114, 410, 414: oxide layer

112, 412: nitride layer 116: source

118: drain 120: ion implantation area

400: NROM 402: Substrate

404, 406: drain/source 418: first

420: second place

Detailed ways

Please refer to FIG. 4 , which shows the structure diagram of NROM. In Fig. 4, NROM 400 is to have a substrate 402 (for example P-type substrate), a drain/source 404, a drain/source 406 are respectively formed in the substrate 402, and by N+ ion implantation The formed N+ ion region. Located on the substrate 402 and between the drain/source 404 and the drain/source 406 is a gate 408 structure, wherein the gate 408 structure is an oxide layer 410, a nitride layer from bottom to top Layer 412, oxide layer 414 and polysilicon layer (i.e. control gate 416), if a high voltage is applied to gate 408 and drain/source 406 for hot carrier program (Hot carrier program), hot electrons will pass through Through the oxide layer 410, it is trapped in the nitride layer 412, and a charge trapping region (ie, the second bit 420) is formed in the nitride layer 412.

For the NROM 400, basically a memory cell of the NROM 400 can store one bit between the corresponding drain/source 404 and the drain/source 406 (i.e. the first bit 418 and the second bit 420), However, when programming and reading in this way, the drain/source 404 and the drain/source 406 must be reversed according to their operation. And when the data of one bit is read, the obtained current values flowing through the drain/source 404 and the drain/source 406 will produce the so-called second bit effect ( 2nd-bit effect) potential barrier, which makes the high current that should flow through the drain/source 404 and the drain/source 406 decrease a lot.

Therefore, the storage unit of the multi-level NROM of the present invention is realized by utilizing the second bit effect of the NROM 400. When the second bit 420 in the NROM 400 is programmed, the charge penetrates the oxide layer 410 due to the hot carrier effect, and is stored in the charge trapping region (that is, the second bit 420), forming a local pull-up (Pulled-high) A surface energy (Surface potential) region (ie potential barrier). When reading the data of the first bit 418, ground the drain/source 404, connect an appropriate voltage to the drain/source 406, and change the read current bit by changing the potential barrier of the second bit 420 To distinguish the potential barrier levels of different programming, it is used as the multiple state storage of the memory cell of the multi-level NROM.

Therefore, in FIG. 4, when the multi-level NROM 400 is programmed, a high voltage is applied to the gate 408, and an appropriate bias voltage is applied to the drain/source 404 and the drain/source 406, which can make Charges are stored in the charge trapping region (that is, the second bit 420 ). Since the amount of charges trapped in the nitride layer 412 is different, the magnitudes of the potential barriers formed are different. When the multi-level NROM 400 is read, an appropriate bias voltage is applied to the gate 408, the drain/source 404 and the drain/source 406 respectively, and the drain/source 404 and the drain/source The voltage applied by 406 must be greater than the potential barrier generated by the second bit effect to turn on the MOS transistor, and a current flows through the drain/source 404 and the drain/source 406 . The drain/source 404, the drain/source 406 and the control gate 416 of the memory cell of the NROM 400 are respectively connected to appropriate bias voltages to detect the current flowing between the drain/source 404 and the drain/source 406. Due to the different potential barriers generated by the second bit effect, the current flowing between the drain/source 404 and the drain/source 406 forms different threshold current levels. According to these threshold current levels Various states of NROM 400 can be read. Figure 5 shows a schematic diagram of the different storage states of the storage unit of the multi-level NROM of the present invention as an example, the storage unit of the binary data of two bits must have ²² states, and each state (such as "11", "10", ""01" and "00") correspond to a reference current level.

Table 1

state The first one second read current value 11 Low Low I1 10 Low High V_t3 I2 01 Low High V_t2 I3 00 High V_t1 High/Low(Don't care) I4(0)

Table 1 shows the potential and the read current when the first bit and the second bit of NROM are in different states, and referring to the icon of FIG. 4 , when reading various levels of NROM 400, the first bit 418 and the second bit The bit 420 must be determined at the same time. When the state is "00", the first bit 418 is programmed to the high potential V _t1 , and any potential of the second bit 420 is acceptable; when the state is "01", only the second bit is programmed. bit 420 to high potential V _t2 ; when the state is “10”, only the second bit 420 is programmed to the high potential V _t3 ; when the state is “11”, the first bit 418 and the second bit 420 are connected to low potential . Therefore, when it is detected that the current flowing between the drain/source 404 and the drain/source 406 is the maximum value (i.e. the current I1 in Table 1), it can be determined that the current stored state of the NROM 400 is ""11"; when it is detected that the current flowing between the drain/source 404 and the drain/source 406 is the second largest value (i.e. the current I2 in Table 1), the state stored in the NROM 400 can be determined at present It is "10", and so on for other states.

To sum up, if NROM is used as a multi-level storage unit, compared with the known flash memory as a multi-level storage unit, the manufacturing process of NROM in forming the gate is simpler than that of flash memory in forming the gate, and the drain of NROM The region near the electrode and the source does not need an additional ion implantation procedure, as long as the current flowing through the drain-source is read unilaterally, the state currently stored in the NROM can be judged.

Therefore, the advantage of the present invention is to make the multi-level storage unit with the structure of NROM, which can reduce the complexity of the semiconductor manufacturing process, and can reduce the design and manufacturing cost of the semiconductor.

In summary, although the present invention has been disclosed above with preferred embodiments, it is not intended to limit the present invention. Any person familiar with the art may make various modifications without departing from the spirit and scope of the present invention. Action and retouching, so the scope of protection of the present invention should be based on the claims.

Claims (6)

1. A memory cell of multi-level NROM, characterized in that: it forms a nitride layer, which can trap several charges to form two charge trapping regions, and these charge trapping regions can store these charges as Bits for storage, the storage cells of multi-level NROM include: a first place; A second bit that has stored these charges, the above two charge trapping regions serve as the first bit and the second bit respectively; Wherein, these charges are stored in the second bit to form a potential barrier, and the potential barrier affects the size of a threshold current level of the first bit read, and the threshold is set by changing the size of the potential barrier. The size of the current limit level, and the size of the critical current level defines different storage states of the storage unit of the multi-level NROM. 2. the storage unit of multi-level NROM as claimed in claim 1, is characterized in that: also comprise: a substrate; a first drain/source formed on the substrate; a second drain/source formed on the substrate; A gate is formed on the substrate between the first drain/source and the second drain/source. 3. The memory cell of multi-level NROM as claimed in claim 2, wherein a first oxide layer, the nitride layer, a second oxide layer and a polysilicon layer. 4. The storage unit of multi-level NROM as claimed in claim 1, wherein the potential barrier formed by the second bit is a threshold voltage, and the threshold voltage determines that the storage unit of multi-level NROM is conducting pass the required voltage. 5. The memory cell of multi-level NROM as claimed in claim 1, wherein the first bit and the second bit are the charge trapping regions. 6. A method for operating a memory cell of a multi-level NROM, characterized in that: the memory cell forms a nitride layer, and the nitride layer can trap several charges to form two charge trapping regions, and the above two charge traps The regions are respectively used as a first bit and a second bit. The first bit and the second bit can store these charges for storage. The steps of the operation method of the storage unit of the multi-level NROM include: storing the charges at the second site to form a potential barrier; setting the size of a threshold current level of the first bit by changing the size of the potential barrier; The different storage states of the storage cells of the multi-level NROM are defined by the size of the threshold current level.

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