CN100412988C

CN100412988C - Rapidly flashing electrically erasable programmable read only memory array capable of choosing bytes

Info

Publication number: CN100412988C
Application number: CNB021526591A
Authority: CN
Inventors: 罗克·洪
Original assignee: Winbond Electronics Corp
Current assignee: Winbond Electronics Corp
Priority date: 2002-11-28
Filing date: 2002-11-28
Publication date: 2008-08-20
Anticipated expiration: 2022-11-28
Also published as: CN1505051A

Abstract

The present invention relates to a flash EEPROM (electrically erasable programmable read only memory) which comprises an array memory cell, one or more group selection wires, a plurality of first-selection transistors, a plurality of second-selection transistors, a plurality of first character element wires and a plurality of second character element wires, wherein the array memory cell is used for storing information; the group selection wires are coupled so as to selectively provide a group voltage; the first-selection transistors are coupled between the group selection wire(s) and the array memory cell; the second-selection transistors are coupled in the connection of the first-selection transistors, the array memory cell and an emitting electrode; the first character element wires are used for controlling the first-selection transistors; the second character element wires are used for controlling the second-selection transistors. The present invention has a small area, the array memory cell of the present invention is divided into a plurality of groups, and the access of each group is controlled by the selection transistors. In the mode, the quantity of the selection transistors can be decreased, and the whole array does not need being programmed or erased.

Description

Quickflashing eeprom array and erasing method thereof

Technical field

(electrically-erasableprogrammable read-only memory EEPROM), refers to a kind of quickflashing EEPROM (Electrically Erasable Programmable Read Only Memo) that can select group that has to the relevant a kind of quickflashing EEPROM (Electrically Erasable Programmable Read Only Memo) of the present invention especially.

Background technology

Fig. 1 (a) is that the standard floating gate is worn tunnel oxidation (floating gate tunnel oxide, FLOTOX) sectional view of cell element 20, floating gate is worn tunnel oxidation cell element 20 and is included compound crystal silicon control gate 22 (above apply a control voltage VCG), compound crystal silicon floating gate 24, the source terminal (one source pole voltage VS is arranged) with 32 couplings of n type zone, drain electrode end (a drain voltage VD is arranged), another compound crystal silicon layer 26 above two

n types zones

28 and 30, and these elements are formed a selection transistor above p type substrate 34.Between two compound crystal silicon elements 22 and 24 (control gate and floating gate), formed dielectric regions 38 between a compound crystal silicon, compound

crystal silicon zone

24 and 26 has formed two gate dielectric zones 40 and 44 respectively, the tunnel window zone 36 of wearing of compound crystal silicon element 24 (floating gate) has then formed and has worn tunnel dielectric regions 42, because the shape that control gate 22 and floating gate 24 have is special, can allow electronics pass so wear the formation in tunnel window zone 36.

Fig. 1 (b) is the symbolic notation that floating gate is worn tunnel oxidation cell element 20, wherein floating gate is worn tunnel oxide transistor 46 and is connected with selecting transistor 48, when running, meeting unlatching selection transistor 48 makes floating gate wear tunnel oxide transistor 46 and comes into operation, and the source terminal and the floating gate of transistor 48 are worn the drain electrode end of tunnel oxide transistor 46 alternatively simultaneously to also have a drain extreme 50.

If the sequencing floating gate is worn tunnel oxidation storage unit 20, when selecting grid end 26 to be applied in a positive voltage, between control gate 22 and drain electrode end 30, apply a quite high potential pulse, high voltage pulse makes and begins to generate carrier in the substrate 34, and make electronics by wearing tunnel dielectric regions 42, accumulation in floating gate 24; On the contrary, if the storage unit 20 of erasing will apply a reverse voltage between grid 22 and drain electrode end, the negatron in floating gate 24 can be by drain electrode attraction and by thin tunnel oxide 42 like this.

Erase and the operation of sequencing is to utilize the Fowler-Nordheim (F-N) of

floating gate

24 and 34 generations of silicon substrate to wear tunnel mechanism, carrier is passed be called the thin oxide layer of tunnel oxide 42.Wear the zone of tunnel window 36 formation tunnel oxides 42, the bigger tunnel window of wearing can increase and erases/speed of sequencing computing, but can increase the cell element size, the thin tunnel oxide regions 42 of wearing can reduce the required tunnel voltage of wearing, and reduce and to erase/time of sequencing computing, but, the manufacturing of this storage unit is difficulty relatively, also will increase the consideration for fiduciary level.

Therefore, floating gate wears that tunnel oxidation cell element 20 is wanted improved place comprise longly to wear the tunnel time, height is worn tunnel voltage and long erasing the time.

Fig. 2 (a) is the sectional view of the important non-volatile memory body-flash body of another kind, in flash memory cell 60, a drain electrode (62 or 64) and a source electrode (64 or 62) zone have been deposited in the substrate 76, top in substrate and drain electrode and source region (62 or 64) has deposited

insulation course

66 and 68, above

insulation course

66 and 68, deposited one deck floating gate 70, make floating gate 70 overlapping with an area part in drain electrode or source region (62 or 64), above floating gate 70, deposit second insulation course 72 then, deposition one deck control gate 74 above floating gate 70 is overlapped overlapping another zone (64 or 62) of itself and discord floating gate 70.

Fig. 2 (b) is a representation of representing storage unit 60 with circuit symbol.

When erase operation for use, to drain and

source terminal

62 and 64 ground connection, other applies high voltage in control gate 74, can allow floating gate 70 interior electrons tunnel arrive control gate 74, with the flash memory cell 60 of erasing, the tunnel process of wearing of wearing tunnel oxidation cell element 20 with floating gate among Fig. 1 (a) compares, the electrons tunnel process of flash memory cell 60 is than very fast in Fig. 2 (a), simultaneously indivedual terminal required voltages are also lower, in addition, applying under the voltage of about 14V, the typical case of flash memory cell 60 erases the time less than 1 millisecond, after the size through modification and optimization storage unit 60, can further improve the time of erasing and/or (lower) voltage.

If sequencing storage unit, then control gate 74 is set for and be close to opening (approximately 2V), the terminal ground connection that to be joined from floating gate 70 distant zones 62, provide high voltage to the terminal of being joined then by floating gate 70 closer zones 64, usually approximately be 12V, the electric field that produces in this time domain 62 is towards the direction away from floating gate 70, can make electronics pass passage area, inject floating gate 70, and allow gate charges, make storage unit 60 sequencing, the electronics of this process flows and is referred to as hot carrier injection method, represents with arrow in the drawings.

Fig. 3 (a) shows storage array 80, several intraconnections flash memory cells 60 in it are arranged with the ranks form, the connected mode of flash memory cell 60 is that the terminal near floating gate 70 is treated as source terminal, the control gate 74 of same array storage unit is received same character line (as WL0, WL1 etc.), column address decoder 82 can be in response to a given column address control and an operation character line, the source terminal of same array storage unit is received same source electrode line (as SL0, SL1 or the like), source electrode line is controlled and is operated by column address decoder 82, similarly, the drain electrode end of same line storage unit is received same bit line (as BL0, BL1 etc.), row address decoder 84 can be controlled and operation bit line by corresponding one given row address (Y-MUX is the row address line traffic pilot).When reading computing, sensor amplifier 86 meeting amplifying signals output it to output buffer 88; When the sequencing computing, data are stored in earlier in the input buffer 90, and then store by row address decoder 84, for can be correctly with the data write storage unit, before the sequencing step, erase earlier is stored in data in the same array storage unit, and this is because the control gate of same array storage unit is received same character line, is same group so can be taken as.More once, in the storage array that uses flash memory cell, the modification of storage unit must be unit (being meant a permutation here) with big block, and using floating gate to wear in the storage array of tunnel oxidation cell element, the modification of storage unit can bit be the basis to bit, when revising storage unit is when being the unit with big block, and some data that do not need to revise still will be written into storage array again, and this process is not only lost time and also wasted power supply.

Fig. 3 (b) and Fig. 3 (a) are similar, and it is to treat as source terminal from floating gate 70 distant terminals that difference is in the connected mode of flash memory cell 60, and details are as follows for the result of this different connected modes.

Table 1A and table 1B be detailed be listed in erase, sequencing and when reading computing, how column address decoder 82 and row address decoder 84 control bit line, character line, source electrode line, the operating characteristic of table 1A is the flash memory that the storage unit among Fig. 2 is used Fig. 3 (a), and the operating characteristic of table 1B then is the flash memory that the storage unit among Fig. 2 is used Fig. 3 (b).

Table 1A

Table 1B

As follows at table 1A and the abbreviation meaning of table among the 1B: Vs reads and the source voltage when erasing, and its voltage is very low, almost is 0V; Ve is F-N needed control gate (CG) voltage of erasing when wearing tunnel, and its value approximately is 15V according to employed processing procedure decision; Vp is the sequencing voltage that is applied to storage transistor drain electrode (or source electrode of close floating gate), and its value almost is 12V according to employed processing procedure decision; Vcgp is a control gate sequencing voltage, should could open the selection transistor, so Vcgp approximately is 2V than threshold voltage (similar 1.5V) height of the storage transistor of waiting to erase; Vdp0 is the drain electrode sequencing voltage that is applied to the storage transistor of selection, purpose is being carried out sequencing (be about to electronics and deposit floating gate (FG) in) with logic input data " 0 ", its value is 12V (Vp) or 0V (Vs) by the structures shape of storage array and storage unit; Vdp1 is the drain electrode sequencing voltage that is applied to the storage transistor of selection, purpose is being carried out sequencing (promptly electronics not being deposited floating gate) with logic input data " 1 ", with program suppress equivalent in meaning, its value is identical with the non-selection bit line of storage transistor, by the structures shape of storage array and storage unit, be 0V (Vs) or 5V (Vcc); Vcgr is that control gate reads bias voltage, and it is worth according to processing procedure and design decision, approximately is 4V; Vdr is that bias voltage is read in drain electrode, greatly between 1.5 to 2V; Vcc is a power supply supply voltage, and it is worth according to processing procedure and design decision, approximately is 5V.

The memory array structure of Fig. 3 (a) and Fig. 3 (b) has a problem, even being exactly part data in the big block, that does not need to revise, the modification of storage unit is the unit with whole big block (i.e. row) still, so still write storage unit again of the data that need revise not, whole process is not only wasted power supply and is also lost time.

United States Patent (USP) the 5th, 812, provide a kind of feasible solution to the problems referred to above No. 452, in this piece patent, each storage unit comprises two transistors: select transistor and a storage transistor for one, select the series connection of transistor AND gate storage transistor, in storage array, the storage unit of predetermined quantity is divided into several blocks, and by using a zone-block selected transistor, we can utilize mode access or the modification storage unit of block to block.

But United States Patent (USP) the 5th, 812, No. 452 solution make the bit of each storage all need two transistors, and this can increase the size of storage array.

We wish and can not need to allow the bit of each storage contain two transistors and increase under the long-pending condition of multiaspect so, with less than the mode of the big block read-only storage array of sequencing electric erazable programmable again.

Summary of the invention

The purpose of this invention is to provide a kind of bit that does not need to allow each storage and all contain two transistors and increase under the long-pending condition of multiaspect so, have with less than the mode of the big block quickflashing EEPROM (Electrically Erasable Programmable Read Only Memo) of the read-only storage array of sequencing electric erazable programmable again.

A kind of quickflashing eeprom array is provided according to an aspect of the present invention, has a plurality of storage group, be characterized in, respectively comprise in this storage group: a plurality of storage unit; One block selection wire provides group voltage through coupling with selectivity; One line decoder and multi-path converter circuit are in order to control this a block selection wire and a bit line; One first selects transistor, and it is to be coupled between this block selection wire and this storage unit; One second selects transistor, and it is to be coupled between this first selection transistor, this storage unit and the emitter connection; One first character line is in order to control this first selection transistor; One second character line is in order to control this second selection transistor; And a column decoder circuit, in order to control this first and this second character line be connected with this emitter.

A kind of method of the quickflashing eeprom array of erasing is provided according to a further aspect of the invention, this quickflashing EEPROM (Electrically Erasable Programmable Read Only Memo) comprises a plurality of storage unit, many character lines, a plurality of first selection transistors, a plurality of second selection transistor, many emission polar curves and many block selection wires, these a plurality of storage unit all have an emitter, be characterized in, this method may further comprise the steps: should a plurality of storage unit be divided into several groups, and be arranged in ordered series of numbers and number row; Link in this ordered series of numbers each row with these several character lines in two corresponding character lines; Link a corresponding block selection wire in this number each row in capable and these several block selection wires; With described a plurality of first one of selecting in the transistors, be coupled in that all belong to together between the row person in these many block selection wires one and these a plurality of storage unit; With described a plurality of second one of selecting in the transistors, be coupled in this a plurality of first select to belong to together among in transistors one, these a plurality of storage unit a row person, and this emitter in belong to together between the row person; With the voltage of erasing a block selection wire in these several block selection wires is charged; And use two in these several character lines to select the character line, send this voltage of erasing with control and select group to one in these several storage unit.Utilize this mode, each group storage unit only needs two to select just can erase one group storage unit of transistors, if each group is the bit group of eight bits, then needed selection number of transistors has only United States Patent (USP) the 5th, 812, No. 452 prior art needed 1/4th.

For clearer understanding purpose of the present invention, characteristics and advantage, preferred embodiment of the present invention is elaborated below in conjunction with accompanying drawing.

Description of drawings

Fig. 1 (a) is the cross sectional side view that traditional floating gate is worn tunnel oxidation storage unit;

Fig. 1 (b) is that floating gate is worn the expression symbol of tunnel oxidation storage unit among Fig. 1 (a);

Fig. 2 (a) is the cross sectional side view of traditional flash cell;

Fig. 2 (b) is the expression symbol of flash memory cell among Fig. 2 (a);

Fig. 3 (a) is the synoptic diagram of the first conventional store array;

Fig. 3 (b) is the synoptic diagram of the second conventional store array;

Fig. 4 (a) is the synoptic diagram according to the storage array of the embodiment of the invention; And

Fig. 4 (b) is the synoptic diagram of storage array according to another embodiment of the present invention.

Embodiment

Fig. 4 (a) illustrates the storage array 100 according to the embodiment of the invention, storage array 100 comprises several groups 102 storage unit 60, each group 102 is the bit group of eight bits among Fig. 4 (a), so comprised 8 storage transistor, the group size that other can be arranged according to design standards, each group 102 is organized into row and column, and according to design standards, storage array 100 can comprise any amount of row and column.

The storage array 80 of storage array 100 and Fig. 3 (a) has a lot of resemblances, horizontal access as control groups 102 such as character line WL0, WL1, bit line BL0, BL1 etc. provide the access of each bit in the group 102, emission polar curve SL0, SL1 etc. provide emitter to connect, as for the function of sensor amplifier 86, output buffer 88, input buffer 90 then with the front narrate the same.

But the present invention still has some different with the storage array 80 of Fig. 3 (a), and one of them is to have increased zone-block selected transistor (as M00A, M01A or the like, common name MA) and block cancellation (deselect) transistor (as M00B, M01B or the like, common name MB); Second different place be increased character cancellation line (as WL0, WL1 or the like); The 3rd different place is to have increased block selection wire (as BS0, BS1 or the like); These change the change that has also comprised column address decoder 104 and row address decoder 106.

Zone-block selected transistor MA is coupled between the block selection wire BS and the sub-line of control gate (subline) 108 of each group 102, the coupling of the flash memory cell control gate of sub-line 108 of each bar control gate and corresponding group 102.

Block cancellation transistor MB is coupled between zone-block selected transistor MA and the emission polar curve SL, and block cancellation transistor can Coupling Control grid line 108 and emission polar curve SL like this.

Character line WL control zone-block selected transistor MA, and character cancellation line WL control block cancellation transistor MB, character line WL provides level (row) access of storage array 100, during computing, provide specific character cancellation line WL be the logic level that is used to provide with corresponding character line WL complementation, for instance, if the logic level of WL0 is " height ", then the position standard of WL0 is " low ", so the sub-line 108 of each control gate and corresponding block selection wire BS or corresponding emission polar curve SL coupling.

Block selection wire BS provides vertical (OK) access of storage array 100, therefore, can carry out access to a particular block 102 in conjunction with specific a character line WL and a block selection wire BS, comprise read, sequencing and erasing.

Fig. 4 (b) illustrates storage array 100b according to another embodiment of the present invention, storage array 100b is similar with the storage array 100 of Fig. 4 (a), do not exist together and have only and to form collector (BL is connected with the bit line) near the FS zone of storage array 60 floating gates, storage unit 102b is the same with storage unit 102, also has sensor amplifier 86, output buffer 88, input buffer 90 too, the main difference that forms storage unit 60 collectors again is that column address decoder 104b and row address decoder 106b offer character line WL, character cancellation line WL, block selection wire BS, the control voltage of emission polar curve SL is different with the control voltage that row address decoder 106 is provided with the column address decoder 104 of Fig. 4 (a).

How table 2A and table 2B explanation column address decoder 104 (104b) and row address decoder 106 (106b) control bit line BL, character line WL, character cancellation line WL, block selection wire BS, emission polar curve SL, the operating characteristic of table 2A is the flash memory 100 that the storage unit among Fig. 2 is used Fig. 4 (a), and the operating characteristic of table 2B then is the flash memory 100b that the storage unit among Fig. 2 is used Fig. 4 (b).

Abbreviation meaning in showing 2A and showing 2B is identical with the discussion part of top relevant table 1A and table 1B, increase abbreviation a: Vwle in addition and be the character line voltage of erasing, its value should add more than or equal to Ve selects transistorized threshold voltage Vt, suppose the similar 2V of Vt, the similar 17V of Vwle then, Vwle and Ve can be 17V simultaneously, and so the virtual voltage at the storage transistor control gate enough provides F-N to wear tunnel (needing 15V according to appointment).

Table 2A

Table 2B

As mentioned above, two of 60 needs of each group 102 (102b) storage unit are selected transistor (MA and MB), whole group 102 (102b) storage unit 60 of just can erasing, if each group is the bit group of eight bits, needed selection number of transistors has only known techniques United States Patent (USP) the 5th, 812, No. 452 required 1/4th, can reduce the required space of storage array 100 (100b) like this.

According to another embodiment, we can be combined into the emission polar curve SL of adjacent two array storage units 102 (102b) an emission polar curve, give an example, in the storage array 100 of Fig. 4 (a), emission polar curve SL0 and SL1 can be combined into an emission polar curve, such combination can further reduce the required space of storage array 100 (100b).Consult table 2B, please note that such combination does not have negative influence to storage array 100b, because the voltage of emission polar curve SL always is Vs (0V); Consult table 2A, please note that sequencing voltage Vp is different with emitter voltage Vs, thus when sequencing storage array 100, can make non-selected adjacent column produce the more disturbance that writes, this in conjunction with the steering logic that needs change column address decoder 104 (104b).

According to another embodiment, we can be combined into a shared emitter with all emission polar curve SL, voltage all is Vs forever, please note the disturbance that writes above-mentioned, so present embodiment relatively is applicable to storage array 100b, do not need column address decoder 104b to control shared emitter in this embodiment, this can further reduce the demand of steering logic, and reduces the required space of storage array 100b.

Claims

1. quickflashing eeprom array has a plurality of storage group, it is characterized in that, respectively comprises in this storage group:

A plurality of storage unit;

One block selection wire provides group voltage through coupling with selectivity;

One line decoder and multi-path converter circuit are in order to control this a block selection wire and a bit line;

One first selects transistor, and it is to be coupled between this block selection wire and this storage unit;

One second selects transistor, and it is to be coupled between this first selection transistor, this storage unit and the emitter connection;

One first character line is in order to control this first selection transistor;

One second character line is in order to control this second selection transistor; And

One column decoder circuit, in order to control this first and this second character line be connected with this emitter.

2. quickflashing eeprom array as claimed in claim 1 is characterized in that, this storage group comprises eight these storage unit.

3. quickflashing eeprom array as claimed in claim 1 is characterized in that, this storage unit comprises a floating gate and a control gate.

4. quickflashing eeprom array as claimed in claim 1 is characterized in that, this a plurality of storage group is arranged in multiple row or multirow, and respectively this storage unit all links with a bit line and an emission polar curve.

5. quickflashing eeprom array as claimed in claim 1 is characterized in that:

These a plurality of storage unit respectively comprise a control gate;

This first selection transistor comprises:

One first terminal, itself and this block selection wire is coupled; And

One second terminal, itself and this control gate is coupled.

6. quickflashing eeprom array as claimed in claim 1 is characterized in that,

These a plurality of storage unit respectively comprise a control gate;

This second selection transistor also comprises:

One first terminal, it is connected coupling with this emitter; And

One second terminal, itself and this control gate is coupled.

7. quickflashing eeprom array as claimed in claim 1 is characterized in that, this this first character line of first selection transistor AND gate links, and this this second character line of second selection transistor AND gate links.

8. quickflashing eeprom array as claimed in claim 1 is characterized in that, also comprises:

This column decoder circuit provides one first voltage to this first character line in order to selectivity, and provides one second voltage to this second character line.

9. quickflashing eeprom array as claimed in claim 8 is characterized in that, this column decoder circuit is also in order to provide an emitter voltage to connect to this emitter.

10. quickflashing eeprom array as claimed in claim 8, it is characterized in that, this column decoder circuit is also in order to this first selects transistor via this first character line traffic control, and this second selects transistor via this second character line traffic control.

11. quickflashing eeprom array as claimed in claim 1 is characterized in that, also comprises an emission polar curve, links with this emitter that respectively is somebody's turn to do respectively this storage unit in the group that stores in the group.

12. quickflashing eeprom array as claimed in claim 1 is characterized in that, also comprises an emission polar curve, links with the emitter that respectively is somebody's turn to do respectively this storage unit in two groups that store in the group.

13. the method for the quickflashing eeprom array of erasing, this quickflashing EEPROM (Electrically Erasable Programmable Read Only Memo) comprises a plurality of storage unit, many character lines, a plurality of first selection transistors, a plurality of second selection transistor, many emission polar curves and many block selection wires, these a plurality of storage unit all have an emitter, it is characterized in that this method may further comprise the steps:

Should a plurality of storage unit be divided into a plurality of groups, be arranged in the storage group of multiple row and the storage unit of multirow;

Link two corresponding character lines in each row and these the many character lines in the storage group of this multiple row;

Link a corresponding block selection wire in each row and these many block selection wires in the storage unit of this multirow;

With described a plurality of first one of selecting in the transistors, be coupled in that all belong to together between the row person in these many block selection wires one and these a plurality of storage unit;

With described a plurality of second one of selecting in the transistors, be coupled in this a plurality of first select to belong to together among in transistors one, these a plurality of storage unit a row person, and this emitter in belong to together between the row person;

With the voltage of erasing a block selection wire in these many block selection wires is charged; And

Use two in these many character lines to select the character line, send this voltage of erasing with control and select group to one in these a plurality of storage unit.