CN109802710A

CN109802710A - A kind of method and device realizing code book and generating

Info

Publication number: CN109802710A
Application number: CN201711137730.6A
Authority: CN
Inventors: 卞青
Original assignee: Shenzhen ZTE Microelectronics Technology Co Ltd
Current assignee: Shenzhen ZTE Microelectronics Technology Co Ltd
Priority date: 2017-11-16
Filing date: 2017-11-16
Publication date: 2019-05-24
Anticipated expiration: 2037-11-16
Also published as: CN109802710B

Abstract

A kind of realization method for generating codebooks and device, comprising: default discrete Fourier transform (DFT) base infrastructure elements that storage generates offline；The addressable address of DFT base infrastructure elements is determined according to code book related information, and DFT base infrastructure elements are carried out to make operable enabled information；Addressable address is exported according to preset address enable signal；DFT base infrastructure elements are taken out according to the addressable address of output, carry out enabled operation according to DFT base infrastructure elements of the enabled information of output to taking-up, and the data after enabled operation are stored to preset DFT basic sequence storage region；Twiddle factor is decomposed, and according to the data for obtaining each layer main beam and auxiliary wave beam；It is added with the main beam of acquisition and the data of auxiliary wave beam, and the data obtained after being added with are stored as code book.The embodiment of the present invention simplifies DFT base index and complex operation, reduces the complexity of code book generation, reduces memory space expense.

Description

Method and device for generating codebook

Technical Field

The present disclosure relates to, but not limited to, link adaptation techniques, and more particularly, to a method and apparatus for implementing codebook generation.

Background

Long term evolution advanced (LTE-a) systems have employed large-scale antenna arrays and beamforming techniques to improve system performance. The beamforming technology based on the large-scale antenna array requires that Channel State Information (CSI) can be accurately obtained at a transmitting end, and an optimal beam is selected according to the CSI for data transmission. The CSI needs to be fed back to the transmitting end through User Equipment (UE) at the receiving end. And the UE obtains a channel coefficient matrix H and a noise coefficient No by utilizing channel estimation, selects the CSI most matched with the current channel according to a set optimal criterion, and finally reports the CSI to the base station.

Before LTE-a release 14, the CSI is calculated and selected by the UE assuming that its current transmission mode is in single user multiple input multiple output (SU-MIMO) mode; if a base station needs to perform multi-user multiple input multiple output (MU-MIMO) transmission according to feedback of a current UE, the base station needs to determine and combine channel states of the UEs, and then recalculate a Rank Indicator (RI), a Precoding Matrix Indicator (PMI), and a Channel Quality Indicator (CQI) used by the MU-MIMO, which often causes a reduction in performance of the MU-MIMO. In order to solve the above problems, LTE-a release 14 proposes an enhanced codebook for large-scale antenna array MU-MIMO, which mainly uses a 2-beam linear combination codebook, and UE jointly selects RI and PMI according to the codebook, and then further calculates a corresponding CQI, and feeds back the CQI to the base station. The activation of the codebook can effectively improve the MU-MIMO transmission performance, but the number of codebooks in the enhanced linear combination codebook set is huge, and 458752 one-layer codebooks and 29360128 two-layer codebooks exist under one configuration of only 32 antenna ports. Such a complicated codebook causes difficulties in generating precoding on the UE side.

For the problem of precoding generation, the related art provides some solutions; the first mode is to generate a needed pre-coding matrix on line in real time according to the requirement of a protocol, the method is easy to implement, but the generation of the pre-coding matrix needs to carry out Discrete Fourier Transform (DFT) base generation (exponential operation) for multiple times, complex matrix multiplication and addition and other calculations every time, and the calculation complexity is very high by comprehensively considering the number of codebooks; another way is to use all off-line codebook storage, which only needs to read the corresponding codebook from the memory without extra computation, but the storage space required by this method is very large (more than 1 gigabit (GBytes)).

Disclosure of Invention

The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

The embodiment of the invention provides a method and a device for generating a codebook, which can simplify DFT base index and complex number operation, reduce the complexity of codebook generation and reduce the cost of storage space.

The embodiment of the invention provides a method for generating a codebook, which comprises the following steps:

storing preset Discrete Fourier Transform (DFT) basic elements generated offline;

determining an addressing address of the DFT basic element according to the codebook association information, and enabling information for enabling the DFT basic element;

outputting an addressing address according to a preset address enabling signal; wherein, the output addressing address is used for taking out DFT basic elements used for generating a codebook;

extracting DFT basic elements according to the output addressing address, performing enabling operation on the extracted DFT basic elements according to the output enabling information, and storing the data after enabling operation into a preset DFT basic sequence storage area;

decomposing the twiddle factors, and performing phase rotation on the data after enabling operation according to the twiddle factors obtained by decomposition to obtain data of each layer of main beams and auxiliary beams;

adding the obtained data of the main beam and the auxiliary beam repeatedly, and storing the data obtained after adding as a codebook;

wherein the addressing address of the DFT base element comprises: addressing addresses of the DFT-based basic elements of the main beam and addressing addresses of the DFT-based basic elements of the auxiliary beam;

the enabling operation includes: exchange between real and virtual and/or reverse.

Optionally, the preset DFT-based basic elements include:

1680 DFT basis of the first quadrant; and DFT multiplication of the first quadrantA value of (d);

wherein, each DFT basic element is stored by a corresponding address; each address contains 1 byte for storing the real part of an element and 1 byte for storing the imaginary part of an element.

Optionally, the preset DFT-based basic elements are stored according to the following addresses:

the DFT basis for the first quadrant is stored at an address determined according to the following sequence:

DFT multiplication of the first quadrantIs stored at an address determined according to the following sequence:

optionally, the codebook associated information includes part or all of the following information:

horizontal oversampling factor O1, vertical oversampling factor O2, antenna horizontal port number N1, antenna vertical port number N2, first-stage codebook index 1first PMI1, first-stage codebook index 2first PMI2, first-stage codebook index 3first PMI3, and power factor configuration information p.

Optionally, the outputting an address according to a preset address enable signal includes:

controlling one or more accumulators according to a preset address enable signal to output the addressing address;

and the addressing address is output according to the sequence that the main beam and the auxiliary beam are crossed one by one.

Optionally, the decomposing twiddle factor includes:

obtaining the twiddle factors according to the second-level codebook index second PMI decomposition of each input layer;

wherein the twiddle factor comprises: the main beam contains phase rotation factors of the upper and lower portions, and the secondary beam contains phase rotation factors of the upper and lower portions.

On the other hand, an apparatus for implementing codebook generation in an embodiment of the present invention includes: a first unit, a second unit, a third unit, a fourth unit, a fifth unit and a sixth unit; wherein,

the first unit is used for: storing preset DFT basic elements generated offline;

the second unit is used for: determining an addressing address of the DFT basic element according to the codebook association information, and enabling information for enabling the DFT basic element;

a third unit for: outputting an addressing address according to a preset address enabling signal; wherein, the output addressing address is used for taking out DFT basic elements used for generating a codebook;

the fourth unit is used for: extracting DFT basic elements according to the output addressing address, performing enabling operation on the extracted DFT basic elements according to the output enabling information, and storing the data after enabling operation into a preset DFT basic sequence storage area;

the fifth unit is used for: decomposing the twiddle factors, and performing phase rotation on the data after enabling operation according to the twiddle factors obtained by decomposition to obtain data of each layer of main beams and auxiliary beams;

the sixth unit is configured to: adding the obtained data of the main beam and the auxiliary beam repeatedly, and storing the data obtained after adding as a codebook;

Optionally, the preset DFT-based basic elements include:

1680 DFT base of first quadrant(ii) a And DFT multiplication of the first quadrantA value of (d);

Optionally, the third unit is specifically configured to:

Optionally, the fifth unit for decomposing the twiddle factor includes:

In still another aspect, an embodiment of the present invention further provides a computer storage medium, where computer-executable instructions are stored in the computer storage medium, and the computer-executable instructions are configured to perform the method described above.

In another aspect, an embodiment of the present invention further provides a terminal, including: a memory and a processor; wherein,

the processor is configured to execute program instructions in the memory;

the program instructions read on the processor to perform the following operations:

storing preset DFT basic elements generated offline;

Compared with the related art, the technical scheme of the application comprises the following steps: storing preset Discrete Fourier Transform (DFT) basic elements generated offline; determining an addressing address of the DFT basic element according to the codebook association information, and enabling information for enabling the DFT basic element; outputting an addressing address according to a preset address enabling signal; extracting DFT basic elements according to the output addressing address, performing enabling operation on the extracted DFT basic elements according to the output enabling information, and storing the data after enabling operation into a preset DFT basic sequence storage area; decomposing the twiddle factors and obtaining data of the main beam and the auxiliary beam of each layer; and adding the obtained data of the main beam and the auxiliary beam repeatedly, and storing the data obtained after adding as a codebook. The embodiment of the invention simplifies the DFT base index and complex number operation, reduces the complexity of codebook generation and reduces the storage space overhead.

Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.

Drawings

The accompanying drawings are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the example serve to explain the principles of the invention and not to limit the invention.

FIG. 1 is a flowchart of a method for implementing codebook generation according to an embodiment of the present invention;

FIG. 2 is a block diagram of an apparatus for implementing codebook generation according to an embodiment of the present invention;

FIG. 3 is a schematic diagram of an alternative circuit configuration to which the present invention is applied;

FIG. 4 is a timing diagram illustrating an exemplary address enable signal applied in the present invention;

FIG. 5 is a block diagram of another alternative circuit to illustrate the application of the present invention;

fig. 6 is a block diagram showing another alternative circuit to which the present invention is applied.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, embodiments of the present invention will be described in detail below with reference to the accompanying drawings. It should be noted that the embodiments and features of the embodiments in the present application may be arbitrarily combined with each other without conflict.

The steps illustrated in the flow charts of the figures may be performed in a computer system such as a set of computer-executable instructions. Also, while a logical order is shown in the flow diagrams, in some cases, the steps shown or described may be performed in an order different than here.

Fig. 1 is a flowchart of a method for generating a codebook according to an embodiment of the present invention, as shown in fig. 1, including:

step 100, storing preset Discrete Fourier Transform (DFT) basic elements generated offline;

optionally, the preset DFT-based basic elements in the embodiment of the present invention include:

Optionally, in the embodiment of the present invention, a preset DFT-based basic element is stored according to the following address:

step 101, determining an addressing address of a DFT basic element according to codebook associated information, and enabling information for enabling the DFT basic element;

Optionally, the codebook associated information in the embodiment of the present invention includes part or all of the following information:

Step 102, outputting an addressing address according to a preset address enabling signal; wherein, the output addressing address is used for taking out DFT basic elements used for generating a codebook;

optionally, the outputting an address according to a preset address enable signal in the embodiment of the present invention includes:

The method for outputting the addressing address according to the sequence that the main beam and the auxiliary beam are crossed one by one comprises the following steps: the addressing addresses are output in the order of the main beam first element address, the auxiliary beam first element address, the main beam second element address, the auxiliary beam second element address … …, the auxiliary beam last element address.

103, extracting DFT basic elements according to the output addressing address, enabling the extracted DFT basic elements according to the output enabling information, and storing the data after enabling operation in a preset DFT basic sequence storage area;

step 104, decomposing the twiddle factors, and performing phase rotation on the data after enabling operation according to the twiddle factors obtained through decomposition to obtain data of each layer of main beams and auxiliary beams;

optionally, decomposing the twiddle factor according to an embodiment of the present invention includes:

It should be noted that the decomposition method of the twiddle factor according to the embodiment of the present invention includes: the method comprises the steps of obtaining a PMI according to an LTE protocol second PMI design principle; namely, the highest 2bits, the middle 2bits and the lowest 2bits of the second PMI are taken as three twiddle factors respectively.

And 105, adding the obtained data of the main beam and the auxiliary beam repeatedly, and storing the data obtained after adding repeatedly as a codebook.

The embodiment of the invention simplifies the operation of DFT base index and complex number, and can generate the corresponding codebook only by a small amount of addition and multiplication, thereby reducing the complexity of codebook generation and reducing the storage space overhead.

Fig. 2 is a block diagram of a device for generating a codebook according to an embodiment of the present invention, and as shown in fig. 2, the device includes: a first unit, a second unit, a third unit, a fourth unit, a fifth unit and a sixth unit; wherein,

optionally, the third unit in the embodiment of the present invention is specifically configured to:

optionally, the fifth unit in the embodiment of the present invention, configured to decompose the twiddle factor, includes:

In still another aspect, an embodiment of the present invention further provides a computer storage medium, where computer-executable instructions are stored in the computer storage medium, and the computer-executable instructions are configured to execute the method for implementing codebook generation as claimed in the above claims.

the processor is configured to execute program instructions in the memory;

storing preset DFT basic elements generated offline;

The method of the embodiment of the present invention is described in detail below by using application examples, which are only used for illustrating the present invention and are not used for limiting the protection scope of the present invention. Application example 1

The precoding coefficient of the application example includes: 32 transmission antenna ports with codebook oversampling parameters of horizontal direction oversampling factor O1 being 4 and vertical direction oversampling factor O2 being 4, where the number of antenna horizontal ports N1 being 4 and the number of antenna vertical ports N2 being 4 are configured for two-dimensional antenna, and the first layer first stage codebook index 1(first PMI1 i)₁₁10, first layer second level codebook index 2(first PMI2) i₁₂12, first layer third level codebook index 3first PMI3i₁₃1, p 1, 2-layer first-layer second-level codebook index second-level PMI i_2,127, 2-layer second-level codebook index second PMI i_2,2＝37。

The application example firstly stores preset DFT basic elements generated offline, and comprises the following steps: 1680 DFT basis of the first quadrant; and the DFT base element of the first quadrant multiplied byA value of (d); each DFT basic element is stored by a corresponding address; each address contains 1 byte (byte) for storing the real part of the base element and 1 byte for storing the imaginary part of the base element.

The addressing address range used for storing DFT basic elements required for generating the codebook in the application example can include [ 0-3359 ]]The addressing address can be determined by design by a person skilled in the art; the addressing address may be determined by: all possible values [1, 2, 3, 4, 5, 6, 7, 8, 10, 12, 14, 16 ] according to N1/N2]The minimum common multiple of N1 and N2 is 1680, and all possible values of O1/O2 are obtained [4]Multiplying by the least common multiple to obtain 6720, i.e., 6720 complex numbers are required to store all N1/N2/O1/O2 combinationsAll possible values of the desired DFT basis are stored by taking the basis element of 1/4 of the first quadrant according to the quadrant symmetry characteristic of the complex number, i.e. 6720 x 1/4 x 1680, and in order to avoid the complex multiplication which may occur when the power factor index p is 2, the DFT basis element of the first quadrant is multiplied by the power factor of p 2 in advanceAnd storing, namely adding 1680 stores;

the second unit and the third unit in this application example pair embodiment may be implemented by the following optional circuits, and fig. 3 is a schematic diagram of a composition structure of the optional circuit in the application example pair embodiment of the present invention, as shown in fig. 3, including:

the first module 301: for input based on N1 ═ 4, N2 ═ 4, and first PMI3i₁₃1, obtaining d1/d2 values and output step length S accumulated each time from corresponding N1/N2 step length memories and d1/d2 memories_N1、S_N2(ii) a Wherein the step value S is output_N1、S_N2Multiplying the sum by first PMI1 or first PMI2 to obtain an accumulation step length; table 1 shows input values of N1 or N2 and corresponding memory output values in the N1 or N2 step size memory according to the embodiment of the present invention, where table 1 is designed based on the following principles: all possible values [1, 2, 3, 4, 5, 6, 7, 8, 10, 12, 14, 16 ] according to N1/N2]The minimum common multiple of N1 and N2 is 1680, namely, first PMI1i corresponds to different configurations of N1/N2₁₁Every increment of N1 corresponds to a read address of I₁₁Increase 1680, first PMI2 i₁₂Every increment of N2 corresponds to a read address i₁₂1680 is added, so the output step size corresponding to different N1 values is 1680/N1, and the output step size corresponding to different N2 values is 1680/N2;

TABLE 1

The content stored in the d1/d2 memory of the application example can beThe contents specified in the LTE protocol are shown in Table 2 as N1, N2, i₁₃As input values and corresponding memory output values d1, d2 are:

TABLE 2

The second module 302 is configured to: after the output step length is obtained through the first module 301, the obtained output step length and d1/d2 are processed through a multiplier to obtain a main beam accumulation step length and an auxiliary beam compensation step length:

S_{N1_add}＝i₁₁*S_N1，S_{N2_add}＝i₁₂*S_N2；Off_N1＝d1*4*S_N1，Off_N2＝d2*4*S_N2。

wherein, the main beam accumulation step is the output step first PMI1i₁₁Or main beam accumulation step size (output step size) first PMI2 i₁₂For example, as the d10 output step size represents that the first PMI1 or the first PMI2 is increased by a value which is required to be increased by a selected addressing address corresponding to 1, and the main beam accumulation step size under the determined first PMI1 or first PMI2 is the multiplication of the two, the difference of storage addresses between elements of the main beam in the horizontal direction or the vertical direction is represented. Similarly, the auxiliary beam compensation step is output step 4 d1(d 2); wherein 4 represents the oversampling multiple in the horizontal/vertical direction, d1/d2 represents the position difference between the auxiliary beam and the main beam in the horizontal/vertical direction, and the auxiliary beam compensation step represents the storage address difference between the elements with the same sequence numbers of the auxiliary beam and the main beam in the horizontal/vertical direction.

The third module 303 is configured to: outputting an address enable signal; the address enable signal in the embodiment of the present invention may include the following three types: the first enable signal, the second enable signal and the main and auxiliary enable signals; wherein the first enable signal controls S_{N1_add}And Off_N1Accumulation of (1), once per enable accumulation; the second enable signal controls S_{N2_add}And Off_N2Accumulation of (1), once per enable accumulation; enabling the second enable signal every N2 times, enabling the first enable signal once; the embodiment of the invention can control the output of the addressing address through the main and auxiliary enabling signals, and the addressing address comprises a main beam addressing address or an auxiliary beam addressing address; for example, a main/auxiliary enable of 0 indicates outputting the main beam addressing address, and the auxiliary beam compensation value is 0, a main/auxiliary enable of 1 indicates outputting the auxiliary beam addressing address, and the auxiliary beam compensation value is Off_N1+Off_N2。

Fig. 4 is a timing diagram illustrating an exemplary address enable signal applied in the present invention, and as shown in fig. 4, the address enable signal may be output by a counter at a desired interval. After generating the address of the first element of the main beam by the main and auxiliary enable signals, generating the address of the first element of the auxiliary beam, then enabling the second enable signal, and performing S once_{N2_add}And Off_N2Accumulation of (1); then, the second element of the main and auxiliary beams is generated, and so on until the fourth element of the main and auxiliary beams is generated, then the second enabling signal and the first enabling signal are enabled, and S is carried out once_{N2_add}And Off_N2Sum of S_{N1_add}And Off_N1The fifth element of the main and auxiliary beams (main beam and auxiliary beam) is generated, and the generation of the DFT-based basic element is completed according to the above method until the sixteenth element of the main and auxiliary beams is generated.

The fourth module 304 is configured to: addressing an addressing address obtained according to the address enabling signal through a residual module to obtain an actual sequence addressing address; the remainder taking is to ensure that the value of the addressing address is in the range [ 0-6719 ] which can be represented by the DFT base, and the remainder taking operation can be realized based on the existing principle.

The fifth module 305 is configured to: inputting the obtained actual sequence addressing address into a comparator to generate enabling information for enabling the DFT basic element; the application example compares the output actual serial addressing addresses with 1680/3360/5040 through comparators respectively, and uses the output of the comparators to obtain each enable signal through combinational logic, namely enable information for enabling the DFT basic elements; specific correspondence relationship can be shown in table 3, and the embodiment of the present invention obtains the enable signal by using the principle of quadrant conversion. If the actual sequence address <1680, this indicates that the value corresponding to the current address is in the first quadrant, and the DFT memory stores the value in the first quadrant as well, so no swap or inversion is required. If between 1680 and 3360, it means that the value corresponding to the current address is in the second quadrant, pi/2 needs to be subtracted in phase to convert to the value corresponding to the first quadrant, which is equivalent to real-imaginary swapping and then inverting the real part of the value in the first quadrant, so it needs to enable real-imaginary swapping and real-part inverting, similarly between 3360 and 5040 and greater than 5040, and it is equivalent to the third and fourth quadrants, which needs real-part inverting/imaginary inverting of the value corresponding to the first quadrant, and real-swapping/imaginary inverting operations to convert.

TABLE 3

The sixth module 306 is configured to: the read address of the output DFT base element (the address for taking out the DFT base element used to generate the codebook) is obtained by quadrant address correction and power factor address correction. The quadrant address correction value is obtained by quadrant indication, and the actual sequence address and the address correction value are added to obtain a first quadrant address, and the corresponding relationship between the quadrant indication and the correction value can be shown in table 4:

quadrant indication	Address correctionValue of
		0	0
1	-1680
		2	-3360
3	-5040

TABLE 4

And adding the first quadrant address and a power factor correction value to obtain a final output address, wherein the power factor correction value is 1680 only when the main and auxiliary enable is 1 (auxiliary beam output) and P is 2, and the other conditions are 0.

The application example extracts DFT basic elements from stored preset DFT basic elements according to the output addressing addresses of the DFT basic elements; enabling the input data according to the output first enabling information and the extracted DFT base, and storing the enabled input data according to the addressing address; wherein the enabling operation comprises: exchange between real and virtual and/or reverse. The fourth unit in the embodiment of the present invention is implemented by the following optional circuit, and fig. 5 is a block diagram of another optional circuit in an application example of the present invention, as shown in fig. 5, including:

the seventh module 501 is configured to: dividing input DFT basic elements into real parts and imaginary parts and storing the real parts and the imaginary parts respectively;

the eighth module 502 is configured to: performing data exchange operation of DFT base elements according to the enabling information, if the real-virtual exchange enabling is 1, selecting data 1 by the two data at the moment, and completing the exchange of the virtual part and the real part; if the fruit virtual swap enable is 0, then two data selects their select data 0, and the real and imaginary parts are not swapped. And performing negation operation according to the enabling information, and performing negation processing on the data input into the inverter if negation enabling is 1.

A ninth module 503 is configured to: outputting a corresponding addressing address according to the read-write enable; when writing enable is carried out, an addressing address is output through the output of the counter, the counter triggers counting according to the falling edge of the main and auxiliary enable signals, namely, after one main beam data and one auxiliary beam data are processed, the writing address is added with 1;

if the main beam memory and the auxiliary beam memory work in a writing mode, and if the main beam memory and the auxiliary beam memory work in a writing mode, the data are stored into a corresponding address of the main beam memory at the moment; if the main and auxiliary enable is 1, the data output by the auxiliary beam memory is sequentially shifted/cleared or not processed according to the value of the power factor p, if p is 2/3, no additional processing is needed, if p is 1, the data is right-shifted by 1 bit (which is equal to divide by 2), if p is 0, the data is cleared, and the processed auxiliary beam data is stored in the corresponding address of the auxiliary beam memory.

In this application example, each time the counter module completes processing one datum, 1 is added, if the counter output is less than N1 × N2, the counter output is the main and auxiliary beam (main beam and auxiliary beam) memory read address; if the counter output is greater than or equal to N1N2, the counter output is required to be subtracted by N1N2 to obtain a main beam memory read address and an auxiliary beam memory read address; here, N1 × N2 is used as a contrast parameter, mainly according to the requirement of the LTE protocol codebook, each layer of codebook is divided into two polarization directions, each polarization direction contains N1 × N2 codebook elements, the number read by the read address counter when each layer of codebook is generated is 2 × N1 × N2, that is, it is necessary to read two times of main/auxiliary beam memories to generate codebooks in polarization direction 0 and polarization direction 1, so that when the read address counter technology is less than N1 × N2, it is directly output as the read address of the main/auxiliary beam memory, when it is greater than or equal to N1 × N2, it is equivalent to reading the main/auxiliary beam memory for the second time, and since the address range of the main/auxiliary beam memory is [0, N1N2-1], it is necessary to subtract N1 × N2 and output the address at this time.

The fifth unit of the embodiment of the present invention is configured to: decomposing the twiddle factor, and generating corresponding negation and exchange enabling according to the twiddle factor; respectively carrying out phase rotation on the input data after enabling operation according to the negation and the exchange enabling to obtain data of each layer of main beams and auxiliary beams; specifically, according to the inputted second PMI i of a certain layer₂Decomposing the required rotation factor q of the layer, generating corresponding negation and exchange enabling according to q, and respectively processing the input data of the main and auxiliary beams according to the enabling; the sixth unit is configured to: after the corresponding primary and secondary beam data are obtained, the two are added to obtain final codebook data, the fifth unit and the sixth unit can be implemented by an optional circuit, fig. 6 is a block diagram of another optional circuit of an application example of the present invention, as shown in fig. 6, including:

the tenth module 601 is configured to: decomposing to obtain a twiddle factor; the twiddle factor q of the application example needs to be respectively selected aiming at a main beam and an auxiliary beam, and is designed based on the existing LTE protocol codebook design principle, and the selection method comprises the following steps: when the counter output is less than N1 × N2 (the upper half of the codebook), the comparator output is 0, the data selector selects data 0, the primary beam rotation factor q is selected to be 0, and the secondary beam rotation factor q is selected to be second PMI i₂The minimum is 2 bits; when the counter output is equal to or greater than N1 × N2 (lower part of codebook), the comparator output is 1, the data selector selects data 1, and the main beam rotation factor q is selected as second PMI i₂The highest 2bits (bit), the secondary beam rotation factor q is chosen to be second PMI i₂The lowest 2bits of the lowest 2bits and the middle 2bits of the summed result. Then, the respective enable signals of the main and auxiliary beams are generated through the combinational logic according to the main and auxiliary beam rotation factors, and the generated corresponding relationship is shown in table 5:

rotateFactor (2bit)	Real part negation enable	Imaginary part negation enable	Exchange enable between real and virtual
				00	0	0	0
01	0	1	1
				10	1	1	0
11	1	0	1

TABLE 5

An eleventh module 602 is configured to: performing exchange and inversion operation on the main beam data according to the enable generated by the twiddle factor to obtain the data of the main beam and the auxiliary beam, adding the obtained data of the main beam and the auxiliary beam again, and storing the added data as a codebook; the method can comprise the following steps: separately storing the real part and the imaginary part of main beam data, and if the real part/the imaginary part is inverted to be 1, respectively carrying out inversion operation on the real part/the imaginary part; if the real part/imaginary part is inverted to be 0, the original value is directly output without processing the real part/imaginary part. Next, if the fruit virtual swap enable is 1, the data selector selects data 1 output (completes the real part virtual swap); if the fruit virtual swap enable is 0, then the data selector selects data 0 output (real imaginary part not swapped). And adding the output results of the main beam real part data selector after enabling operation according to the twiddle factors, storing the added results into a real part of a result register, adding the output results of the imaginary part data selector, and storing the added results into an imaginary part of the result register. And using the stored real part and imaginary part of the register as a codebook to finish the generation of the codebook.

Application example two

Forming an array {2, 3, 6, 8, 10, 12, 14, 16} of all values of N1 × N2 according to all values of N1 and N2 to obtain the minimum common multiple 1680 of each element in the array, and multiplying the minimum common multiple 1680 by the oversampling multiple 4 to obtain 6720 of the number of corresponding DFT-based basic elements; and then, a quadrant compression storage method is adopted, and only the value of the first quadrant in all DFT bases is stored, so that 1680 DFT bases are required to be stored in total, and meanwhile, the power factor is avoidedMultiplication operation of time, storing 1680 DFT base multiplicationAs a result, the address storing each DFT-based basic element can be given by:

storing DFT basic elements according to the sequence; wherein, the real part and the imaginary part of each DFT base respectively occupy 1 Byte (Byte), and one storage address is used, and the address is 0-3359 in this example.

Step two: according to the input first PMI1i₁₁、first PMI2 i₁₂、first PMI3 i₁₃Sequentially generating an addressing address, a real part/imaginary part exchange enabling signal, a real part/imaginary part negation enabling signal and a main/auxiliary enabling signal of each DFT basic element of the main beam and the auxiliary beam; and after taking out the DFT base elements according to the generated addressing address, respectively carrying out exchange and negation operations according to the first enabling information to obtain the final output main and auxiliary carrier DFT base. Since N1 is 4 and N2 is 4, each DFT basis of the main and auxiliary beams contains N1 × N2 is 16 complex elements, and these 32 elements are generated sequentially (16 main beams and 16 auxiliary beams); specifically, the method comprises the following steps:

the embodiment of the invention realizes the following contents through an accumulator, and firstly, an output step value S is obtained according to the values of N1 and N2_N1、S_N2(ii) a In this example S_N1＝420，S_N2420; according to the input first PMI1i₁₁、first PMI 2 i₁₂Obtaining the accumulated step length S of the main and auxiliary beams_{N1_add}＝i₁₁*S_N1＝4200，S_{N2_add}＝i₁₂*S_N2840 according to first PMI3i₁₃Deriving d of the auxiliary beam₁＝2，d₂0; and obtaining the offset step length Off of the auxiliary wave beam_N1＝2*4*420＝3360，Off_N20 x 4 x 420 x 0, the addressing address sequence corresponding to 16 elements of the main beam is generated:

{0,S_{N2_add},2S_{N2_add},...(N2-1)S_{N2_add},0+S_{N1_add},S_{N2_add}+S_{N1_add},...

(N2-1)S_{N2_add}+S_{N1_add},0+(N1-1)S_{N1_add},S_{N2_add}+(N1-1)S_{N1_add},

2*S_{N2_add}+(N1-1)S_{N1_add},...(N2-1)S_{N2_add}+(N1-1)S_{N1_add}}；

and the addressing address sequence of the auxiliary beam:

{0,S_{N2_add}+Off_N2,2(S_{N2_add}+Off_N2),...(N2-1)(S_{N2_add}+Off_N2),0+S_{N1_add}+Off_N1,

2*(S_{N2_add}+Off_N2)+S_{N1_add}+Off_N1,...(N2-1)(S_{N2_add}+Off_N2)+S_{N1_add}+Off_N1,

0+(N1-1)(S_{N1_add}+Off_N1),S_{N2_add}+Off_N2+(N1-1)(S_{N1_add}+Off_N1),

2*(S_{N2_add}+Off_N2)+(N1-1)(S_{N1_add}+Off_N1),...

(N2-1)(S_{N2_add}+Off_N2)+(N1-1)(S_{N1_add}+Off_N1)}；

after the addressing address sequence is generated, each address in the main beam address sequence and the auxiliary beam address sequence is left according to the total number 6720 of DFT basic elements to obtain the addressing address of the DFT basic elements; wherein, the primary beam is {0, 840, 1680, 2520, 4200, 5040, 5880, 0, 1680, 2520, 3360, 4200, 5880, 0, 840, 1680}, and the secondary beam is {0, 840, 1680, 2520, 840, 1680, 2520, 3360, 1680, 2520, 3360, 4200, 2520, 3360, 4200, 5040 }; finally, the first quadrant address and the enabling signal of the main beam and the auxiliary beam are generated according to the address sequence, the first quadrant address of the address in the range of [0,1679] is the original address, the real part is negated and enabled to be 0, the imaginary part is negated and enabled to be 0, the real part is swapped and enabled to be 0, the first quadrant address of the address in the range of [1680, 3359] is the original address minus 1680, the real part is negated and enabled to be 0, the imaginary part is negated and enabled to be 1, the real part is swapped and enabled to be 1, the first quadrant address of the address in the range of [3360, 5039] is the original address minus 3360, the real part is negated and enabled to be 1, the imaginary part is negated and enabled to be 1, the real part is swapped and enabled to be 0, the first quadrant address of the address in the range of [5040, 6719] is the original address minus 5040, the real part is negated and enabled to be 0, the imaginary part is enabled to be 1, the imaginary part is swapped and enabled to be 1, the final first quadrant address and enable for this example is shown in tables 6 and 7:

TABLE 6

TABLE 7

According to the embodiment of the invention, the address is corrected through the power factor, the address is corrected only for the auxiliary beam, meanwhile, the address is 1680 only when P is 2, and the other values of P are 0, because P is 1, the power factor correction address in the embodiment is 0, therefore, DFT base element data are directly and sequentially taken out according to the first quadrant address, and then real part/imaginary part inversion and exchange processing are carried out according to the enabling signal, and finally, a DFT base sequence corresponding to the main beam and the auxiliary beam is obtained; wherein, the main beam is:

because the power factor P is 1, at this time, the auxiliary beam needs to be right-shifted by one bit, and the power adjustment value is multiplied by the auxiliary beam DFT base sequence to obtain a power-adjusted auxiliary beam DFT base sequence:

according to 1/2 layers of respective second PMI i_2，1，i_2，2And taking values to obtain 1/2 layers of respective three twiddle factors. Wherein i_2，1，i_2，2Is in the value range of [0, 63 ]]Expressed by 6bits unsigned number, three twiddle factors q of layer 1_1，1,q_2，1,q_3，1Respectively get i_2，1The highest 2bits, the middle 2bits and the lowest 2bits, and three twiddle factors q of 2 layers_1，2，q_2，2,q_3，2Respectively get i_2，2The highest 2bits, the middle 2bits and the lowest 2 bits. In this example q_1，1＝0,q_2，1＝1,q_3，1＝3，q_1，2＝2,q_2，2＝1,q_3，2＝1。

And respectively carrying out phase rotation on the main and auxiliary beam DFT base sequences according to the obtained main and auxiliary beam DFT base sequences and 1/2 layers of rotation factors to obtain 1/2 layers of respective main and auxiliary beam rotated codebook sequences, wherein the length of each part of sequences in the upper and lower parts is the length of the DFT base sequence. The adjusting method comprises the following steps: for the twiddle factor of 0, the adjustment value is the original element; for the twiddle factor being 1, the adjustment value is to invert the imaginary part of the original element and then exchange the real part and the imaginary part; for the twiddle factor of 2, the adjustment value is to invert the real part and the imaginary part of the original element; for the twiddle factor of 3, the adjustment value is to invert the real part of the original element and then exchange the real part and the imaginary part.

Specifically, the upper half of the main beam 1-layer codebook is the main beam DFT base sequence, and does not need to be adjusted, and the upper half of the main beam 1-layer codebook is:

the upper half part of the auxiliary beam 1 layer codebook is according to q_3，1Phase rotation is performed as 3, and the upper half of the auxiliary beam 1-layer codebook is:

the lower half of the main beam 1 layer codebook is according to q_1，1Phase rotation is carried out when the total phase is 0, and the lower half part of a 1-layer codebook of the main beam is as follows:

the lower half of the auxiliary beam layer 1 codebook is according toq_2，1+q_1，1Rotate for 1, assist beam 1 layer codebook lower half:

the upper half part of the main beam 2-layer codebook is the main beam DFT base sequence, and does not need to be adjusted, and the upper half part of the main beam 2-layer codebook is:

the upper part of the auxiliary beam 2 layer codebook is according to q_3，2Phase rotation is performed for 1, and the auxiliary beam 2 layer codebook is in the upper half:

the lower half of the main beam 2-layer codebook is according to q_1，2Phase rotation is carried out for 2, and the lower half part of the 2-layer codebook of the main beam is as follows:

the lower half part of the auxiliary beam 2-layer codebook is according to q_2，2+q_1，2Rotating for 3, the lower half sequence of the auxiliary beam 1-layer codebook is as follows:

the final codebook sequence for each layer of the primary and secondary beams 1/2 is derived, where each layer contains N1 x N2 x 2-32 elements.

And adding the elements in the main and auxiliary beam codebook sequences at the same position in sequence for the generated codebook sequence of each layer to obtain a final 2-layer codebook and storing the final 2-layer codebook.

Specifically, for a 1-layer codebook, sequentially adding 32 elements of the upper and lower parts of a main and auxiliary beam 1-layer codebook sequence to obtain a final 1-layer codebook sequence:

for the 2-layer codebook, sequentially adding 32 elements of the upper part and the lower part of the 2-layer codebook sequence of the main beam and the auxiliary beam to obtain a final 2-layer codebook sequence:

finally, 1/2 layers of codebook sequences are sequentially stored in a generated codebook memory.

From the above steps, it can be seen that, for this embodiment, the required precoding codebook matrix can be generated through simple address generation, memory reading, real part and imaginary part exchange/negation, shifting, and real number multiply-add for a limited number of times. Compared with the existing offline storage technology, the method only needs to store a small part of DFT base element values, the required storage space is only about 7kB, the existing offline storage needs at least 1GB storage space, the required storage of the method is about one ten-thousandth of that of the prior art, and meanwhile, excessive complexity is not increased in the aspect of addressing; compared with the existing online generation technology, the method completely avoids complex calculation such as exponential operation, complex multiplication and the like through operations such as partial offline storage and real part and imaginary part exchange/negation and the like, and greatly reduces the implementation complexity of online generation.

When searching for the optimal PMI of the primary and secondary beams (i.e., searching for first PMI and p), the codebook generation method of the present invention directly outputs the result in the primary beam memory in the module 203 without performing the steps of phase rotation and beam combination, as described in the first to second steps of the embodiment, in each codebook generation execution process. The method for outputting the beam DFT base in advance can further reduce the complexity of codebook generation and accelerate the codebook generation speed.

The codebook generating method only needs to perform one step, namely the first step, the second step, and the value of a main/auxiliary beam memory in the module 203 once in the codebook generating and executing process when determining the optimal values of the first PMI and the p to search the optimal second PMI, does not need to perform the step of generating the main/auxiliary beam base sequence when the codebook is required to be generated in each subsequent change of the second PMI, and can complete the generation of the codebook only by repeatedly executing the steps of the third step, the fourth step. The method for rapidly generating the second PMI codebook can further reduce the complexity of codebook generation and accelerate the codebook generation speed.

It will be understood by those skilled in the art that all or part of the steps of the above methods may be implemented by a program instructing associated hardware (e.g., a processor) to perform the steps, and the program may be stored in a computer readable storage medium, such as a read only memory, a magnetic or optical disk, and the like. Alternatively, all or part of the steps of the above embodiments may be implemented using one or more integrated circuits. Accordingly, each module/unit in the above embodiments may be implemented in hardware, for example, by an integrated circuit to implement its corresponding function, or in software, for example, by a processor executing a program/instruction stored in a memory to implement its corresponding function. The present invention is not limited to any specific form of combination of hardware and software.

Although the embodiments of the present invention have been described above, the above description is only for the convenience of understanding the present invention, and is not intended to limit the present invention. It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.

Claims

1. A method for generating a codebook, comprising:

2. The method of claim 1, wherein the predetermined number of DFT-based basic elements comprises:

3. The method of claim 2, wherein the preset number of DFT based elements are stored at the following addresses:

4. the method according to any one of claims 1 to 3, wherein the codebook associated information comprises part or all of the following information:

5. The method according to any one of claims 1 to 3, wherein outputting the address according to the preset address enable signal comprises:

6. The method of any of claims 1 to 3, wherein decomposing the twiddle factor comprises:

7. An apparatus for implementing codebook generation, comprising: a first unit, a second unit, a third unit, a fourth unit, a fifth unit and a sixth unit; wherein,

8. The apparatus of claim 7, wherein the preset number of DFT based elements comprises:

9. The apparatus of claim 8, wherein the preset number of DFT based elements are stored at the following addresses:

10. the apparatus according to any one of claims 7 to 9, wherein the codebook associated information comprises some or all of the following information:

11. The device according to any one of claims 7 to 9, wherein the third unit is specifically configured to:

12. The apparatus according to any one of claims 7 to 9, wherein the fifth unit for decomposing the twiddle factor comprises:

13. A computer storage medium having computer-executable instructions stored therein for performing the method of any one of claims 1-5.

14. A terminal, comprising: a memory and a processor; wherein,

the processor is configured to execute program instructions in the memory;

storing preset DFT basic elements generated offline;