CN109799659B - Array substrate and liquid crystal display panel - Google Patents
Array substrate and liquid crystal display panel Download PDFInfo
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- CN109799659B CN109799659B CN201910191223.3A CN201910191223A CN109799659B CN 109799659 B CN109799659 B CN 109799659B CN 201910191223 A CN201910191223 A CN 201910191223A CN 109799659 B CN109799659 B CN 109799659B
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Abstract
The invention discloses an array substrate, wherein a first pixel electrode and a second pixel electrode which are insulated from each other and located in the same layer are arranged in each pixel unit on the array substrate, the first pixel electrode comprises a first main electrode and a plurality of first branch electrodes, the second pixel electrode comprises a second main electrode and a plurality of second branch electrodes, the first main electrode and the second main electrode are parallel and are arranged alternately, the plurality of first branch electrodes and the plurality of second branch electrodes are arranged between the first main electrode and the second main electrode, the plurality of first branch electrodes and the plurality of second branch electrodes are arranged alternately and are insulated from each other, a first thin film transistor connected with the first pixel electrode and a second thin film transistor connected with the second pixel electrode are also arranged in each pixel unit, and the first thin film transistor and the second thin film transistor are connected to two different data lines. The invention also discloses a liquid crystal display panel which comprises the array substrate.
Description
Technical Field
The invention relates to the technical field of liquid crystal display, in particular to an array substrate and a liquid crystal display panel.
Background
Liquid Crystal Display (LCD) devices have many advantages such as thin body, power saving, and no radiation, and are widely used. Such as: liquid crystal televisions, mobile phones, Personal Digital Assistants (PDAs), digital cameras, computer screens, notebook computer screens, or the like, are dominant in the field of flat panel displays.
The lcd device generally includes a housing, an lcd panel disposed in the housing, and a backlight module disposed in the housing.
A conventional Liquid Crystal display panel includes a Color Filter (CF) Substrate, a Thin Film Transistor Array (TFT) Substrate, and a Liquid Crystal Layer (Liquid Crystal Layer) filled between the two substrates. The conventional liquid crystal display device implements color display by using color filters coated with color resistors of red, green, blue, etc. to filter monochromatic light (usually white light) provided by the backlight module. Usually, three sub-pixels of red, green and blue are arranged to form a pixel, and the color filter can only allow 1/3 light to pass through due to the filtering property of the color photoresist, so that the light transmittance of the liquid crystal display panel is greatly lost.
Another method for realizing Color display is to remove the Color filter in the lcd panel and use the backlight module of Field Sequential Color (FSC) mode. The field sequential mode backlight module generally comprises three groups of LED backlight sources of red, green and blue, wherein light emitted by the backlight sources is sequentially switched into three colors of red, green and blue according to a time sequence; meanwhile, the corresponding pixels realize the change of light transmittance through liquid crystal, and the colors are mixed according to time by using the retention effect of human retina, thereby realizing color display. The field sequential display can realize high-transmittance display without using a color filter, and meanwhile, colors are directly synthesized by a backlight source, so that the color purity is higher, but the frequency of a field sequential display mode is at least 3 times faster than that of a traditional liquid crystal display mode, so that the requirement on the response speed of liquid crystal molecules is very high.
The conventional liquid crystal display device can improve the response speed of liquid crystal molecules. The pixel electrodes on the thin film transistor array substrate are made into the sawtooth shape, when voltage is applied, the sawtooth-shaped pixel electrodes can improve the edge field effect, when no voltage is applied, liquid crystal molecules among the sawteeth respectively and quickly recover to the initial state towards the closer electrode strips, although the response speed of the liquid crystal molecules can be improved, the driving voltage is larger, correspondingly, the power consumption is larger, even if the larger driving voltage is used, the penetration rate cannot reach the sum state, and therefore the penetration rate is relatively lower.
Disclosure of Invention
In order to overcome the defects and shortcomings in the prior art, the present invention provides an array substrate and a liquid crystal display panel to solve the problems of large driving voltage, large power consumption and low transmittance of a pixel electrode in the prior art.
The purpose of the invention is realized by the following technical scheme:
the invention provides an array substrate, which comprises a plurality of scanning lines and a plurality of data lines arranged on the array substrate, wherein the array substrate is defined by a plurality of pixel units formed by mutually insulating and crossing the scanning lines and the data lines, a common electrode is also arranged on the array substrate, a first pixel electrode and a second pixel electrode are arranged in each pixel unit, the first pixel electrode and the second pixel electrode are mutually insulated and positioned in the same layer, the first pixel electrode comprises a first main electrode and a plurality of first branch electrodes, the second pixel electrode comprises a second main electrode and a plurality of second branch electrodes, the first main electrode and the second main electrode are parallel and mutually and alternately arranged, the first branch electrodes and the second branch electrodes are all arranged between the first main electrode and the second main electrode, and the first branch electrodes are all in conductive connection with the first main electrode, the plurality of second branch electrodes are all in conductive connection with the second main electrode, the plurality of first branch electrodes and the plurality of second branch electrodes are arranged alternately, a first thin film transistor connected with the first pixel electrode and a second thin film transistor connected with the second pixel electrode are further arranged in each pixel unit, and the first thin film transistor and the second thin film transistor are connected to two different data lines.
Furthermore, the plurality of first branch electrodes are perpendicular to the first main electrode, and the plurality of second branch electrodes are perpendicular to the second main electrode.
Furthermore, the first main electrode and the second main electrode extend along the data line direction, and the plurality of first branch electrodes and the plurality of second branch electrodes extend along the scan line direction.
Furthermore, the control end of the first thin film transistor and the control end of the second thin film transistor are both connected with the same scanning line, the first pixel electrode is connected with one of the two data lines adjacent to the left and right of the pixel unit through the first thin film transistor, and the second pixel electrode is connected with the other of the two data lines adjacent to the left and right of the pixel unit through the second thin film transistor.
Furthermore, two parallel data lines are arranged between two adjacent columns of the pixel units, and each pixel unit in the same row is connected to the same scanning line.
Furthermore, two scan lines are disposed between two adjacent rows of the pixel units, and each pixel unit in the same row is alternately connected to the two scan lines on the upper and lower sides of the pixel unit in the row.
Furthermore, the number of the second main electrodes is two, one first main electrode is arranged between the two second main electrodes, the left side and the right side of the first main electrode are respectively provided with a plurality of first branch electrodes, and one side of each second main electrode facing the first main electrode is provided with a plurality of second branch electrodes.
Furthermore, the number of the first trunk electrodes and the number of the second trunk electrodes are two, one second trunk electrode is arranged between two first trunk electrodes, one first trunk electrode is arranged between two second trunk electrodes, the left side and the right side of the second trunk electrode, which are positioned between two first trunk electrodes, are connected with a plurality of second branch electrodes, the left side and the right side of the first trunk electrode, which are positioned between two second trunk electrodes, are connected with a plurality of first branch electrodes, the first trunk electrode, which is positioned on the outermost side, is connected with a plurality of first branch electrodes on one side facing the second trunk electrode, and the second trunk electrode, which is positioned on the outermost side, is connected with a plurality of second branch electrodes on one side facing the first trunk electrode.
Furthermore, the widths of the first branch electrodes at the end far away from the first main electrode are gradually reduced, and the widths of the second branch electrodes at the end far away from the second main electrode are gradually reduced.
The invention also provides a liquid crystal display panel which comprises the array substrate, the opposite substrate and the liquid crystal layer between the array substrate and the opposite substrate.
The invention has the beneficial effects that: the first pixel electrode is set as a first main electrode and a plurality of first branch electrodes, the second pixel electrode is set as a second main electrode and a plurality of second branch electrodes, the plurality of first branch electrodes and the plurality of second branch electrodes are mutually arranged alternately and insulated and separated, the fringe field effect can be improved by the plurality of first branch electrodes and the plurality of second branch electrodes, when no voltage is applied, liquid crystal molecules between the plurality of first branch electrodes and the plurality of second branch electrodes respectively quickly recover to an initial state towards a closer branch electrode, the response speed of the liquid crystal molecules can be accelerated, the first thin film transistor and the second thin film transistor enable the first pixel electrode and the second pixel electrode to be connected with two different data lines, voltages with opposite polarities are applied to the first pixel electrode and the second pixel electrode, the fringe field effect is further improved, and therefore the driving voltage can be reduced and the power consumption can be reduced, the penetration rate can also be increased.
Drawings
FIG. 1 is a schematic cross-sectional view of a liquid crystal display panel in a black state according to the present invention;
FIG. 2 is a schematic cross-sectional view of a liquid crystal display panel in a white state according to the present invention;
fig. 3 is a schematic circuit diagram of an array substrate according to an embodiment of the invention;
FIG. 4 is a schematic plan view of a pixel unit according to an embodiment of the present invention;
fig. 5 is a schematic circuit diagram of an array substrate according to a second embodiment of the invention;
FIG. 6 is a schematic plane structure diagram of a pixel unit according to a third embodiment of the present invention;
FIG. 7 is a schematic plan view of a pixel unit according to a fourth embodiment of the present invention;
FIG. 8 is a schematic plane structure diagram of a pixel unit according to a fifth embodiment of the present invention;
FIG. 9 is a schematic plan view of a pixel unit according to a sixth embodiment of the present invention;
FIG. 10 is a graph comparing the transmittance with voltage for the present invention and the prior art.
Detailed Description
To further illustrate the technical means and effects of the present invention adopted to achieve the predetermined objects, the following detailed description of the embodiments, structures, features and effects of the array substrate and the liquid crystal display panel according to the present invention with reference to the accompanying drawings and the preferred embodiments is as follows:
[ example one ]
Fig. 1 is a schematic cross-sectional structure diagram of a liquid crystal display panel in a black state, fig. 2 is a schematic cross-sectional structure diagram of a liquid crystal display panel in a white state, fig. 3 is a schematic circuit structure diagram of an array substrate according to a first embodiment of the present invention, and fig. 4 is a schematic plan structure diagram of a pixel unit according to a first embodiment of the present invention. As shown in fig. 1 to 4, an array substrate according to an embodiment of the present invention includes a plurality of scan lines 11 and a plurality of data lines 12 disposed on an array substrate 10, and a plurality of pixel units P are defined on the array substrate 10 by the scan lines 11 and the data lines 12 crossing each other in an insulated manner. The array substrate 10 is further provided with a common electrode 14, each pixel unit P is provided with a first pixel electrode 16 and a second pixel electrode 17, the first pixel electrode 16 and the second pixel electrode 17 are insulated from each other and located in the same layer, and the first pixel electrode 16 and the second pixel electrode 17 are insulated from the common electrode 14 by an insulating layer 15. The first pixel electrode 16 includes a first main electrode 161 and a plurality of first branch electrodes 162, the second pixel electrode 17 includes a second main electrode 171 and a plurality of second branch electrodes 172, the plurality of first branch electrodes 162 are all electrically connected to the first main electrode 161, the plurality of second branch electrodes 172 are all electrically connected to the second main electrode 171, the first main electrode 161 and the second main electrode 171 are parallel and are alternately arranged, and the plurality of first branch electrodes 162 and the plurality of second branch electrodes 172 are all disposed between the first main electrode 161 and the second main electrode 171. The first pixel electrode 16 and the second pixel electrode 17 are formed by etching and patterning a conductive layer.
In this embodiment, the left and right sides of the first pixel electrode 16 are respectively provided with a plurality of first branch electrodes 162, the plurality of first branch electrodes 162 are respectively perpendicular to and conductively connected with the first main electrode 161, the second pixel electrode 17 is provided with a plurality of second branch electrodes 172 at a side facing the first main electrode 161, the plurality of second branch electrodes 172 are respectively perpendicular to and conductively connected with the second main electrode 171, the plurality of first branch electrodes 162 and the plurality of second branch electrodes 172 are alternately arranged, and the first pixel electrode 16 and the second pixel electrode 17 are engaged with each other as if two combs.
Further, there are at least two second trunk electrodes 171, and the plurality of first branch electrodes 162 located at the left and right sides of the first trunk electrode 161 between the two second trunk electrodes 171 are bilaterally symmetric along the first trunk electrode 161. In this embodiment, there are one first trunk electrode 161 and two second trunk electrodes 171, the first trunk electrode 161 is disposed between the two second trunk electrodes 171, and the plurality of first branch electrodes 162 on the left and right sides of the first trunk electrode 161 are bilaterally symmetric along the first trunk electrode 161.
In the present embodiment, a first thin film transistor 131 connected to the first pixel electrode 16 and a second thin film transistor 132 connected to the second pixel electrode 17 are further disposed in each pixel unit P, the first thin film transistor 131 and the second thin film transistor 132 are connected to two different data lines 12, and the two different data lines 12 are used for applying voltage signals with opposite polarities. In this embodiment, the two voltage signals with opposite polarities have the same amplitude, that is, the first pixel electrode 16 applies the driving voltage with the opposite polarity and the same amplitude as the second pixel electrode 17, so that a fringe electric field is formed between the first pixel electrode 16 and the common electrode 14 and between the second pixel electrode 17 and the common electrode 16, and a stronger fringe electric field is also formed between the first pixel electrode 16 and the second pixel electrode 17 (as shown in fig. 2), thereby increasing the intensity of the fringe electric field, reducing the driving voltage, and reducing the power consumption.
In this embodiment, the control terminal of the first thin film transistor 131 and the control terminal of the second thin film transistor 132 are both connected to the same scan line 11, so that the first pixel electrode 16 and the second pixel electrode 17 are simultaneously connected to the corresponding gray scale voltages. The source of the first thin film transistor 131 is connected to one of the two adjacent data lines 12 on the left and right of the pixel unit P, and the drain of the first thin film transistor 131 is electrically connected to the first pixel electrode 16; the source of the second thin film transistor 132 is connected to the other of the two data lines 12 adjacent to the pixel unit P on the left and right, and the drain of the second thin film transistor 132 is electrically connected to the second pixel electrode 17.
In the present embodiment, the first main electrode 161 and the second main electrode 171 both extend along the data line 12 direction, and the plurality of first branch electrodes 162 and the plurality of second branch electrodes 172 both extend along the scan line 11 direction. For example, the first main electrode 161 and the second main electrode 171 may also extend along the scanning line 11 direction, but the alignment direction of the liquid crystal molecules is changed.
In this embodiment, two data lines 12 are arranged between two pixel units P in two adjacent left and right columns, one of the two pixel units P is connected to one of the data lines 12, and the other of the two pixel units P is connected to the other data line 12. In this embodiment, the pixel units P in the same row are connected to the same scan line 11, and the pixel units P in two adjacent rows are connected to different scan lines 11.
The following table is a simulation table of the present invention and the prior art:
| V1 | V2 | rise time | Time of fall | RT | TR | Relative penetration rate | |
| Prior Art | 7V | / | 2.66ms | 1.72ms | 4.38ms | 4.88％ | 100％ |
| The invention | -4V | 4V | 2.70ms | 4.09ms | 6.79ms | 7.48％ | 153.23％ |
Fig. 10 is a graph comparing the Transmittance (TR) of the present invention with that of the prior art, wherein a dotted line 40 is a graph of the Transmittance (TR) of the present invention as a function of a driving voltage, and a solid line 50 is a graph of the Transmittance (TR) of the prior art as a function of the driving voltage. Referring to the table and fig. 10, the prior art applies a driving voltage of 7V, with a rise time of 2.66ms, a fall time of 1.72ms, a Response Time (RT) of 4.38ms, and a Transmittance (TR) of 4.88%; in the present invention, a driving voltage of-4V is applied to the first pixel electrode 16, a driving voltage of 4V is applied to the second pixel electrode 17, a first rise time is 2.70ms, a fall time is 4.09ms, a Response Time (RT) is 6.79ms, and a Transmittance (TR) is 7.48%. Compared with the prior art, the driving voltage is reduced by 3V, the penetration rate (TR) is increased by 2.60%, and the penetration rate (TR) of the prior art is 100%, and is improved by 53.23% compared with the penetration rate (TR) of the prior art. As shown in fig. 10, in the present invention, when the driving voltage is 4V, the Transmittance (TR) has already reached the saturation state, whereas the prior art has not yet reached the saturation state when the driving voltage is 7V, and when the Transmittance (TR) is reached, the driving voltage applied by the present invention is much smaller than that applied by the prior art, which shows that the present invention greatly reduces the driving voltage and reduces the power consumption.
[ example two ]
Fig. 5 is a schematic circuit structure diagram of an array substrate according to a second embodiment of the present invention, and as shown in fig. 5, the structure and the operation principle of the array substrate according to the second embodiment of the present invention are basically the same as those of the array substrate according to the first embodiment (fig. 3), except that in this embodiment, two scan lines 11 are disposed between two rows of pixel units P adjacent to each other, each pixel unit P in the same row is alternately connected to the two scan lines 11 disposed on the upper and lower sides of the pixel unit P in the row, and the pixel unit P is connected to the scan lines 11 through a first thin film transistor 131 and a second thin film transistor 132.
In the present embodiment, one data line 12 is disposed between two adjacent columns of pixel units P, and the same data line 12 is connected to two pixel units P adjacent to each other left and right.
It should be understood by those skilled in the art that the rest of the structure and the operation principle of the present embodiment are the same as those of the first embodiment, and are not described herein again.
[ third example ]
Fig. 6 is a schematic plan view of a pixel unit in a third embodiment of the present invention, and as shown in fig. 6, the structure and the operation principle of the array substrate provided in the third embodiment of the present invention are substantially the same as those of the array substrate in the first embodiment (fig. 4), except that in this embodiment, the plurality of first branch electrodes 162 located on the left and right sides of the first trunk electrode 161 between the two second trunk electrodes 171 are arranged along the first trunk electrode 161 in a vertically staggered manner. In this embodiment, there are one first trunk electrode 161, two second trunk electrodes 171, the first trunk electrode 161 is disposed between the two second trunk electrodes 171, the left and right sides of the first trunk electrode 161 are respectively connected with a plurality of first branch electrodes 162, the plurality of first branch electrodes 162 on the left and right sides of the first trunk electrode 161 are arranged in a vertically staggered manner along the first trunk electrode 161, and each second trunk electrode 171 is connected with a plurality of second branch electrodes 172 on a side facing the first trunk electrode 161.
It should be understood by those skilled in the art that the rest of the structure and the operation principle of the present embodiment are the same as those of the first embodiment, and are not described herein again.
[ example four ]
Fig. 7 is a schematic plan view of a pixel unit in a fourth embodiment of the present invention, and as shown in fig. 7, the array substrate provided in the fourth embodiment of the present invention has substantially the same structure and operation principle as the array substrate in the first embodiment (fig. 4), except that in the present embodiment, the widths of the first branch electrodes 162 at the end far from the first main electrode 161 are gradually reduced, and the widths of the second branch electrodes 172 at the end far from the second main electrode 171 are gradually reduced.
In the present embodiment, the width of the first branch electrodes 162 at the end far from the first trunk electrode 161 is gradually reduced, the width of the second branch electrodes 172 at the end far from the second trunk electrode 171 is gradually reduced, the first branch electrodes 162 at the end far from the first trunk electrode 161 are tapered, and the second branch electrodes 172 at the end far from the second trunk electrode 171 are tapered.
It should be understood by those skilled in the art that the rest of the structure and the operation principle of the present embodiment are the same as those of the first embodiment, and are not described herein again.
[ example five ]
Fig. 8 is a schematic plan view of a pixel unit in a fifth embodiment of the present invention, and as shown in fig. 8, the array substrate provided in the fifth embodiment of the present invention is basically the same as the array substrate in the first embodiment (fig. 4) in structure and operation principle, except that in this embodiment, there are at least two first trunk electrodes 161, at least two second trunk electrodes 171, one second trunk electrode 171 between the two first trunk electrodes 161, one first trunk electrode 161 between the two second trunk electrodes 171, a plurality of second branch electrodes 172 connected to left and right sides of the second trunk electrode 171 between the two first trunk electrodes 161, and the plurality of second branch electrodes 172 are bilaterally symmetric along the second trunk electrode 171. The left and right sides of the first main electrode 161 between the two second main electrodes 171 are respectively connected with a plurality of first branch electrodes 162, and the plurality of first branch electrodes 162 are bilaterally symmetrical along the first main electrode 161. The first trunk electrode 161 located at the outermost side is provided with a plurality of first branch electrodes 162 on the side facing the second trunk electrode 171, and the second trunk electrode 171 located at the outermost side is provided with a plurality of second branch electrodes 172 on the side facing the first trunk electrode 161.
In this embodiment, there are two first trunk electrodes 161, two second trunk electrodes 171, the first trunk electrodes 161 and the second trunk electrodes 171 are alternately arranged, the left and right sides of the first trunk electrode 161 between the two second trunk electrodes 171 are both provided with a plurality of first branch electrodes 162, and the plurality of first branch electrodes 162 on the left and right sides of the first trunk electrode 161 are bilaterally symmetric along the first trunk electrode 161; a plurality of second branch electrodes 172 are disposed on both left and right sides of the second main electrode 171 between the two first main electrodes 161, and the plurality of second branch electrodes 172 on both left and right sides of the second main electrode 171 are bilaterally symmetric along the second main electrode 171.
In the present embodiment, the first trunk electrode 161 adjacent to the edge of the pixel unit P is provided with a plurality of first branch electrodes 162 at one side facing the second trunk electrode 171, and the other side is free of the first branch electrodes 162; the second trunk electrode 171 adjacent to the edge of the pixel unit P is provided with a plurality of second branch electrodes 172 at one side toward the first trunk electrode 161, and the other side is free of the second branch electrodes 172.
In the present embodiment, the width of the first branch electrodes 162 at the end far from the first trunk electrode 161 is gradually reduced, the width of the second branch electrodes 172 at the end far from the second trunk electrode 171 is gradually reduced, the first branch electrodes 162 at the end far from the first trunk electrode 161 are tapered, and the second branch electrodes 172 at the end far from the second trunk electrode 171 are tapered.
It should be understood by those skilled in the art that the rest of the structure and the operation principle of the present embodiment are the same as those of the first embodiment, and are not described herein again.
[ sixth example ]
Fig. 9 is a schematic plan view illustrating a pixel unit in a sixth embodiment of the present invention, and as shown in fig. 9, the array substrate provided in the sixth embodiment of the present invention has substantially the same structure and operation principle as the array substrate in the fifth embodiment (fig. 8), except that in this embodiment, the plurality of first branch electrodes 162 located at the left and right sides of the first trunk electrode 161 between the two second trunk electrodes 171 are arranged along the first trunk electrode 161 in a vertically staggered manner; the plurality of second branch electrodes 172 located at the left and right sides of the second trunk electrode 171 between the two first trunk electrodes 161 are arranged along the second trunk electrode 171 in a vertically staggered manner.
Those skilled in the art should understand that the rest of the structure and the operation principle of the present embodiment are the same as those of the fifth embodiment, and are not described herein again.
Referring to fig. 1 and fig. 2, the present invention further provides a liquid crystal display panel, which includes the array substrate 10, the opposite substrate 20, and the liquid crystal layer 30 between the array substrate 10 and the opposite substrate 20.
The array substrate 10 and the opposite substrate 20 may be made of glass, acrylic, polycarbonate, or other materials, the common electrode 14, the first pixel electrode 16, and the second pixel electrode 17 may be made of Indium Tin Oxide (ITO), Indium Zinc Oxide (IZO), or other transparent conductive materials, and the liquid crystal layer 30 is made of positive liquid crystal molecules, that is, liquid crystal molecules having positive dielectric anisotropy, which has the advantage of fast response. As shown in fig. 1, in the initial state, the positive liquid crystal molecules in the liquid crystal layer 30 assume a lying posture substantially parallel to the first substrate, i.e., the long axis direction of the positive liquid crystal molecules is substantially parallel to the surface of the substrate, and the positive liquid crystal molecules are aligned in parallel to the extending direction of the first and second branch electrodes 162 and 172, i.e., the long axis direction of the positive liquid crystal molecules is parallel to the extending direction of the first and second branch electrodes 162 and 172. As shown in fig. 2, when a picture is displayed, a fringe field is formed between the first pixel electrode 16 and the common electrode 14 and between the second pixel electrode 17 and the first pixel electrode 16, and a fringe field is also formed between the second pixel electrode 17 and the first pixel electrode 16, and the positive liquid crystal molecules are deflected in a direction perpendicular to the extending direction of the first branch electrode 162 and the second branch electrode 172 under the action of the fringe field, so that the liquid crystal display panel is in a white state.
In this document, the terms upper, lower, left, right, front, rear and the like are used for defining the positions of the structures in the drawings and the positions of the structures relative to each other, and are only used for the clarity and convenience of the technical solution. It is to be understood that the use of the directional terms should not be taken to limit the scope of the claims.
Although the present invention has been described with reference to the preferred embodiments, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (6)
1. An array substrate, comprising a plurality of scanning lines (11) and a plurality of data lines (12) disposed on the array substrate (10), the array substrate (10) being defined by the plurality of scanning lines (11) and the plurality of data lines (12) being insulated from each other and crossing to form a plurality of pixel units (P), the array substrate (10) being further provided with a common electrode (14), characterized in that each pixel unit (P) is provided with a first pixel electrode (16) and a second pixel electrode (17), the first pixel electrode (16) and the second pixel electrode (17) being insulated from each other and being located at the same layer, the first pixel electrode (16) comprising a first main electrode (161) and a plurality of first branch electrodes (162), the second pixel electrode (17) comprising a second main electrode (171) and a plurality of second branch electrodes (172), the first main electrode (161) and the second electrode (171) being parallel to each other and arranged alternately, a plurality of the first branch electrodes (162) and a plurality of the second branch electrodes (172) are disposed between the first main electrode (161) and the second main electrode (171), a plurality of the first branch electrodes (162) are electrically connected to the first main electrode (161), a plurality of the second branch electrodes (172) are electrically connected to the second main electrode (171), a plurality of the first branch electrodes (162) and a plurality of the second branch electrodes (172) are alternately arranged, each pixel unit (P) is further provided therein with a first thin film transistor (131) connected to the first pixel electrode (16) and a second thin film transistor (132) connected to the second pixel electrode (17), the first thin film transistor (131) and the second thin film transistor (132) are connected to two different data lines (12), a control terminal of the first thin film transistor (131) and a control terminal of the second thin film transistor (132) are connected to the same scanning line (11) The first pixel electrode (16) is connected with one of the two data lines (12) adjacent to the left and right of the pixel unit (P) through the first thin film transistor (131), the second pixel electrode (17) is connected with the other of the two data lines (12) adjacent to the left and right of the pixel unit (P) through the second thin film transistor (132), two parallel scanning lines (11) are arranged between two adjacent rows of the pixel unit (P), the pixel units (P) in the same row are alternately connected to the two scanning lines (11) on the upper and lower sides of the row of the pixel unit (P), one data line (12) is arranged between two adjacent rows of the pixel unit (P), and the same data line (12) is connected with the two pixel units (P) adjacent to the left and right; the widths of the first branch electrodes (162) at the end far away from the first main electrode (161) are gradually reduced, and the widths of the second branch electrodes (172) at the end far away from the second main electrode (171) are gradually reduced.
2. The array substrate of claim 1, wherein a plurality of the first branch electrodes (162) are perpendicular to the first main electrode (161), and a plurality of the second branch electrodes (172) are perpendicular to the second main electrode (171).
3. The array substrate of claim 2, wherein the first main electrode (161) and the second main electrode (171) extend along the direction of the data line (12), and the first branch electrodes (162) and the second branch electrodes (172) extend along the direction of the scan line (11).
4. The array substrate of claim 1, wherein the number of the second trunk electrodes (171) is two, one first trunk electrode (161) is disposed between two second trunk electrodes (171), a plurality of first branch electrodes (162) are respectively disposed on both left and right sides of the first trunk electrode (161), and a plurality of second branch electrodes (172) are respectively disposed on one side of each second trunk electrode (171) facing the first trunk electrode (161).
5. The array substrate of claim 1, wherein the number of the first trunk electrodes (161) and the second trunk electrodes (171) is two, one second trunk electrode (171) is disposed between two first trunk electrodes (161), one first trunk electrode (161) is disposed between two second trunk electrodes (171), a plurality of second branch electrodes (172) are disposed between two first trunk electrodes (161), a plurality of first branch electrodes (162) are disposed between two second trunk electrodes (171) and on the left and right sides of the first trunk electrode (161), a plurality of first branch electrodes (162) are disposed between the two second trunk electrodes (171) and on the left and right sides of the first trunk electrode (161), and a plurality of first branch electrodes (162) are disposed on the outermost first trunk electrode (161) on the side facing the second trunk electrode (171), the second trunk electrode (171) located at the outermost side is provided with a plurality of second branch electrodes (172) in a connecting manner on the side facing the first trunk electrode (161).
6. A liquid crystal display panel comprising the array substrate (10) according to any one of claims 1 to 5, a counter substrate (20), and a liquid crystal layer (30) between the array substrate (10) and the counter substrate (20).
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| US20240353722A1 (en) * | 2021-10-19 | 2024-10-24 | Fuzhou Boe Optoelectronics Technology Co., Ltd. | Display panel and display device |
| CN114267776A (en) * | 2021-12-16 | 2022-04-01 | 惠州华星光电显示有限公司 | Display panel, manufacturing method and mobile terminal |
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