CN109726163B - SPI-based communication system, method, equipment and storage medium - Google Patents
SPI-based communication system, method, equipment and storage medium Download PDFInfo
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Abstract
The embodiment of the invention discloses a communication system, a method, equipment and a storage medium based on SPI, wherein the system comprises: the system comprises a host computer configured with a universal SPI interface module and at least one slave computer configured with a slave computer SPI interface module; the slave SPI interface module comprises a data area, a serial clock pin, a host input/slave output data pin, a host output/slave input data pin and a slave selection pin; the data area comprises an interrupt register, wherein a first interrupt bit of a host triggering a slave and a second interrupt bit of the slave triggering the host are arranged in the interrupt register; a preset pin of the host is connected to an interrupt register of the slave SPI interface module, so that the host can write the first interrupt bit and read the second interrupt bit; the slave is set to read the first interrupt bit and write the second interrupt bit. The embodiment of the invention effectively reduces the load of the CPU for processing the SPI interface data.
Description
Technical Field
Embodiments of the present invention relate to communications technologies, and in particular, to an SPI-based communication system, method, device, and storage medium.
Background
A Serial Peripheral Interface (SPI) is a synchronous SPI, which typically uses 4 wires: serial clock line SCK, master input/slave output data line MISO, master output/slave input data line MOSI, and low active slave select line NSS.
As shown in fig. 1, a common SPI interface writes data into a transmission buffer area when data needs to be transmitted, and starts to transmit the data; meanwhile, data is received into the receiving buffer, and the received data can be processed by a Central Processing Unit (CPU) in an interrupt or polling manner.
However, in the prior art, when data is transmitted, if the slave receiving buffer is full, the master continues to transmit, which results in loss of data stream. Data is sent in bytes without a check mechanism, and when a CPU receives data in bytes, the CPU processing capacity efficiency is low due to frequent interrupt calling.
Disclosure of Invention
The embodiment of the invention provides a communication system, a method, equipment and a storage medium based on an SPI (Serial peripheral interface), so as to reduce the load of a CPU (Central processing Unit) for processing SPI interface data.
In a first aspect, an embodiment of the present invention provides an SPI-based communication system, including:
the system comprises a host computer configured with a universal SPI interface module and at least one slave computer configured with a slave computer SPI interface module; the slave SPI interface module comprises a data area, a serial clock pin, a host input/slave output data pin, a host output/slave input data pin and a slave selection pin; the data area comprises an interrupt register, a master-to-slave buffer area and a slave-to-master buffer area, wherein a first interrupt bit of a master trigger slave and a second interrupt bit of the slave trigger master are arranged in the interrupt register; the universal SPI interface module is in signal connection with corresponding pins of the slave SPI interface module; a preset pin of the host is connected to an interrupt register of the slave SPI interface module, so that the host can write the first interrupt bit and read the second interrupt bit; the slave is configured to read the first interrupt bit and write the second interrupt bit.
In a second aspect, an embodiment of the present invention further provides an SPI-based communication method, including:
when the host sends data, generating a data frame according to the data to be sent and a preset data frame structure; the structure of the data frame is 1 byte frame length, 0-60 byte payload and 2 byte CRC check value;
reading an interrupt register of the slave SPI interface module;
if the first interrupt bit of the interrupt register is cleared, sending the data frame to the slave SPI interface module by taking two bytes as a unit; the former byte is a written data address, the latter byte is data of the data frame corresponding to the written data address, the 1 st bit of the written data address is a read-write operation identification bit and is identified as a write operation, and the 2 nd to 7 th bits correspond to the address of a master-to-backup cache area in the slave SPI interface module;
and executing write operation on an interrupt register of the slave SPI interface module after one data frame is sent, setting a first interrupt position of the interrupt register to trigger the slave to generate interrupt, and executing SPI data receiving operation by the slave.
In a third aspect, an embodiment of the present invention further provides an SPI-based communication method, including:
when the slave machine sends data, generating a data frame according to the data to be sent and a preset data frame structure; the structure of the data frame is 1 byte frame length, 0-60 byte payload and 2 byte CRC check value;
reading an interrupt register of the slave SPI interface module;
if the second interrupt bit of the interrupt register is cleared, sending the data frame to the slave SPI interface module by taking two bytes as a unit; the former byte is a written data address, the latter byte is data of the data frame corresponding to the written data address, the 1 st bit of the written data address is a read-write operation identification bit and is identified as a write operation, and the 2 nd to 7 th bits correspond to an address of a standby main cache area in the slave SPI interface module;
and executing write operation on an interrupt register of the slave SPI interface module after one data frame is sent, setting a second interrupt position of the interrupt register to trigger the host to generate interrupt, and executing SPI data receiving operation by the host.
In a fourth aspect, an embodiment of the present invention further provides an apparatus, where the apparatus includes:
one or more processors;
a memory for storing one or more programs;
a general SPI interface module;
when executed by the one or more processors, cause the one or more processors to implement an SPI-based communication method as provided by any embodiment of the invention.
In a fifth aspect, an embodiment of the present invention further provides an apparatus, where the apparatus includes:
one or more processors;
a memory for storing one or more programs;
a slave SPI interface module;
when executed by the one or more processors, cause the one or more processors to implement an SPI-based communication method as provided by any embodiment of the invention.
In a sixth aspect, embodiments of the present invention further provide a storage medium containing computer-executable instructions, which when executed by a computer processor, are configured to perform an SPI-based communication method as provided by any of the embodiments of the present invention.
In a seventh aspect, embodiments of the present invention further provide a storage medium containing computer-executable instructions, which when executed by a computer processor, are used to execute the SPI-based communication method provided in any of the embodiments of the present invention.
According to the embodiment of the invention, a frame-based communication mechanism is provided for the SPI interface by optimizing the SPI interface module of the slave and providing the data exchange module, a data flow control and data response mechanism is provided for the SPI interface by the interrupt register, and the load of the CPU for processing the SPI interface data is effectively reduced by the mechanisms.
Drawings
Fig. 1 is a schematic structural diagram of a general SPI interface module in the prior art;
FIG. 2 is a schematic structural diagram of an SPI-based communication system in an embodiment of the present invention;
fig. 3 is a schematic structural diagram of a slave SPI interface module 201 in the embodiment of the present invention;
FIG. 4 is a diagram of the contents structure of address bytes in an embodiment of the present invention;
FIG. 5 is a flow chart of a method of SPI-based communication in an embodiment of the present invention;
FIG. 6 is a block diagram of a data frame in an embodiment of the invention;
FIG. 7 is a flow chart of another SPI-based communication method in an embodiment of the present invention;
FIG. 8 is a schematic diagram of the structure of an apparatus in an embodiment of the invention;
fig. 9 is a schematic structural diagram of another apparatus in the embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures.
Examples
Fig. 2 is a schematic structural diagram of an SPI-based communication system according to an embodiment of the present invention, which is applicable to a case where a master and a slave communicate based on an SPI interface, and the system includes:
a master 10 configured with a generic SPI interface module 101 and at least one slave 20 configured with a slave SPI interface module 201. In fig. 2, one master and one slave are connected as an example.
As shown in fig. 3, the slave SPI interface module 201 includes a data area, a serial clock pin CLK, a master input/slave output data pin MISO, a master output/slave input data pin MOSI, and a slave select pin NSS. These four pins are connected in one-to-one correspondence with the pins of the general SPI interface module 101 of the host 10. The slave select pin NSS is active low, that is, the slave select pin of the general SPI interface module 101 of the host 10 outputs low level, and the slave is selected.
The data area comprises an interrupt register, a master-to-slave buffer area and a slave-to-master buffer area, wherein a first interrupt bit of a master trigger slave and a second interrupt bit of the slave trigger master are arranged in the interrupt register; in fig. 3, the first interrupt bit is denoted by SI and the second interrupt bit is denoted by MI, but the first interrupt bit and the second interrupt bit are not limited to the bit configured in fig. 3. The universal SPI interface module is in signal connection with corresponding pins of the slave SPI interface module; a preset pin of the host is connected to an interrupt register of the slave SPI interface module, so that the host can write the first interrupt bit and read the second interrupt bit; the slave is configured to read the first interrupt bit and write the second interrupt bit.
Both the host 10 and the slave 20 can perform read/write operations on the interrupt register of the slave SPI interface module 201. For the master 10, when the master 10 sends data, the interrupt register of the slave SPI interface module 201 is read, and when the first interrupt bit of the interrupt register is cleared, the data is sent to the slave SPI interface module 201, so that the slave 20 copies the data from the master-to-slave buffer area of the slave SPI interface module 201. When the host 10 receives data, the interrupt register of the slave SPI interface module 201 is read, and if the second interrupt bit of the interrupt register is set, the data of the backup main buffer area of the slave SPI interface module 201 is read. For the slave 20, when the slave 20 sends data, the interrupt register of the slave SPI interface module 201 is read, and when the second interrupt bit of the interrupt register is cleared, the data is sent to the slave SPI interface module 201, so that the master 10 copies the data from the slave to the master buffer of the slave SPI interface module 201. When the slave 20 receives data, the interrupt register of the slave SPI interface module 201 is read, and if the first interrupt bit of the interrupt register is set, the master-to-backup buffer area data of the slave SPI interface module 201 is read.
Specifically, the slave SPI module 201 is an IP core including an SPI interface function, as shown in fig. 3. The MOSI pin receives master-to-slave information, while the MISO pin sends slave-to-master information. The slave SPI interface module 201 takes two bytes as a processing cycle, the first byte is an address, and the content of the byte is as shown in fig. 4. The first bit is a WRB bit to indicate whether the processing cycle is a write operation or a read operation. The last seven bits are the address of the data area, ranging from 0 to 127.
Taking the master-to-slave SPI interface module 201 as an example, if the WRB is 1, which indicates a master write operation, the slave SPI interface module 201 will copy the second byte data received from the MOSI pin to the master-to-slave buffer according to the address of the first byte. If the WRB is 0, indicating a host read operation, the slave SPI interface module 201 copies a byte of data from the slave to the master buffer at the address of the first byte and sends the byte of data to the host through the MISO pin. It can be understood that the process of the slave performing read-write operation on the slave SPI interface module is similar, but the paths for receiving and transmitting data between the slave and the slave SPI interface module are different.
For an interrupt register with address 0, the host is allowed to complete a read or write operation to the interrupt register. For a read operation, if the MOSI pin receives an address with the first byte being 0, the slave SPI interface module 201 will send the contents of the interrupt register to the host through the MISO pin in the second byte. For a write operation, if the address with the first byte of 0x80 is received from the MOSI pin, the slave SPI interface module 201 writes the second byte received from the MOSI pin to the interrupt register. It can be understood that the process of reading and writing operations of the slave to the slave SPI interface module is similar, but the paths of receiving and sending the data of the register between the slave and the slave SPI interface module are different.
The embodiment also provides a communication method based on the SPI. As shown in fig. 5, when the master sends data and the slave receives data, the method includes:
And step 520, reading an interrupt register of the slave SPI interface module.
The former byte is a write data address, the latter byte is data of the data frame corresponding to the write data address, the 1 st bit of the write data address is a read-write operation identification bit and is identified as write operation, namely, the 1 st bit is 1, and the 2 nd to 7 th bits correspond to the address from the master buffer area to the standby buffer area in the slave SPI interface module, namely, the data is to be written into a target register of the master buffer area to the standby buffer area.
And 540, after the transmission of one data frame is completed, executing write operation on an interrupt register of the slave SPI interface module, and setting a first interrupt position of the interrupt register. After the setting, the slave can be triggered to generate an interrupt, and then the slave executes the SPI data receiving operation.
The first interrupt bit is cleared to inform the host computer that the slave computer has completed receiving data, so that when the host computer sends data next time, the first interrupt bit read to the interrupt register is cleared, and data can be sent.
As shown in fig. 7, when the slave sends data and the master receives data, the method includes:
and 710, when the slave machine sends data, generating a data frame according to a preset data frame structure according to the data to be sent. The structure of the data frame is 1 byte frame length, 0-60 byte payload and 2 byte CRC check value.
And 720, reading an interrupt register of the slave SPI interface module.
The former byte is a write data address, the latter byte is data of the data frame corresponding to the write data address, the 1 st bit of the write data address is a read-write operation identification bit and is identified as write operation, and the 2 nd to 7 th bits correspond to the address of the backup main cache area in the slave SPI interface module.
And 740, executing write operation on the interrupt register of the slave SPI interface module and setting the second interrupt position of the interrupt register after one data frame is sent. So as to trigger the host to generate an interrupt, and the host executes the SPI data receiving operation.
And step 750, reading an interrupt register of the slave SPI interface module when the host receives data.
And the 1 st bit of the preset data address is a read-write operation identification bit and is identified as read operation, and the 2 nd to 7 th bits are the address of a master buffer area first register in the slave SPI interface module.
And 7110, writing the interrupt register of the slave SPI interface module, and clearing a second interrupt bit of the interrupt register.
As shown in fig. 3, the master may trigger an interrupt to the slave by setting the bit corresponding to the SI. The slave can set a bit corresponding to the MI and output the GPIO pin, and if the host is connected with the GPIO pin to be used as a hard interrupt interface, the bit can be used as an interrupt bit for triggering the host by the slave.
According to the technical scheme of the embodiment, a frame-based communication mechanism is provided for the SPI interface by optimizing the SPI interface module of the slave and providing the data exchange module, a data flow control and data response mechanism is provided for the SPI interface by the interrupt register, and the load of the CPU for processing SPI interface data is effectively reduced by the mechanisms.
Fig. 8 is a schematic structural diagram of a device according to an embodiment of the present invention, as shown in fig. 8, the device includes a processor 810, a memory 820, and a general SPI interface module 830; the number of the processors 810 in the device may be one or more, and one processor 810 is taken as an example in fig. 8; the processor 810, the memory 820 and the SPI interface module 830 in the device may be connected by a bus or other means, as exemplified by the bus connection in fig. 8.
The memory 820 is a computer-readable storage medium that can be used to store software programs, computer-executable programs, and modules, such as program instructions/modules corresponding to the SPI-based communication method in the embodiments of the present invention. The processor 810 performs various functional applications of the device and data processing, i.e., implements the above-described SPI-based communication method applied to the host, by executing software programs, instructions, and modules stored in the memory 820.
The memory 820 may mainly include a program storage area and a data storage area, wherein the program storage area may store an operating system, an application program required for at least one function; the storage data area may store data created according to the use of the terminal, and the like. Further, the memory 820 may include high speed random access memory, and may also include non-volatile memory, such as at least one magnetic disk storage device, flash memory device, or other non-volatile solid state storage device. In some examples, the memory 820 may further include memory located remotely from the processor 810, which may be connected to devices through a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof. The universal SPI interface module 830 is used for the host to perform SPI communication with the slave.
Embodiments of the present invention also provide a storage medium containing computer-executable instructions, which when executed by a computer processor, are configured to perform a method for SPI-based communication, comprising:
when the host sends data, generating a data frame according to the data to be sent and a preset data frame structure; the structure of the data frame is 1 byte frame length, 0-60 byte payload and 2 byte CRC check value;
reading an interrupt register of the slave SPI interface module;
if the first interrupt bit of the interrupt register is cleared, sending the data frame to the slave SPI interface module by taking two bytes as a unit; the former byte is a written data address, the latter byte is data of the data frame corresponding to the written data address, the 1 st bit of the written data address is a read-write operation identification bit and is identified as a write operation, and the 2 nd to 7 th bits correspond to the address of a master-to-backup cache area in the slave SPI interface module;
and executing write operation on an interrupt register of the slave SPI interface module after one data frame is sent, setting a first interrupt position of the interrupt register to trigger the slave to generate interrupt, and executing SPI data receiving operation by the slave.
Of course, the storage medium containing the computer-executable instructions provided by the embodiments of the present invention is not limited to the method operations described above, and may also perform related operations in the SPI-based communication method applied to the host provided by any embodiments of the present invention.
From the above description of the embodiments, it is obvious for those skilled in the art that the present invention can be implemented by software and necessary general hardware, and certainly, can also be implemented by hardware, but the former is a better embodiment in many cases. Based on such understanding, the technical solutions of the present invention may be embodied in the form of a software product, which can be stored in a computer-readable storage medium, such as a floppy disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a FLASH Memory (FLASH), a hard disk or an optical disk of a computer, and includes several instructions for enabling a computer device (which may be a personal computer, a server, or a network device) to execute the method according to the embodiments of the present invention.
Fig. 9 is a schematic structural diagram of an apparatus according to an embodiment of the present invention, as shown in fig. 9, the apparatus includes a processor 910, a memory 920, and a slave SPI interface module 930; the number of the processors 910 in the device may be one or more, and one processor 910 is taken as an example in fig. 9; the processor 910, the memory 920 and the slave SPI interface module 930 in the device may be connected by a bus or other means, and fig. 9 illustrates the connection by the bus as an example.
The memory 920 is used as a computer-readable storage medium for storing software programs, computer-executable programs, and modules, such as program instructions/modules corresponding to the SPI-based communication method in the embodiment of the present invention. The processor 910 executes various functional applications of the device and data processing, i.e., implements the SPI-based communication method applied to the slave, by running software programs, instructions, and modules stored in the memory 920.
The memory 920 may mainly include a program storage area and a data storage area, wherein the program storage area may store an operating system, an application program required for at least one function; the storage data area may store data created according to the use of the terminal, and the like. Further, the memory 920 may include high speed random access memory, and may also include non-volatile memory, such as at least one magnetic disk storage device, flash memory device, or other non-volatile solid state storage device. In some examples, the memory 920 may further include memory located remotely from the processor 910, which may be connected to devices over a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof. The slave SPI interface module 930 is used for the master to perform SPI communication with the slave.
Embodiments of the present invention also provide a storage medium containing computer-executable instructions, which when executed by a computer processor, are configured to perform a method for SPI-based communication, comprising:
when the slave machine sends data, generating a data frame according to the data to be sent and a preset data frame structure; the structure of the data frame is 1 byte frame length, 0-60 byte payload and 2 byte CRC check value;
reading an interrupt register of the slave SPI interface module;
if the second interrupt bit of the interrupt register is cleared, sending the data frame to the slave SPI interface module by taking two bytes as a unit; the former byte is a written data address, the latter byte is data of the data frame corresponding to the written data address, the 1 st bit of the written data address is a read-write operation identification bit and is identified as a write operation, and the 2 nd to 7 th bits correspond to an address of a standby main cache area in the slave SPI interface module;
and executing write operation on an interrupt register of the slave SPI interface module after one data frame is sent, setting a second interrupt position of the interrupt register to trigger the host to generate interrupt, and executing SPI data receiving operation by the host.
Of course, the storage medium containing the computer-executable instructions provided by the embodiments of the present invention is not limited to the method operations described above, and may also perform related operations in the SPI-based communication method applied to the slave device provided by any embodiments of the present invention.
From the above description of the embodiments, it is obvious for those skilled in the art that the present invention can be implemented by software and necessary general hardware, and certainly, can also be implemented by hardware, but the former is a better embodiment in many cases. Based on such understanding, the technical solutions of the present invention may be embodied in the form of a software product, which can be stored in a computer-readable storage medium, such as a floppy disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a FLASH Memory (FLASH), a hard disk or an optical disk of a computer, and includes several instructions for enabling a computer device (which may be a personal computer, a server, or a network device) to execute the method according to the embodiments of the present invention.
It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.
Claims (9)
1. An SPI-based communication system, comprising:
the system comprises a host computer configured with a universal SPI interface module and at least one slave computer configured with a slave computer SPI interface module; the slave SPI interface module comprises a data area, a serial clock pin, a host input/slave output data pin, a host output/slave input data pin and a slave selection pin; the data area comprises an interrupt register, a master-to-slave buffer area and a slave-to-master buffer area, wherein a first interrupt bit of a master trigger slave and a second interrupt bit of the slave trigger master are arranged in the interrupt register; the universal SPI interface module is in signal connection with corresponding pins of the slave SPI interface module; a preset pin of the host is connected to an interrupt register of the slave SPI interface module, so that the host can write the first interrupt bit and read the second interrupt bit; the slave is configured to read the first interrupt bit and write the second interrupt bit.
2. An SPI-based communication method, comprising:
when the host sends data, generating a data frame according to the data to be sent and a preset data frame structure; the structure of the data frame is 1 byte frame length, 0-60 byte payload and 2 byte CRC check value;
reading an interrupt register of the slave SPI interface module;
if the first interrupt bit of the interrupt register is cleared, sending the data frame to the slave SPI interface module by taking two bytes as a unit; the former byte is a written data address, the latter byte is data of the data frame corresponding to the written data address, the 1 st bit of the written data address is a read-write operation identification bit and is identified as a write operation, and the 2 nd to 7 th bits correspond to the address of a master-to-backup cache area in the slave SPI interface module;
and executing write operation on an interrupt register of the slave SPI interface module after one data frame is sent, setting a first interrupt position of the interrupt register to trigger the slave to generate interrupt, and executing SPI data receiving operation by the slave.
3. The method of claim 2, further comprising:
when the host receives data, reading an interrupt register of the slave SPI interface module;
if the second interrupt position of the interrupt register is set, sending a byte preset data address to the slave SPI interface module so as to read the frame length of a data frame to be received; the 1 st bit of the preset data address is a read-write operation identification bit and is identified as read operation, and the 2 nd to 7 th bits are the addresses of the first registers of the standby to main cache areas in the slave SPI interface module;
circularly reading the data which is reserved in the main buffer area by taking one byte as a unit according to the frame length of the data frame to be received;
after reading the rest data, performing CRC;
if the CRC check is successful, the read data is stored;
if the CRC fails, discarding the read data;
and executing write operation on an interrupt register of the slave SPI interface module, and clearing a second interrupt bit of the interrupt register.
4. An SPI-based communication method, comprising:
when the slave machine sends data, generating a data frame according to the data to be sent and a preset data frame structure; the structure of the data frame is 1 byte frame length, 0-60 byte payload and 2 byte CRC check value;
reading an interrupt register of the slave SPI interface module;
if the second interrupt bit of the interrupt register is cleared, sending the data frame to the slave SPI interface module by taking two bytes as a unit; the former byte is a written data address, the latter byte is data of the data frame corresponding to the written data address, the 1 st bit of the written data address is a read-write operation identification bit and is identified as a write operation, and the 2 nd to 7 th bits correspond to an address of a standby main cache area in the slave SPI interface module;
and executing write operation on an interrupt register of the slave SPI interface module after one data frame is sent, setting a second interrupt position of the interrupt register to trigger the host to generate interrupt, and executing SPI data receiving operation by the host.
5. The method of claim 4, further comprising:
when the slave receives data, reading a data frame from the main buffer area to the standby buffer area according to memory mapping;
after reading the data frame, performing CRC check;
if the CRC check is successful, the read data is stored;
if the CRC fails, discarding the read data;
and executing write operation on an interrupt register of the slave SPI interface module, and clearing a first interrupt bit of the interrupt register.
6. An SPI interface communication based device, comprising:
one or more processors;
a memory for storing one or more programs;
a general SPI interface module;
when executed by the one or more processors, cause the one or more processors to implement the SPI-based communication method according to claim 2 or 3.
7. An SPI interface communication based device, comprising:
one or more processors;
a memory for storing one or more programs;
a slave SPI interface module;
when executed by the one or more processors, cause the one or more processors to implement the SPI-based communication method according to claim 4 or 5.
8. A storage medium containing computer-executable instructions for performing the SPI-based communication method of claim 2 or 3 when executed by a computer processor.
9. A storage medium containing computer-executable instructions for performing the SPI-based communication method of claim 4 or 5 when executed by a computer processor.
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