CN109495206A - A kind of user that be used to wirelessly communicate, the method and apparatus in base station - Google Patents
A kind of user that be used to wirelessly communicate, the method and apparatus in base station Download PDFInfo
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- CN109495206A CN109495206A CN201710811512.XA CN201710811512A CN109495206A CN 109495206 A CN109495206 A CN 109495206A CN 201710811512 A CN201710811512 A CN 201710811512A CN 109495206 A CN109495206 A CN 109495206A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0056—Systems characterized by the type of code used
- H04L1/0057—Block codes
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0056—Systems characterized by the type of code used
- H04L1/0071—Use of interleaving
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Abstract
This application discloses the method and apparatus in a kind of user that be used to wirelessly communicate, base station.First node executes the first operation.First bit sequence and the second bit sequence are outputting and inputting for the first operation respectively, and the bit and the first bit sequence that the second bit sequence includes are identical；The first kind bit subsequence that first bit sequence is arranged successively by Q1 forms, and preceding Q1-1 in the Q1 first kind bit subsequences being arranged successively are respectively by 1,3 ..., and 2 times of Q1 subtracts the bit composition that 3 resulting differences are arranged successively again；The second class bit subsequence that second bit sequence is arranged successively by Q2 forms, and the second class of Q2 bit sub-series of packets includes Q3 the second class bit subsequences pair, and any second class bit subsequence is to including the identical second class bit subsequence of two length；It is up to a bit in any second class bit subsequence and belongs to any first kind bit subsequence.The interleaving scheme that the application proposes has lower implementation complexity and more preferably performance.
Description
Technical field
The present invention relates to the transmission plans of the wireless signal in wireless communication system, more particularly to the biography that be used to interweave
Defeated method and apparatus.
Background technique
Polarization code (Polar Codes) is a kind of first by Bi Erken university, Turkey Erdal Arikan professor in 2008
The encoding scheme of secondary proposition is that symmetric binary input discrete memoryless channel(DMC) (B-DMC, Binary may be implemented in one kind
Input Discrete Memoryless Channel) capacity code building method.In 3GPP (3rd Generation
Partner Project, third generation cooperative partner program) in RAN1#87 meeting, 3GPP has been determined using polarization code scheme conduct
The control channel encoding scheme of 5G eMBB (enhancing mobile broadband) scene.For polarization code, in channel encoder and modulation
The operation that interweaves is introduced between mapper for the performance of polarization code, the especially performance under high order modulation, is very heavy
It wants.In 3GPPRAN1#90 meeting, the interleaver designs scheme based on triangle is adopted.
Summary of the invention
Inventors discovered through research that the existing interleaver based on triangle is to enter by row write, then read by column.This
Kind design scheme calculates complexity there are side length and element intertexture on triangle angle is insufficient, thus the problems such as influencing performance.
In view of the above-mentioned problems, this application discloses a solution.In the absence of conflict, the first segment of the application
The feature in embodiment and embodiment in point can be applied in second node, and vice versa.In the absence of conflict, originally
Feature in the embodiment and embodiment of application can be arbitrarily combined with each other.
This application discloses the methods in the first node that be used to wirelessly communicate characterized by comprising
Execute the first operation；
Wherein, the first bit sequence and the second bit sequence are outputting and inputting for first operation respectively, described the
Bit included by two bit sequences is identical with bit included by first bit sequence；First bit sequence is by Q1
A first kind bit subsequence being arranged successively forms, the preceding Q1-1 in the Q1 first kind bit subsequences being arranged successively
A first kind bit subsequence is respectively by 1,3 ..., and 2 times of Q1 subtracts the bit composition that 3 resulting differences are arranged successively again；Institute
It states the second class bit subsequence that the second bit sequence is arranged successively by Q2 to form, the Q2 the second analogies being arranged successively
It include Q3 the second class bit subsequences pair, the Q3 the second any second analogies of class bit subsequence centering in special subsequence
Special subsequence is to including the identical second class bit subsequence of two length；The Q2 the second sub- sequences of class bit being arranged successively
It is up to a bit in any second class bit subsequence in column and belongs to the Q1 first kind bit being arranged successively
Any one first kind bit subsequence in sequence；The Q1 and Q2 is greater than 1 positive integer respectively, and the Q3 is small
In the nonnegative integer of the Q2.
As one embodiment, the essence of the above method is, first operation is to be located at channel coding (Channel
Coding) intertexture (Interleaving) operation between modulation mapping (ModulationMapping), the above method propose
Interleaving scheme be based on triangular design.It is different with the existing interleaving scheme based on triangular design, in the above method
Interleaver in element be to be written in a manner of horizontal since the obtuse angle apex angle of triangle, then from any top of triangle
Angle starts to read in a manner of vertical line；And in the existing interleaving scheme based on triangular design, element is from quadrangle
Or a side of triangle is entered by row write, then is read by column.
Preceding Q1-1 first kind ratio as one embodiment, in the Q1 first kind bit subsequences being arranged successively
The quantity of included bit successively increases 2 in special subsequence, in the Q1 first kind bit subsequences being arranged successively
Resulting difference that Q1 of the quantity less than 2 times of bit included by the last one first kind bit subsequence subtracts 1.
As one embodiment, the quantity of included bit in the Q1 first kind bit subsequences being arranged successively
Successively increase 2.
As one embodiment, the interleaving scheme proposed in the above method is advantageous in that, and existing intertexture side at present
Case is compared, and the interleaving scheme that the above method proposes has simpler realization and more preferably performance.
As one embodiment, first bit sequence includes positive integer bit.
As one embodiment, second bit sequence includes positive integer bit.
As one embodiment, the number for the bit that first bit sequence and second bit sequence include is phase
With.
Any first kind bit as one embodiment, in the Q1 first kind bit subsequences being arranged successively
Sequence includes positive integer bit.
Any second class bit as one embodiment, in the Q2 the second class bit subsequences being arranged successively
Sequence includes positive integer bit.
As one embodiment, there is no a bits to belong to the Q1 sub- sequences of first kind bit being arranged successively simultaneously
Any two first kind bit subsequence in column.
As one embodiment, there is no a bits to belong to the Q2 the second sub- sequences of class bit being arranged successively simultaneously
Any two the second class bit subsequence in column.
The last one first kind ratio as one embodiment, in the Q1 first kind bit subsequences being arranged successively
The bit that special subsequence is arranged successively by P forms, and the P is positive integer.
As one embodiment, the P with 2 times of Q1 subtracts 1, and resulting difference is equal.
As one embodiment, resulting difference that Q1 of the P less than 2 times subtracts 1.
As one embodiment, first operation is to interweave (interleaving).
As one embodiment, the Q2 is equal to the Q1 and subtracts 1 again multiplied by 2.
As one embodiment, the Q2 is equal to the Q1 and subtracts 2 again multiplied by 2.
As one embodiment, the Q2 is equal to the Q3 and adds 1 again multiplied by 2.
As one embodiment, the Q2 is equal to the Q3 and adds 2 again multiplied by 2.
Any first kind bit as one embodiment, in the Q1 first kind bit subsequences being arranged successively
Bit in sequence is arranged successively.
Any second class bit as one embodiment, in the Q2 the second class bit subsequences being arranged successively
Bit in sequence is arranged successively.
As one embodiment, any second class bit subsequence centering of the Q3 the second class bit subsequence centerings
Two the second class bit subsequences be continuous in the second class bit subsequence that the Q2 is arranged successively.
As one embodiment, any second class bit subsequence centering of the Q3 the second class bit subsequence centerings
Two the second class bit subsequences be discontinuous in the second class bit subsequence that the Q2 is arranged successively.
As one embodiment, any second class bit subsequence centering of the Q3 the second class bit subsequence centerings
Two the second class bit subsequences among there are at least one the second class bit subsequences.
As one embodiment, for given second class bit of the Q3 the second class bit subsequence centerings
Sequence pair, there are Q5 among two the second class bit subsequences of the given second class bit subsequence centering to be arranged successively
The second class bit subsequence, the Q5 is positive integer.
As a sub- embodiment of above-described embodiment, the Q5 and described two second class bit subsequences are in the Q2
Position in a the second class bit subsequence being arranged successively is related.
It is last in the Q1 first kind bit subsequences being arranged successively as a sub- embodiment of above-described embodiment
The bit that one first kind bit subsequence is arranged successively by Q1 forms, and the Q5 is odd number.
As a sub- embodiment of above-described embodiment, position of the First ray in second bit sequence is more leaned on
Before, the Q5 is bigger, and the First ray is come in second bit sequence in described two second class bit subsequences
Earlier above the second class bit subsequence.
As a sub- embodiment of above-described embodiment, the Q5 the second class bit subsequence centering a for the Q3
All second class bit subsequences are to being identical.
As a sub- embodiment of above-described embodiment, described two second class bit subsequences are successively arranged at the Q2
Index in second class bit subsequence of column is a1 and a2 respectively, and the a1 and the a2 are being no more than the Q2 just respectively
Integer, the a1 are less than the a2, and the difference that the a2 subtracts 1 is equal to the difference that the Q2 subtracts the a1.
The last one first kind ratio as one embodiment, in the Q1 first kind bit subsequences being arranged successively
Q1 of the quantity of included bit equal to the 2 times resulting difference that subtracts 1 in special subsequence, 2 times of the Q1 subtracts 1 resulting difference and institute
It is equal to state Q2, the Q1 subtracts 1, and resulting difference is equal with the Q3.
As a sub- embodiment of above-described embodiment, second class of the Q3 the second class bit subsequence centerings
The quantity of bit included by bit subsequence is 1,2,3 respectively ..., 1) Q3 (i.e. since 1, is successively increased.
The last one first kind ratio as one embodiment, in the Q1 first kind bit subsequences being arranged successively
The quantity of included bit is less than or equal to Q1 in special subsequence, and 2 times of the Q1 subtracts 2, and resulting difference is equal with the Q2,
The Q1 subtracts 2, and resulting difference is equal with the Q3.
As a sub- embodiment of above-described embodiment, second class of the Q3 the second class bit subsequence centerings
The quantity of bit included by bit subsequence is 1,2,3 respectively ..., 1) Q3 (i.e. since 1, is successively increased.
The last one first kind ratio as one embodiment, in the Q1 first kind bit subsequences being arranged successively
The quantity of included bit is greater than Q1 and the resulting difference that subtracts 1 of the Q1 less than 2 times in special subsequence, 2 times of the Q1 subtracts 2 gained
Difference it is equal with the Q2, the Q1 subtracts 2, and resulting difference is equal with the Q3.
As a sub- embodiment of above-described embodiment, second class of the Q3 the second class bit subsequence centerings
The quantity of bit included by bit subsequence is Q3 two positive integer neither waited respectively, and the Q3 a two neither waits just whole
Array is made of at the first integer set, first integer set all positive integers except the removing Q8 from 1 to Q3, and 2 times
The Q1 subtract 1 and subtract again that the resulting difference of P is equal with the Q8, the P is the Q1 first kind bits being arranged successively
The quantity of included bit in the last one first kind bit subsequence in subsequence.
As one embodiment, the Q3 the second class bit subsequence centering first in second bit sequence
The quantity of bit included by second class bit subsequence of a appearance is 1.
As one embodiment, the Q3 the second class bit subsequence centering first in second bit sequence
The quantity of bit included by second class bit subsequence of a appearance is the Q3.
As one embodiment, the first node is UE (User Equipment, user equipment).
As one embodiment, the first node is base station.
According to the one aspect of the application characterized by comprising
Execute channel coding；
Wherein, first bit sequence is the output of the channel coding.
As one embodiment, the channel coding includes rate-matched (rate matching).
As one embodiment, the channel coding is encoded based on Turbo.
As one embodiment, the channel coding is based on LDPC, and (Low Density Parity Check, low-density are odd
Even parity check) coding.
As one embodiment, the channel coding is based on polarization (polar) coding.
As one embodiment, the channel coding is based on convolutional encoding.
As one embodiment, the input of the channel coding is third bit sequence, and the third bit sequence includes
Positive integer bit.
As a sub- embodiment of above-described embodiment, the bit in the third bit sequence is sequentially input the channel
It encodes in corresponding channel encoder.
According to the one aspect of the application characterized by comprising
Send the first wireless signal；
Wherein, second bit sequence be used to generate first wireless signal.
As one embodiment, first wireless signal is that second bit sequence successively passes through modulation mapper
(Modulation Mapper), layer mapper (Layer Mapper), precoding (Precoding), resource particle mapper
Output after (Generation) occurs for (Resource Element Mapper), multicarrier symbol.
As a sub- embodiment of above-described embodiment, the multicarrier symbol is OFDM (OrthogonalFrequency
Division Multiplexing, orthogonal frequency division multiplexing) symbol.
As a sub- embodiment of above-described embodiment, the multicarrier symbol is DFT-S-OFDM (Discrete
Fourier Transform Spread OFDM, discrete fourier change orthogonal frequency division multiplexing) symbol.
As a sub- embodiment of above-described embodiment, the multicarrier symbol is FBMC (Filter Bank Multi
Carrier, filter bank multi-carrier) symbol.
As one embodiment, first wireless signal is that second bit sequence successively passes through modulation mapper,
Layer mapper, conversion precoder (transform precoder, for generating complex valued signals), precoding, resource particle
Mapper, the output after multicarrier symbol generation.
As one embodiment, first wireless signal (is consequently not used for transmitting physical in physical layer control channel
The physical layer channel of layer data) on transmit.
As one embodiment, first wireless signal (can be used to carry physical layer in physical layer data channel
The physical layer channel of data) on transmit.
As one embodiment, the first node is UE.
As a sub- embodiment of above-described embodiment, first wireless signal is in PUCCH (Physical
UplinkControl Channel, Physical Uplink Control Channel) on transmit.
As a sub- embodiment of above-described embodiment, first wireless signal sPUCCH (short PUCCH, it is short
PUCCH it is transmitted on).
As a sub- embodiment of above-described embodiment, first wireless signal is in NR-PUCCH (New Radio
PUCCH, new wireless PUCCH) on transmit.
As a sub- embodiment of above-described embodiment, first wireless signal is in NB-PUCCH (NarrowBand
PUCCH, narrowband PUCCH) on transmit.
As a sub- embodiment of above-described embodiment, first wireless signal is in PUSCH (Physical Uplink
Shared CHannel, Physical Uplink Shared Channel) on transmit.
As a sub- embodiment of above-described embodiment, first wireless signal sPUSCH (short PUSCH, it is short
PUSCH it is transmitted on).
As a sub- embodiment of above-described embodiment, first wireless signal is in NR-PUSCH (NewRadio
PUSCH, new wireless PUSCH) on transmit.
As a sub- embodiment of above-described embodiment, first wireless signal is in NB-PUSCH (NarrowBand
PUSCH, narrowband PUSCH) on transmit.
As one embodiment, the first node is base station.
As a sub- embodiment of above-described embodiment, first wireless signal is in PDCCH (Physical
DownlinkControl Channel, Physical Downlink Control Channel) on transmit.
As a sub- embodiment of above-described embodiment, first wireless signal sPDCCH (short PDCCH, it is short
PDCCH it is transmitted on).
As a sub- embodiment of above-described embodiment, first wireless signal is in NR-PDCCH (New Radio
PDCCH, new wireless PDCCH) on transmit.
As a sub- embodiment of above-described embodiment, first wireless signal is in NB-PDCCH (NarrowBand
PDCCH, narrowband PDCCH) on transmit.
As a sub- embodiment of above-described embodiment, first wireless signal is in PDSCH (Physical
Downlink Shared CHannel, Physical Downlink Shared Channel) on transmission upload it is defeated.
As a sub- embodiment of above-described embodiment, first wireless signal sPDSCH (short PDSCH, it is short
PDSCH it is transmitted on).
As a sub- embodiment of above-described embodiment, first wireless signal is in NR-PDSCH (NewRadio
PDSCH, new wireless PDSCH) on transmit.
As a sub- embodiment of above-described embodiment, first wireless signal is in NB-PDSCH (NarrowBand
PDSCH, narrowband PDSCH) on transmit.
According to the one aspect of the application, which is characterized in that the Q2 adds 1 sum equal with 2 product with the Q1.
As one embodiment, the Q2 is equal to the Q1 and subtracts 1 again multiplied by 2.
As one embodiment, the Q3 is equal to after the Q2 subtracts 1 again divided by 2.
As one embodiment, the Q3 is equal with the difference that the Q2 subtracts 1 is equal to 2 product.
The last one first kind ratio as one embodiment, in the Q1 first kind bit subsequences being arranged successively
Special subsequence is made of the bit that P is arranged successively, and the P with 2 times of Q1 subtracts 1, and resulting difference is equal.
According to the one aspect of the application, which is characterized in that the Q2 adds 2 sum equal with 2 product with the Q1.
As one embodiment, the Q2 is equal to the Q1 and subtracts 2 again multiplied by 2
As one embodiment, the Q3 is equal to after the Q2 subtracts 2 again divided by 2.
As one embodiment, the Q3 is equal with the difference that the Q2 subtracts 2 is equal to 2 product.
The last one first kind ratio as one embodiment, in the Q1 first kind bit subsequences being arranged successively
The bit that special subsequence is arranged successively by P forms, the positive integer for resulting difference that the Q1 that the P is less than 2 times subtracts 1.
According to the one aspect of the application, which is characterized in that the first node is base station.
As one embodiment, first bit sequence includes Downlink Control Information, and the first node is base station.
As a sub- embodiment of above-described embodiment, the Downlink Control Information includes corresponding data { when occupied
Domain resource, occupied frequency domain resource, MCS (Modulation and Coding Scheme, modulation coding scheme), RV
(Redundancy Version, redundancy versions), NDI (New Data Indicator, new data instruction), HARQ (Hybrid
At least one of Automatic Repeat reQuest, hybrid automatic repeat-request) process number }.
According to the one aspect of the application, which is characterized in that the first node is user equipment
As one embodiment, first bit sequence includes ascending control information, and the first node is that user sets
It is standby.
As a sub- embodiment of above-described embodiment, the ascending control information includes { HARQ-ACK
(Acknowledgement, confirmation), CSI (ChannelStateInformation, channel state information), SR
At least one of (Scheduling Request, scheduling request), CRI (CSI-RS resource indication) }.
This application discloses the methods in the second node that be used to wirelessly communicate characterized by comprising
Execute the second operation；
Wherein, the first sequence of real numbers and the second sequence of real numbers are the output and input of second operation respectively, described the
Real number included by two sequence of real numbers is identical with real number included by first sequence of real numbers；First sequence of real numbers is by Q1
A first kind real number subsequence being arranged successively forms, the preceding Q1-1 in the Q1 first kind real number subsequences being arranged successively
A first kind real number subsequence is respectively by 1,3 ..., and 2 times of Q1 subtracts the real number composition that 3 resulting differences are arranged successively again；Institute
It states the second class real number subsequence that the second sequence of real numbers is arranged successively by Q2 to form, the Q2 the second classes being arranged successively are real
It include Q3 the second class real number subsequences pair in number subsequence, the Q3 any second classes of the second class real number subsequence centering are real
Number subsequence is to including the identical second class real number subsequence of two length；The Q2 the second sub- sequences of class real number being arranged successively
It is up to a real number in any second class real number subsequence in column and belongs to the Q1 first kind real number being arranged successively
Any one first kind real number subsequence in sequence；The Q1 and Q2 is greater than 1 positive integer respectively, and the Q3 is small
In the nonnegative integer of the Q2.
As one embodiment, the number for the real number that first sequence of real numbers includes and first bit sequence include
The number of bit be bit one equal, that the real number and first bit sequence that first sequence of real numbers includes include
One is corresponding, and any real number is the Soft Inform ation of corresponding bit in first sequence of real numbers.
As one embodiment, the number for the real number that second sequence of real numbers includes and second bit sequence include
The number of bit be bit one equal, that the real number and second bit sequence that second sequence of real numbers includes include
One is corresponding, and any real number is the Soft Inform ation of corresponding bit in second sequence of real numbers.
As one embodiment, second operation is to deinterleave (de-interleaving).
As one embodiment, first sequence of real numbers includes positive integer real number.
As one embodiment, second sequence of real numbers includes positive integer real number.
As one embodiment, the number for the real number that first sequence of real numbers and second sequence of real numbers include is phase
With.
Any first kind real number as one embodiment, in the Q1 first kind real number subsequences being arranged successively
Sequence includes positive integer real number.
Any second class real number as one embodiment, in the Q2 the second class real number subsequences being arranged successively
Sequence includes positive integer real number.
As one embodiment, there is no a real numbers to belong to the Q1 sub- sequences of first kind real number being arranged successively simultaneously
Any two first kind real number subsequence in column.
As one embodiment, there is no a real numbers to belong to the Q2 the second sub- sequences of class real number being arranged successively simultaneously
Any two the second class real number subsequence in column.
As one embodiment, the last one first kind in the Q1 first kind real number subsequences being arranged successively is real
The real number that number subsequence is arranged successively by Q1 forms.
As one embodiment, the last one first kind in the Q1 first kind real number subsequences being arranged successively is real
The real number that number subsequence is arranged successively by P forms, and the P is less than the positive integer of the Q1.
Any first kind real number as one embodiment, in the Q1 first kind real number subsequences being arranged successively
Real number in sequence is arranged successively.
Any second class real number as one embodiment, in the Q2 the second class real number subsequences being arranged successively
Real number in sequence is arranged successively.
As one embodiment, any second class real number subsequence centering of the Q3 the second class real number subsequence centerings
Two the second class real number subsequences be continuous in second sequence of real numbers.
As one embodiment, any second class real number subsequence centering of the Q3 the second class real number subsequence centerings
Two the second class real number subsequences be discontinuous in second sequence of real numbers.
As one embodiment, any second class real number subsequence centering of the Q3 the second class real number subsequence centerings
Two the second class real number subsequences among there are at least one the second class real number subsequences.
As one embodiment, for given second class real number of the Q3 the second class real number subsequence centerings
Sequence pair, there are Q5 among two the second class real number subsequences of the given second class real number subsequence centering to be arranged successively
The second class real number subsequence, the Q5 is positive integer.
As a sub- embodiment of above-described embodiment, the Q5 and described two second class real number subsequences are in the Q2
Position in a the second class real number subsequence being arranged successively is related,
It is last in the Q1 first kind real number subsequences being arranged successively as a sub- embodiment of above-described embodiment
The real number that one first kind real number subsequence is arranged successively by Q1 forms, and the Q5 is odd number.
As a sub- embodiment of above-described embodiment, position of second sequence in second sequence of real numbers is more leaned on
Before, the Q5 is bigger, and second sequence is to come second sequence of real numbers in described two second class real number subsequences
In a second class real number subsequence earlier above.
As a sub- embodiment of above-described embodiment, described two second class real number subsequences are successively arranged at the Q2
Index in second class real number subsequence of column is a1 and a2 respectively, and the a1 and the a2 are being no more than the Q2 just respectively
Integer, the a1 are less than the a2, and the a2 adds 1 sum to subtract the difference of the a1 equal to the Q2.
As one embodiment, the last one first kind in the Q1 first kind real number subsequences being arranged successively is real
Q1 of the quantity equal to 2 times of the included real number resulting difference that subtracts 1 in number subsequences, 2 times of the Q1 subtracts 1 resulting difference and institute
It is equal to state Q2, the Q1 subtracts 1, and resulting difference is equal with the Q3.
As a sub- embodiment of above-described embodiment, second class of the Q3 the second class real number subsequence centerings
The quantity of real number included by real number subsequence is 1,2,3 respectively ..., 1) Q3 (i.e. since 1, is successively increased.
As one embodiment, the last one first kind in the Q1 first kind real number subsequences being arranged successively is real
The quantity of included real number is less than or equal to Q1 in number subsequence, and 2 times of the Q1 subtracts 2, and resulting difference is equal with the Q2,
The Q1 subtracts 2, and resulting difference is equal with the Q3.
As a sub- embodiment of above-described embodiment, second class of the Q3 the second class real number subsequence centerings
The quantity of real number included by real number subsequence is 1,2,3 respectively ..., 1) Q2 (i.e. since 1, is successively increased.
As one embodiment, the last one first kind in the Q1 first kind real number subsequences being arranged successively is real
The quantity of included real number is greater than Q1 and the resulting difference that subtracts 1 of the Q1 less than 2 times in number subsequences, 2 times of the Q1 subtracts 2 gained
Difference it is equal with the Q2, the Q1 subtracts 2, and resulting difference is equal with the Q3.
As a sub- embodiment of above-described embodiment, second class of the Q3 the second class real number subsequence centerings
The quantity of real number included by real number subsequence is Q3 two positive integer neither waited respectively, and the Q3 a two neither waits just whole
Array is at the first integer set, and first integer set from all positive integers except the 1 removing Q8 into Q3 by forming, and 2
Times the Q1 subtract 1 and subtract again that the resulting difference of P is equal with the Q8, the P is a first kind reality being arranged successively of the Q1
The quantity of included real number in the last one first kind real number subsequence in number subsequence.
As one embodiment, the Q3 the second class real number subsequence centering first in second sequence of real numbers
The quantity of bit included by second class real number subsequence of a appearance is 1.
As one embodiment, the Q3 the second class real number subsequence centering first in second sequence of real numbers
The quantity of bit included by second class real number subsequence of a appearance is Q3.
As one embodiment, the second node is base station.
As one embodiment, the second node is UE (User Equipment, user equipment).
According to the one aspect of the application characterized by comprising
Execute channel decoding；
Wherein, first sequence of real numbers is the input of the channel decoding.
As one embodiment, first bit sequence is the input of the corresponding channel coding of the channel decoding.
According to the one aspect of the application characterized by comprising
Receive the first wireless signal；
Wherein, first wireless signal be used to generate second sequence of real numbers.
As one embodiment, second bit sequence be used to generate first wireless signal.
As one embodiment, second sequence of real numbers is that first wireless signal successively passes through DFT (Discrete
Fourier Transform, discrete Fourier transform), multiple antennas detection obtains after constellation demodulation (DeModulation).
As one embodiment, second sequence of real numbers is that first wireless signal successively passes through DFT, balanced, more
Antenna detection obtains after constellation demodulation.
As one embodiment, second sequence of real numbers is first wireless signal by { DFT, balanced, multiple antennas
Detection, constellation demodulation } one of or it is a variety of after obtain.
According to the one aspect of the application, which is characterized in that the Q2 adds 1 sum equal with 2 product with the Q1.
As one embodiment, the Q3 is equal with the difference that the Q2 subtracts 1 is equal to 2 product.
The last one first kind ratio as one embodiment, in the Q1 first kind bit subsequences being arranged successively
Special subsequence is made of the bit that P is arranged successively, and the P with 2 times of Q1 subtracts 1, and resulting difference is equal.
According to the one aspect of the application, which is characterized in that the Q2 adds 2 sum equal with 2 product with the Q1.
As one embodiment, the Q3 is equal with the difference that the Q2 subtracts 2 is equal to 2 product.
The last one first kind ratio as one embodiment, in the Q1 first kind bit subsequences being arranged successively
The bit that special subsequence is arranged successively by P forms, the positive integer for resulting difference that the Q1 that the P is less than 2 times subtracts 1.
According to the one aspect of the application, which is characterized in that the second node is user equipment.
According to the one aspect of the application, which is characterized in that the second node is base station.
This application discloses the equipment in the first node that be used to wirelessly communicate characterized by comprising
First processing module executes the first operation；
Wherein, the first bit sequence and the second bit sequence are outputting and inputting for first operation respectively, described the
Bit included by two bit sequences is identical with bit included by first bit sequence；First bit sequence is by Q1
A first kind bit subsequence being arranged successively forms, the preceding Q1-1 in the Q1 first kind bit subsequences being arranged successively
A first kind bit subsequence is respectively by 1,3 ..., and 2 times of Q1 subtracts the bit composition that 3 resulting differences are arranged successively again；Institute
It states the second class bit subsequence that the second bit sequence is arranged successively by Q2 to form, the Q2 the second analogies being arranged successively
It include Q3 the second class bit subsequences pair, the Q3 the second any second analogies of class bit subsequence centering in special subsequence
Special subsequence is to including the identical second class bit subsequence of two length；The Q2 the second sub- sequences of class bit being arranged successively
It is up to a bit in any second class bit subsequence in column and belongs to the Q1 first kind bit being arranged successively
Any one first kind bit subsequence in sequence；The Q1 and Q2 is greater than 1 positive integer respectively, and the Q3 is small
In the nonnegative integer of the Q2.
As one embodiment, the equipment in the above-mentioned first node that be used to wirelessly communicate is characterized in that, described the
One processing module also executes channel coding；Wherein, first bit sequence is the output of the channel coding.
As one embodiment, the equipment in the above-mentioned first node that be used to wirelessly communicate is characterized in that, the Q2
Add 1 sum equal with 2 product with the Q1.
As one embodiment, the equipment in the above-mentioned first node that be used to wirelessly communicate is characterized in that, the Q2
Add 2 sum equal with 2 product with the Q1.
As one embodiment, the equipment in the above-mentioned first node that be used to wirelessly communicate is characterized in that, described the
One node is base station.
As one embodiment, the equipment in the above-mentioned first node that be used to wirelessly communicate is characterized in that, described the
One node users equipment.
As one embodiment, the equipment in the above-mentioned first node that be used to wirelessly communicate is characterised by comprising:
First sender module sends the first wireless signal；
Wherein, second bit sequence be used to generate first wireless signal.
This application discloses the equipment in the second node that be used to wirelessly communicate characterized by comprising
Second processing module executes the second operation；
Wherein, the first sequence of real numbers and the second sequence of real numbers are the output and input of second operation respectively, described the
Real number included by two sequence of real numbers is identical with real number included by first sequence of real numbers；First sequence of real numbers is by Q1
A first kind real number subsequence being arranged successively forms, the preceding Q1-1 in the Q1 first kind real number subsequences being arranged successively
A first kind real number subsequence is respectively by 1,3 ..., and 2 times of Q1 subtracts the real number composition that 3 resulting differences are arranged successively again；Institute
It states the second class real number subsequence that the second sequence of real numbers is arranged successively by Q2 to form, the Q2 the second classes being arranged successively are real
It include Q3 the second class real number subsequences pair in number subsequence, the Q3 any second classes of the second class real number subsequence centering are real
Number subsequence is to including the identical second class real number subsequence of two length；The Q2 the second sub- sequences of class real number being arranged successively
It is up to a real number in any second class real number subsequence in column and belongs to the Q1 first kind real number being arranged successively
Any one first kind real number subsequence in sequence；The Q1 and Q2 is greater than 1 positive integer respectively, and the Q3 is small
In the nonnegative integer of the Q2.
As one embodiment, the equipment in the above-mentioned second node that be used to wirelessly communicate is characterized in that, described the
Two processing modules also execute channel decoding；Wherein, first sequence of real numbers is the input of the channel decoding.
As one embodiment, the equipment in the above-mentioned second node that be used to wirelessly communicate is characterized in that, the Q2
Add 1 sum equal with 2 product with the Q1.
As one embodiment, the equipment in the above-mentioned second node that be used to wirelessly communicate is characterized in that, the Q2
Add 2 sum equal with 2 product with the Q1.
As one embodiment, the equipment in the above-mentioned second node that be used to wirelessly communicate is characterized in that, described the
Two nodes are user equipmenies.
As one embodiment, the equipment in the above-mentioned second node that be used to wirelessly communicate is characterized in that, described the
Two nodes are user base stations.
As one embodiment, the equipment in the above-mentioned second node that be used to wirelessly communicate is characterised by comprising:
First receiver module receives the first wireless signal；
Wherein, first wireless signal be used to generate second sequence of real numbers.
It is compared as one embodiment with traditional scheme, the application has following advantage:
The application be positioned at channel coding (Channel Coding) and modulation map (ModulationMapping) it
Between intertexture (Interleaving) operation propose a kind of novel interleaving scheme.It is compared with current existing interleaving scheme,
The interleaving scheme that the application proposes has lower implementation complexity and more preferably performance.
Detailed description of the invention
By reading referring to the detailed description of non-limiting embodiments in the following drawings, other spies of the application
Sign, objects and advantages will become more apparent:
Fig. 1 shows the flow chart operated according to the execution first of one embodiment of the application；
Fig. 2 shows the schematic diagrames according to the network architecture of one embodiment of the application；
Fig. 3 shows the reality of the radio protocol architecture of the user plane and control plane according to one embodiment of the application
Apply the schematic diagram of example；
Fig. 4 shows the schematic diagram of enode and UE according to one embodiment of the application；
Fig. 5 shows the flow chart of the wireless transmission of one embodiment according to the application；
Fig. 6 shows the flow chart of the wireless transmission of another embodiment according to the application；
Fig. 7 shows relationship between the first bit sequence and the second bit sequence according to one embodiment of the application
Schematic diagram；
Fig. 8 shows relationship between the first bit sequence and the second bit sequence according to another embodiment of the application
Schematic diagram；
Fig. 9 shows relationship between the first bit sequence and the second bit sequence according to another embodiment of the application
Schematic diagram；
Figure 10 shows and closes between the first bit sequence and the second bit sequence according to another embodiment of the application
The schematic diagram of system；
Figure 11 shows and closes between the first bit sequence and the second bit sequence according to another embodiment of the application
The schematic diagram of system；
Figure 12 shows the schematic diagram of the first wireless signal of generation according to one embodiment of the application；
Figure 13 shows the structural block diagram for the processing unit in first node of one embodiment according to the application；
Figure 14 shows the structural block diagram for the processing unit in second node of one embodiment according to the application；
Figure 15 shows and closes between the first bit sequence and the second bit sequence according to another embodiment of the application
The schematic diagram of system；
Figure 16 shows and closes between the first bit sequence and the second bit sequence according to another embodiment of the application
The schematic diagram of system；
Figure 17 shows close between the first bit sequence and the second bit sequence according to another embodiment of the application
The schematic diagram of system.
Embodiment 1
Embodiment 1 illustrates the flow chart for executing the first operation, as shown in Fig. 1.
In embodiment 1, the first node in the application executes the first operation.Wherein, the first bit sequence and
Two bit sequences are outputting and inputting for first operation, bit included by second bit sequence and described the respectively
Bit included by one bit sequence is identical；The first kind bit subsequence group that first bit sequence is arranged successively by Q1
The preceding Q1-1 first kind bit subsequence in first kind bit subsequences being arranged successively at, the Q1 respectively by 1,
3 ..., 2 times of Q1 subtracts the bit composition that 3 resulting differences are arranged successively again；Second bit sequence is successively arranged by Q2
Second class bit subsequence of column forms, and includes Q3 the second analogies in the Q2 the second class bit subsequences being arranged successively
Special subsequence pair, the Q3 the second any second class bit subsequences of class bit subsequence centering are to identical including two length
The second class bit subsequence；Any second class bit subsequence in the Q2 the second class bit subsequences being arranged successively
In a be up to bit belong to any one first kind bit in the first kind bit subsequence that the Q1 is arranged successively
Subsequence；The Q1 and Q2 is greater than 1 positive integer respectively, and the Q3 is less than the nonnegative integer of the Q2.
As one embodiment, first bit sequence includes positive integer bit.
As one embodiment, second bit sequence includes positive integer bit.
As one embodiment, the number for the bit that first bit sequence and second bit sequence include is phase
With.
Any first kind bit as one embodiment, in the Q1 first kind bit subsequences being arranged successively
Sequence includes positive integer bit.
Any second class bit as one embodiment, in the Q2 the second class bit subsequences being arranged successively
Sequence includes positive integer bit.
As one embodiment, there is no a bits to belong to the Q1 sub- sequences of first kind bit being arranged successively simultaneously
Any two first kind bit subsequence in column.
As one embodiment, there is no a bits to belong to the Q2 the second sub- sequences of class bit being arranged successively simultaneously
Any two the second class bit subsequence in column.
The last one first kind ratio as one embodiment, in the Q1 first kind bit subsequences being arranged successively
To subtract 1 resulting that bit that difference is arranged successively forms by 2 times of Q1 for special subsequence.
The last one first kind ratio as one embodiment, in the Q1 first kind bit subsequences being arranged successively
The bit that special subsequence is arranged successively by P forms, the positive integer for resulting difference that the Q1 that the P is less than 2 times subtracts 1.
As one embodiment, first operation is to interweave (interleaving).
As one embodiment, the Q2 is equal to the Q1 and subtracts 1 again multiplied by 2.
As one embodiment, the Q2 is equal to the Q1 and subtracts 2 again multiplied by 2.
As one embodiment, the Q2 is equal to the Q3 and adds 1 again multiplied by 2.
As one embodiment, the Q2 is equal to the Q3 and adds 2 again multiplied by 2.
Any first kind bit as one embodiment, in the Q1 first kind bit subsequences being arranged successively
Bit in sequence is arranged successively.
Any second class bit as one embodiment, in the Q2 the second class bit subsequences being arranged successively
Bit in sequence is arranged successively.
As one embodiment, a second any second class bit subsequence centering of class bit subsequence centering of the Q3
The position in the second class bit subsequence that two the second class bit subsequences are arranged successively at the Q2 is adjacent.
As one embodiment, a second any second class bit subsequence centering of class bit subsequence centering of the Q3
The position in the second class bit subsequence that two the second class bit subsequences are arranged successively at the Q2 is non-conterminous.
As one embodiment, the Q3 the second class bit subsequence centering first in second bit sequence
The quantity of bit included by second class bit subsequence of a appearance is 1.
As one embodiment, the Q3 the second class bit subsequence centering first in second bit sequence
The quantity of bit included by second class bit subsequence of a appearance is the Q3.
The last one first kind ratio as one embodiment, in the Q1 first kind bit subsequences being arranged successively
Q1 of the quantity of included bit equal to the 2 times resulting difference that subtracts 1 in special subsequence, 2 times of the Q1 subtracts 1 resulting difference and institute
It is equal to state Q2, the Q1 subtracts 1, and resulting difference is equal with the Q3.
As a sub- embodiment of above-described embodiment, second class of the Q3 the second class bit subsequence centerings
The quantity of bit included by bit subsequence is 1,2,3 respectively ..., 1) Q3 (i.e. since 1, is successively increased.
The last one first kind ratio as one embodiment, in the Q1 first kind bit subsequences being arranged successively
The quantity of included bit is less than or equal to Q1 in special subsequence, and 2 times of the Q1 subtracts 2, and resulting difference is equal with the Q2,
The Q1 subtracts 2, and resulting difference is equal with the Q3.
As a sub- embodiment of above-described embodiment, second class of the Q3 the second class bit subsequence centerings
The quantity of bit included by bit subsequence is 1,2,3 respectively ..., 1) Q3 (i.e. since 1, is successively increased.
The last one first kind ratio as one embodiment, in the Q1 first kind bit subsequences being arranged successively
The quantity of included bit is greater than Q1 and the resulting difference that subtracts 1 of the Q1 less than 2 times in special subsequence, 2 times of the Q1 subtracts 2 gained
Difference it is equal with the Q2, the Q1 subtracts 2, and resulting difference is equal with the Q3.
As a sub- embodiment of above-described embodiment, second class of the Q3 the second class bit subsequence centerings
The quantity of bit included by bit subsequence is Q3 two positive integer neither waited respectively, and the Q3 a two neither waits just whole
Array is made of at the first integer set, first integer set all positive integers except the removing Q8 from 1 to Q3, and 2 times
The Q1 subtract 1 and subtract again that the resulting difference of P is equal with the Q8, the P is the Q1 first kind bits being arranged successively
The quantity of included bit in the last one first kind bit subsequence in subsequence.
As one embodiment, the first node is UE (User Equipment, user equipment).
As one embodiment, the first node is base station.
Embodiment 2
Embodiment 2 illustrates the schematic diagram of the network architecture, as shown in Fig. 2.
Attached drawing 2 illustrates LTE (Long-Term Evolution, long term evolution), LTE-A (Long-Term
Evolution Advanced, enhance long term evolution) and future 5G system the network architecture 200.LTE network framework 200 can claim
For EPS (Evolved Packet System, evolved packet system) 200.EPS 200 may include one or more UE
(User Equipment, user equipment) 201, E-UTRAN-NR (evolution UMTS Terrestrial Radio Access Network network-is new wireless)
202,5G-CN (5G-CoreNetwork, 5G core net)/EPC (Evolved Packet Core, evolution block core) 210,
HSS (Home Subscriber Server, home signature user server) 220 and Internet service 230.Wherein, UMTS pairs
Answer universal mobile telecommunications service (Universal Mobile Telecommunications System).EPS can connect with other
Enter network interconnection, but in order to not show these entity/interfaces simply.As shown in Fig. 2, EPS offer packet-switched services, however institute
The technical staff in category field will be apparent that each conception of species presented through the application, which extends to, provides circuit switched service
Network.E-UTRAN-NR includes NR node B (gNB) 203 and other gNB204.GNB203 provides user and control towards UE201
Plane protocol terminations processed.GNB203 can be connected to other gNB204 via X2 interface (for example, backhaul).GNB203 is alternatively referred to as base
It stands, base transceiver station, radio base station, radio transceiver, transceiver function, set of basic (BSS), extended service set
Close (ESS), TRP (transmitting and receiving point) or some other suitable term.GNB203 is provided for UE201 and is connect to 5G-CN/EPC210
Access point.The example of UE201 includes cellular phone, smart phone, session initiation protocol (SIP) phone, laptop computer, a
Personal digital assistant (PDA), satelline radio, global positioning system, multimedia device, video-unit, digital audio-frequency player (example
Such as, MP3 player), camera, game console, unmanned plane, aircraft, narrowband Physical Network equipment, machine type communication device,
Land craft, automobile, wearable device or any other like functional device.Those skilled in the art can also incite somebody to action
UE201 be known as mobile station, subscriber stations, mobile unit, subscriber unit, radio-cell, remote unit, mobile device, wireless device,
Wireless communication device, remote-control device, mobile subscriber stations, access terminal, mobile terminal, wireless terminal, remote terminal, hand-held set,
User agent, mobile client, client or some other suitable term.GNB203 is connected to 5G-CN/ by S1 interface
EPC210.5G-CN/EPC210 include MME 211, other MME214, S-GW (Service Gateway, gateway) 212 with
And P-GW (Packet Date Network Gateway, grouped data network gateway) 213.MME211 be processing UE201 with
The control node of signaling between 5G-CN/EPC210.Generally, MME211 provides carrying and connection management.All User IPs
(Internet Protocal, Internet Protocol) packet is transmitted by S-GW212, and S-GW212 is itself coupled to P-GW213.P-
GW213 provides the distribution of UE IP address and other functions.P-GW213 is connected to Internet service 230.Internet service 230 is wrapped
It includes operator and corresponds to the Internet protocol service, specifically may include internet, Intranet, IMS (IP Multimedia
Subsystem, IP multimedia subsystem) and PS streaming service (PSS).
As one embodiment, the UE201 corresponds to the first node in the application, and the gNB203 corresponds to this Shen
Please in the second node.
As one embodiment, the UE201 corresponds to the second node in the application, and the gNB203 corresponds to this Shen
Please in the first node.
Embodiment 3
Embodiment 3 illustrates user plane and controls the schematic diagram of the embodiment of the radio protocol architecture of plane, such as attached drawing 3
It is shown.
Attached drawing 3 is schematic diagram of the explanation for the embodiment of user plane and the radio protocol architecture for controlling plane, attached
Fig. 3 shows the radio protocol architecture for being used for UE and gNB: layer 1, layer 2 and layer 3 with three layers.1 (L1 layers) of layer are lowermost layer and reality
Apply various PHY (physical layer) signal processing function.L1 layers are referred to as PHY301 herein.Layer 2 (L2 layers) 305 PHY301 it
On, and be responsible for passing through link of the PHY301 between UE and gNB.In user plane, L2 layer 305 includes MAC (Medium
Access Control, media access control) sublayer 302, RLC (Radio Link Control, radio link layer control association
View) sublayer 303 and PDCP (Packet Data Convergence Protocol, Packet Data Convergence Protocol) sublayer 304, this
A little layer terminates at the gNB on network side.Although it is not shown, but UE can have several protocol layers on L2 layer 305, wrap
The network layer (for example, IP layers) terminated at the P-GW213 on network side and the other end for terminating at connection are included (for example, distal end
UE, server etc.) at application layer.The multichannel that PDCP sublayer 304 is provided between different radio carrying and logic channel is multiple
With.PDCP sublayer 304 provides the header compressed for upper layer data packet also to reduce radio transmitting expense, passes through encryption data
It wraps and safety is provided, and the handover to UE provided between gNB is supported.Rlc sublayer 303 provides upper layer data packet
Segmentation and Reassembly dress, re-emitting for lost data packets and reordering to compensate unordered as caused by HARQ connect for data packet
It receives.Media access control sublayer 302 provides the multiplexing between logical AND transport channel.Media access control sublayer 302 is also responsible for distributing one between UE
Various radio resources (for example, resource block) in a cell.Media access control sublayer 302 is also responsible for HARQ operation.In the control plane,
Radio protocol architecture for UE and gNB is substantially the same for physical layer 301 and L2 layer 305, but not for controlling
The header compressed function of plane processed.Control plane further includes RRC (Radio Resource Control, nothing in layer 3 (L3 layers)
The control of line electric resources) sublayer 306.RRC sublayer 306 is responsible for obtaining radio resource (that is, radio bearer) and uses gNB and UE
Between RRC signaling configure lower layer.
The first node of the radio protocol architecture suitable for the application as one embodiment, in attached drawing 3.
The second node of the radio protocol architecture suitable for the application as one embodiment, in attached drawing 3.
As one embodiment, first bit sequence in the application is created on the PHY301.
As one embodiment, second bit sequence in the application is created on the PHY301.
As one embodiment, first wireless signal in the application is created on the PHY301.
Embodiment 4
Embodiment 4 illustrates enode and the schematic diagram of UE, as shown in Fig. 4.
GNB410 includes controller/processor 475, and memory 476 receives processor 470, transmited processor 416, channel
Coding/interleaver 477, channel decoding/deinterleaver 478, emitter/receiver 418 and antenna 420.
UE450 includes controller/processor 459, memory 460, data source 467, transmited processor 468, reception processing
Device 456, channel coding/interleaver 457, channel decoding/deinterleaver 458, emitter/receiver 454 and antenna 452.
In DL (Downlink, downlink), at gNB, the upper layer data packet from core network be provided to controller/
Processor 475.Controller/processor 475 implements L2 layers of functionality.In DL, controller/processor 475 provides header pressure
Contracting, encryption, packet are segmented and reorder, the multiplexing between logical AND transport channel, and based on the measurement pair of various priority
The radio resource of UE450 is allocated.Controller/processor 475 is also responsible for HARQ operation, lost package re-emits, and
To the signaling of UE450.Transmited processor 416 and channel coding/interleaver 477 are implemented various for L1 layers (that is, physical layer)
Signal processing function.Channel coding/interleaver 477 implements coding and interweaves to promote the forward error correction at UE450
(FEC).Transmited processor 416 is implemented based on various modulation schemes (for example, binary phase shift keying (BPSK), quadrature phase shift keying
(QPSK), M phase-shift keying (PSK) (M-PSK), M quadrature amplitude modulation (M-QAM)) signal cluster mapping, and to it is encoded and warp
Modulated symbol carries out spatial pre-coding/beam shaping processing, generates one or more spatial flows.Transmited processor 416 with
Each spatial flow is mapped to subcarrier afterwards, is multiplexed in the time and/or frequency domain with reference signal (for example, pilot tone), and
The physical channel of carrying time domain multi-carrier symbols stream is then generated using fast Fourier inverse transformation (IFFT).Each transmitter
The base band multicarrier symbol circulation chemical conversion RF flow that 418 transmited processors 416 provide, is subsequently provided different antennae 420.
In DL (Downlink, downlink), at UE450, each receiver 454 receives letter by its respective antenna 452
Number.Each receiver 454 restores the information being modulated on radio-frequency carrier, and RF flow is converted to base band multicarrier symbol stream and is mentioned
It is supplied to and receives processor 456.Receive the various signal processing function of L1 layers of processor 456 and the implementation of channel decoding/deinterleaver 458
Energy.It receives processor 456 and base band multicarrier symbol stream is transformed into frequency domain from time domain using Fast Fourier Transform (FFT).?
Frequency domain, physical layer data signal and reference signal are received the demultiplexing of processor 456, and wherein reference signal will be used for channel and estimate
Meter, physical layer data are resumed out the spatial flow using UE450 as destination by multiple antennas detection in receiving processor 456.
Symbol on each spatial flow is demodulated and restores in receiving processor 456, and generates soft decision.Subsequent channel decoding/solution
Interleaver 458 decodes and deinterleaves the soft decision to restore the upper layer data by gNB410 transmitting and control on the physical channel
Signal.Then provide upper layer data and control signal to controller/processor 459.Controller/processor 459 implements L2 layers
Function.Controller/processor can be associated with the memory 460 of storage program code and data.Memory 460 can be described as counting
Calculation machine readable media.Demultiplexing, package-restructuring in DL, between the offer of controller/processor 459 conveying and logic channel
Dress, decryption, header decompression, control signal processing are to restore the upper layer data packet from core network.Then by upper layer data
Packet provides all protocol layers on L2 layers.Various control signals can also be provided to L3 to be used for L3 processing.Controller/place
Reason device 459 is also responsible for carrying out error detection using confirmation (ACK) and/or negative confirmation (NACK) agreement to support HARQ operation.
In UL (Uplink, uplink), at UE450, upper layer data packet is provided to control using data source 467
Device/processor 459.Data source 467 indicates all protocol layers on L2 layers.Similar to the hair at the gNB410 described in DL
Send function, controller/processor 459 implements header compressed, encryption, packet segmentation and again based on the radio resource allocation of gNB410
The L2 layer function of plane is implemented for user plane and is controlled in multiplexing between sequence and logical AND transport channel.Control
Device/processor 459 processed is also responsible for HARQ operation, lost package re-emits, and to the signaling of gNB410.Channel coding/intertexture
Device 457 implements channel coding, and the data after coding prelist between the modulation and multi-antenna space by the implementation of transmited processor 468
The processing of code/beam shaping is modulated into multicarrier/single-carrier symbol stream, then provides via transmitter 454 and arrive different antennae 452.
The baseband symbol stream that transmited processor 468 provides is converted to radio frequency symbol stream first by each transmitter 454, then provides antenna
452。
The reception function at the UE450 being functionally similar to described in DL in UL (Uplink, uplink), at gNB410
Energy.Each receiver 418 receives radiofrequency signal by its respective antenna 420, and the radiofrequency signal received is converted to base band letter
Number, and baseband signal is provided to reception processor 470.It receives processor 470 and channel decoding/deinterleaver 478 is common real
Apply L1 layers of function.Controller/processor 475 implements L2 layer function.Controller/processor 475 can with storage program code and
The memory 476 of data is associated.Memory 476 can be described as computer-readable media.In UL, controller/processor 475 is mentioned
For between conveying and logic channel demultiplexing, package-restructuring dress, decryption, header decompression, control signal processing with restore come
From the upper layer data packet of UE450.Upper layer data packet from controller/processor 475 can provide core network.Controller/
Processor 475 is also responsible for carrying out error detection using ACK and/or NACK agreement to support HARQ operation.
As one embodiment, the UE450 includes: at least one processor and at least one processor, it is described extremely
A few memory includes computer program code；At least one processor and the computer program code are configured to
It is used together at least one described processor.
As one embodiment, the UE450 includes: a kind of memory for storing computer-readable instruction program, described
The generation when being executed by least one processor of computer-readable instruction program acts, and the movement includes: to execute in the application
It is described first operation, execute the application in the channel coding, send the application in first wireless signal.
As one embodiment, the UE450 includes: a kind of memory for storing computer-readable instruction program, described
The generation when being executed by least one processor of computer-readable instruction program acts, and the movement includes: to execute in the application
It is described second operation, execute the application in the channel decoding, receive the application in first wireless signal.
As one embodiment, the gNB410 includes: at least one processor and at least one processor, it is described extremely
A few memory includes computer program code；At least one processor and the computer program code are configured to
It is used together at least one described processor.
As one embodiment, the gNB410 includes: a kind of memory for storing computer-readable instruction program, described
The generation when being executed by least one processor of computer-readable instruction program acts, and the movement includes: to execute in the application
It is described second operation, execute the application in the channel decoding, receive the application in first wireless signal.
As one embodiment, the gNB410 includes: a kind of memory for storing computer-readable instruction program, described
The generation when being executed by least one processor of computer-readable instruction program acts, and the movement includes: to execute in the application
It is described first operation, execute the application in the channel coding, send the application in first wireless signal.
As one embodiment, the UE450 corresponds to the first node in the application, and the gNB410 corresponds to this Shen
Please in the second node.
As one embodiment, the UE450 corresponds to the second node in the application, and the gNB410 corresponds to this Shen
Please in the first node.
As one embodiment, at least one of { transmited processor 468, the channel coding/interleaver 457 }
It is used to carry out first operation；In { the reception processor 470, the channel decoding/deinterleaver 478 } at least it
One is used to carry out second operation.
As one embodiment, at least one of { transmited processor 468, the channel coding/interleaver 457 }
It is used to carry out the channel coding；In { the reception processor 470, the channel decoding/deinterleaver 478 } at least it
One is used to carry out the channel decoding.
As one embodiment, { antenna 452, the transmitter 454, the transmited processor 468, the channel
Coding/interleaver 457, the controller/processor 459 } at least one of be used to send first wireless signal；
{ antenna 420, the receiver 418, the reception processor 470, the channel decoding/deinterleaver 478, the control
Device/processor 475 processed } at least one of be used to receive first wireless signal.
As one embodiment, at least one of { transmited processor 416, the channel coding/interleaver 477 }
It is used to carry out first operation；In { described receive processor 456, the channel decoding/deinterleaver 458 } at least it
One is used to carry out second operation.
As one embodiment, at least one of { transmited processor 416, the channel coding/interleaver 477 }
It is used to carry out the channel coding；In { described receive processor 456, the channel decoding/deinterleaver 458 } at least it
One is used to carry out the channel decoding.
As one embodiment, { antenna 420, the transmitter 418, the transmited processor 416, the channel
Coding/interleaver 477, the controller/processor 475 } at least one of be used to send first wireless signal；
{ antenna 452, the receiver 454, the reception processor 456, the channel decoding/deinterleaver 458, the control
Device/processor 459 processed } at least one of be used to receive first wireless signal.
Embodiment 5
Embodiment 5 illustrates the flow chart of wireless transmission, as shown in Fig. 5.In attached drawing 5, base station N1 is the service of UE U2
Cell maintains base station.
For N1, channel coding is executed in step s 11；The first operation is executed in step s 12；It sends out in step s 13
Send the first wireless signal.
For U2, the first wireless signal is received in the step s 21；The second operation is executed in step S22；In step S23
Middle execution channel decoding.
In embodiment 5, the first bit sequence and the second bit sequence are outputting and inputting for first operation respectively,
First sequence of real numbers and the second sequence of real numbers are the output and input of second operation respectively.Second bit sequence is wrapped
The bit included is identical with bit included by first bit sequence, real number included by second sequence of real numbers and described
Real number included by first sequence of real numbers is identical.First bit sequence and first sequence of real numbers are a successively by Q1 respectively
The first kind bit subsequence of arrangement and the Q1 first kind real number subsequence compositions being arranged successively；What the Q1 was arranged successively
Preceding Q1-1 first kind bit subsequence in first kind bit subsequence is respectively by 1,3 ..., and it is resulting that 2 times of Q1 subtracts 3 again
The poor bit being arranged successively composition；The preceding Q1-1 first kind in the Q1 first kind real number subsequences being arranged successively is real
Number subsequence is respectively by 1,3 ..., and 2 times of Q1 subtracts the real number composition that 3 resulting differences are arranged successively again.Second bit
The second class bit subsequence that sequence and second sequence of real numbers are arranged successively by Q2 respectively and Q2 be arranged successively the
Two class real number subsequences composition；It include Q3 the second sub- sequences of class bit in the Q2 the second class bit subsequences being arranged successively
Column pair, the Q3 the second any second class bit subsequences of class bit subsequence centering are to including two length identical second
Class bit subsequence；It include Q3 the second class real number subsequences pair in the Q2 the second class real number subsequences being arranged successively,
The Q3 the second any second class real number subsequences of class real number subsequence centering are to real including identical second class of two length
Number subsequence.Be up to one in any second class bit subsequence in the Q2 the second class bit subsequences being arranged successively
A bit belongs to any one first kind bit subsequence in the first kind bit subsequence that the Q1 are arranged successively；It is described
A be up to real number belongs to institute in any second class real number subsequence in Q2 the second class real number subsequences being arranged successively
State any one first kind real number subsequence in the first kind real number subsequence that Q1 are arranged successively.The Q1 and Q2 points
It is not greater than 1 positive integer, the Q3 is less than the nonnegative integer of the Q2.First bit sequence is the channel coding
Output, first sequence of real numbers is the input of the channel decoding.Second bit sequence is by the N1 for generating
First wireless signal, first wireless signal is by the U2 for generating second sequence of real numbers.
As one embodiment, first bit sequence includes positive integer bit.
As one embodiment, second bit sequence includes positive integer bit.
As one embodiment, first sequence of real numbers includes positive integer real number.
As one embodiment, second sequence of real numbers includes positive integer real number.
Any first kind bit as one embodiment, in the Q1 first kind bit subsequences being arranged successively
Sequence includes positive integer bit.
Any second class bit as one embodiment, in the Q2 the second class bit subsequences being arranged successively
Sequence includes positive integer bit.
Any first kind real number as one embodiment, in the Q1 first kind real number subsequences being arranged successively
Sequence includes positive integer real number.
Any second class real number as one embodiment, in the Q2 the second class real number subsequences being arranged successively
Sequence includes positive integer real number.
As one embodiment, first operation is to interweave (interleaving).
As one embodiment, second operation is to deinterleave (de-interleaving).
As one embodiment, the number for the real number that first sequence of real numbers includes and first bit sequence include
The number of bit be bit one equal, that the real number and first bit sequence that first sequence of real numbers includes include
One is corresponding, and any real number is the Soft Inform ation of corresponding bit in first sequence of real numbers.
As one embodiment, the number for the real number that second sequence of real numbers includes and second bit sequence include
The number of bit be bit one equal, that the real number and second bit sequence that second sequence of real numbers includes include
One is corresponding, and any real number is the Soft Inform ation of corresponding bit in second sequence of real numbers.
Any first kind bit as one embodiment, in the Q1 first kind bit subsequences being arranged successively
Bit in sequence is arranged successively.
Any second class bit as one embodiment, in the Q2 the second class bit subsequences being arranged successively
Bit in sequence is arranged successively.
Any first kind real number as one embodiment, in the Q1 first kind real number subsequences being arranged successively
Real number in sequence is arranged successively.
Any second class real number as one embodiment, in the Q2 the second class real number subsequences being arranged successively
Real number in sequence is arranged successively.
As one embodiment, the channel coding includes rate-matched (rate matching).
As one embodiment, the channel coding is based on polarization (polar) coding.
As one embodiment, first wireless signal (is simply possible to use in carrier in down physical layer control channel
Manage layer signaling down channel) on transmit.
As a sub- embodiment of above-described embodiment, the down physical layer control channel is PDCCH.
As a sub- embodiment of above-described embodiment, the down physical layer control channel is sPDCCH.
As a sub- embodiment of above-described embodiment, the down physical layer control channel is NR-PDCCH.
As a sub- embodiment of above-described embodiment, the down physical layer control channel is NB-PDCCH.
As one embodiment, first wireless signal (can be used to carry physics in down physical layer data channel
The down channel of layer data) on transmit.
As a sub- embodiment of above-described embodiment, the down physical layer data channel is PDSCH.
As a sub- embodiment of above-described embodiment, the down physical layer data channel is sPDSCH.
As a sub- embodiment of above-described embodiment, the down physical layer data channel is NR-PDSCH.
As a sub- embodiment of above-described embodiment, the down physical layer data channel is NB-PDSCH.
As one embodiment, second sequence of real numbers is that first wireless signal successively passes through DFT, multiple antennas inspection
It surveys, is obtained after constellation demodulation.
As one embodiment, second sequence of real numbers is that first wireless signal successively passes through DFT, balanced, more
Antenna detection obtains after constellation demodulation.
As one embodiment, second sequence of real numbers is first wireless signal by { DFT, balanced, multiple antennas
Detection, constellation demodulation } one of or it is a variety of after obtain.
As one embodiment, the Q2 adds 1 sum equal with 2 product with the Q1, the Q2 subtract 1 difference with it is described
Q3 is equal with 2 product.
As one embodiment, the Q2 is equal to the Q1 and multiplied by 2 subtracts 1 again, the Q3 be equal to after the Q2 subtracts 1 again divided by
2。
As one embodiment, the Q2 adds 2 sum equal with 2 product with the Q1, the Q2 subtract 2 difference with it is described
Q3 is equal with 2 product.
As one embodiment, the Q2 is equal to the Q1 and multiplied by 2 subtracts 2 again, the Q3 be equal to after the Q2 subtracts 2 again divided by
2。
As one embodiment, first bit sequence includes Downlink Control Information.
As a sub- embodiment of above-described embodiment, the Downlink Control Information includes corresponding data { when occupied
At least one of domain resource, occupied frequency domain resource, MCS, RV, NDI, HARQ process number }.
Embodiment 6
Embodiment 6 illustrates the flow chart of wireless transmission, as shown in Fig. 6.In attached drawing 6, base station N3 is the service of UE U4
Cell maintains base station.
For N3, the first wireless signal is received in step S31；The second operation is executed in step s 32；In step S33
Middle execution channel decoding.
For U4, channel coding is executed in step S41；The first operation is executed in step S42；It is sent out in step S43
Send the first wireless signal.
In embodiment 6, the first bit sequence and the second bit sequence are outputting and inputting for first operation respectively,
First sequence of real numbers and the second sequence of real numbers are the output and input of second operation respectively.Second bit sequence is wrapped
The bit included is identical with bit included by first bit sequence, real number included by second sequence of real numbers and described
Real number included by first sequence of real numbers is identical.First bit sequence and first sequence of real numbers are a successively by Q1 respectively
The first kind bit subsequence of arrangement and the Q1 first kind real number subsequence compositions being arranged successively；What the Q1 was arranged successively
Preceding Q1-1 first kind bit subsequence in first kind bit subsequence is respectively by 1,3 ..., and it is resulting that 2 times of Q1 subtracts 3 again
The poor bit being arranged successively composition；The preceding Q1-1 first kind in the Q1 first kind real number subsequences being arranged successively is real
Number subsequence is respectively by 1,3 ..., and 2 times of Q1 subtracts the real number composition that 3 resulting differences are arranged successively again.Second bit
The second class bit subsequence that sequence and second sequence of real numbers are arranged successively by Q2 respectively and Q2 be arranged successively the
Two class real number subsequences composition；It include Q3 the second sub- sequences of class bit in the Q2 the second class bit subsequences being arranged successively
Column pair, the Q3 the second any second class bit subsequences of class bit subsequence centering are to including two length identical second
Class bit subsequence；It include Q3 the second class real number subsequences pair in the Q2 the second class real number subsequences being arranged successively,
The Q3 the second any second class real number subsequences of class real number subsequence centering are to real including identical second class of two length
Number subsequence.Be up to one in any second class bit subsequence in the Q2 the second class bit subsequences being arranged successively
A bit belongs to any one first kind bit subsequence in the first kind bit subsequence that the Q1 are arranged successively；It is described
A be up to real number belongs to institute in any second class real number subsequence in Q2 the second class real number subsequences being arranged successively
State any one first kind real number subsequence in the first kind real number subsequence that Q1 are arranged successively.The Q1 and Q2 points
It is not greater than 1 positive integer, the Q3 is less than the nonnegative integer of the Q2.First bit sequence is the channel coding
Output, first sequence of real numbers is the input of the channel decoding.Second bit sequence is by the U4 for generating
First wireless signal, first wireless signal is by the N3 for generating second sequence of real numbers.
As one embodiment, first wireless signal (is simply possible to use in carrier in upstream physical layer control channel
Manage layer signaling up channel) on transmit.
As a sub- embodiment of above-described embodiment, the upstream physical layer control channel is PUCCH.
As a sub- embodiment of above-described embodiment, the upstream physical layer control channel is sPUCCH.
As a sub- embodiment of above-described embodiment, the upstream physical layer control channel is NR-PUCCH.
As a sub- embodiment of above-described embodiment, the upstream physical layer control channel is NB-PUCCH.
As one embodiment, first wireless signal (can be used to carry physics in upstream physical layer data channel
The up channel of layer data) on transmit.
As a sub- embodiment of above-described embodiment, the upstream physical layer data channel is PUSCH.
As a sub- embodiment of above-described embodiment, the upstream physical layer data channel is sPUSCH.
As a sub- embodiment of above-described embodiment, the upstream physical layer data channel is NR-PUSCH.
As a sub- embodiment of above-described embodiment, the upstream physical layer data channel is NB-PUSCH.
As one embodiment, first bit sequence includes ascending control information.
As a sub- embodiment of above-described embodiment, the ascending control information include HARQ-ACK, CSI, SR,
At least one of CRI }.
Embodiment 7
Embodiment 7 illustrates the schematic diagram of relationship between the first bit sequence and the second bit sequence, as shown in Fig. 7.
In embodiment 7, first bit sequence and second bit sequence are described in the application respectively
One operation is output and input, bit included by bit included by second bit sequence and first bit sequence
It is identical；First bit sequence is made of the first kind bit subsequence that Q1 is arranged successively, and the Q1 are arranged successively
First kind bit subsequence is respectively by 1,3 ..., and 2 times of Q1 subtracts the bit composition that 1 resulting difference is arranged successively again；It is described
The second class bit subsequence that second bit sequence is arranged successively by Q2 forms, the Q2 the second class bits being arranged successively
It include Q3 the second class bit subsequences pair, the Q3 the second any second class bits of class bit subsequence centering in subsequence
Subsequence is to including the identical second class bit subsequence of two length；The Q2 the second class bit subsequences being arranged successively
In any second class bit subsequence in a be up to bit belong to the sub- sequences of first kind bit that the Q1 is arranged successively
Any one first kind bit subsequence in column；The Q1 is greater than 2 positive integer, and the Q2 adds 1 sum and the Q1 and 2
Product it is equal, the Q2 subtract 1 difference it is equal with 2 product with the Q3.The Q3 the second class bit subsequence centerings are appointed
The second class bit that two the second class bit subsequences of one second class bit subsequence centering are arranged successively at the Q2
Position in sequence is discontinuous.
In fig. 7, first bit sequence is arranged successively by 25 bits and is formed, in first bit sequence
Bit is by { x1, x2..., x25Indicate.The index for the first kind bit subsequences that the Q1 is arranged successively be respectively # 1,
2 ..., Q1-1, Q1 }；The index for the second class bit subsequences that the Q2 is arranged successively be respectively # 1,2 ..., Q2-1,
Q2}；The index of the Q3 the second class bit subsequences pair is # { 1,2 ..., Q3 } respectively.In the ellipse of each solid border
Bit sequence be a first kind bit subsequence in first kind bit subsequence that the Q1 is arranged successively, solid line side
The serial number of frame is the index of the Q1 first kind bit subsequences being arranged successively.Bit in the ellipse of each dotted border
Sequence is a second class bit subsequence in the Q2 the second class bit subsequences being arranged successively, the sequence of dotted border
It number is the index of the Q2 the second class bit subsequences being arranged successively.Times of the Q3 the second class bit subsequence centerings
One second class bit subsequence is connected between the identical second class bit subsequence of two length for including by solid-line curve, boundless
The serial number of frame is the index of the Q3 the second class bit subsequences pair.
Any first kind bit as one embodiment, in the Q1 first kind bit subsequences being arranged successively
Bit in sequence is arranged successively.
Any second class bit as one embodiment, in the Q2 the second class bit subsequences being arranged successively
Bit in sequence is arranged successively.
As one embodiment, there is no a bits to belong to the Q1 sub- sequences of first kind bit being arranged successively simultaneously
Any two first kind bit subsequence in column.
As one embodiment, there is no a bits to belong to the Q2 the second sub- sequences of class bit being arranged successively simultaneously
Any two the second class bit subsequence in column.
As one embodiment, for given second class bit of the Q3 the second class bit subsequence centerings
Sequence pair, there are Q5 among two the second class bit subsequences of the given second class bit subsequence centering to be arranged successively
The second class bit subsequence, the Q5 is positive integer.
As a sub- embodiment of above-described embodiment, the Q5 and described two second class bit subsequences are in the Q2
Position in a the second class bit subsequence being arranged successively is related,
As a sub- embodiment of above-described embodiment, the Q5 is less than the odd number of the Q3.
As a sub- embodiment of above-described embodiment, the second class bit that First ray is arranged successively at the Q2 is sub
Position in sequence is more forward, and the Q5 is bigger；The First ray is to come institute in described two second class bit subsequences
State earlier above the second class bit subsequence in the second class bit subsequence that Q2 are arranged successively.
As one embodiment, the given second sub- sequence of class bit any for the Q3 the second class bit subsequence centerings
Column pair, two the second class bit subsequences of the given second class bit subsequence centering be arranged successively at the Q2 the
Index in two class bit subsequences is a1 and a2 respectively, and the a1 and the a2 are no more than the positive integer of the Q2 respectively,
The a1 is less than the a2, and the a2 subtracts the a1 equal to the Q2 and adds 1 again.
Embodiment 8
Embodiment 8 illustrates the schematic diagram of relationship between the first bit sequence and the second bit sequence, as shown in Fig. 8.
In embodiment 8, first bit sequence and second bit sequence are described in the application respectively
One operation is output and input, bit included by bit included by second bit sequence and first bit sequence
It is identical；First bit sequence is made of the first kind bit subsequence that Q1 is arranged successively, and the Q1 are arranged successively
First kind bit subsequence is respectively by 1,3 ..., and 2 times of Q1 subtracts the bit composition that 1 resulting difference is arranged successively again；It is described
The second class bit subsequence that second bit sequence is arranged successively by Q2 forms, the Q2 the second class bits being arranged successively
It include Q3 the second class bit subsequences pair, the Q3 the second any second class bits of class bit subsequence centering in subsequence
Subsequence is to including the identical second class bit subsequence of two length；The Q2 the second class bit subsequences being arranged successively
In any second class bit subsequence in a be up to bit belong to the sub- sequences of first kind bit that the Q1 is arranged successively
Any one first kind bit subsequence in column；The Q1 is greater than 2 positive integer, and the Q2 adds 1 sum and the Q1 and 2
Product it is equal, the Q2 subtract 1 difference it is equal with 2 product with the Q3.A second class bit subsequence centering of the Q3
Two the second class bit subsequences of any second class bit subsequence centering are continuous in second bit sequence.
In attached drawing 8, first bit sequence is arranged successively by 25 bits and is formed, in first bit sequence
Bit is by { x1, x2..., x25Indicate.The index for the first kind bit subsequences that the Q1 is arranged successively be respectively # 1,
2 ..., Q1-1, Q1 }；The index for the second class bit subsequences that the Q2 is arranged successively be respectively # 1,2 ..., Q2-1,
Q2}；The index of the Q3 the second class bit subsequences pair is # { 1,2 ..., Q3 } respectively.In the ellipse of each solid border
Bit sequence be a first kind bit subsequence in first kind bit subsequence that the Q1 is arranged successively, solid line side
The serial number of frame is the index of the Q1 first kind bit subsequences being arranged successively.Bit in the ellipse of each dotted border
Sequence is a second class bit subsequence in the Q2 the second class bit subsequences being arranged successively, the sequence of dotted border
It number is the index of the Q2 the second class bit subsequences being arranged successively.Times of the Q3 the second class bit subsequence centerings
One second class bit subsequence is connected between the identical second class bit subsequence of two length for including by solid-line curve, boundless
The serial number of frame is the index of the Q3 the second class bit subsequences pair.
As one embodiment, the first subsequence and the second subsequence are the Q2 the second class bit being arranged successively
Any two the second class bit subsequence in sequence, the second class bit that first subsequence is arranged successively at the Q2
Position in subsequence is before second subsequence, and the bit number that second subsequence includes is not less than first son
The bit number that sequence includes.
As one embodiment, the Q3 the second class bit subsequence centering first in second bit sequence
The quantity of bit included by second class bit subsequence of a appearance is 1.
Embodiment 9
Embodiment 9 illustrates the schematic diagram of relationship between the first bit sequence and the second bit sequence, as shown in Fig. 9.
In embodiment 9, first bit sequence and second bit sequence are described in the application respectively
One operation is output and input, bit included by bit included by second bit sequence and first bit sequence
It is identical；First bit sequence is made of the first kind bit subsequence that Q1 is arranged successively, and the Q1 are arranged successively
First kind bit subsequence is respectively by 1,3 ..., and 2 times of Q1 subtracts the bit composition that 1 resulting difference is arranged successively again；It is described
The second class bit subsequence that second bit sequence is arranged successively by Q2 forms, the Q2 the second class bits being arranged successively
It include Q3 the second class bit subsequences pair, the Q3 the second any second class bits of class bit subsequence centering in subsequence
Subsequence is to including the identical second class bit subsequence of two length；The Q2 the second class bit subsequences being arranged successively
In any second class bit subsequence in a be up to bit belong to the sub- sequences of first kind bit that the Q1 is arranged successively
Any one first kind bit subsequence in column；The Q1 is greater than 2 positive integer, and the Q2 adds 1 sum and the Q1 and 2
Product it is equal, the Q2 subtract 1 difference it is equal with 2 product with the Q3.A second class bit subsequence centering of the Q3
Two the second class bit subsequences of any second class bit subsequence centering are continuous in second bit sequence.
In attached drawing 9, first bit sequence is arranged successively by 25 bits and is formed, in first bit sequence
Bit is by { x1, x2..., x25Indicate.The index for the first kind bit subsequences that the Q1 is arranged successively be respectively # 1,
2 ..., Q1-1, Q1 }；The index for the second class bit subsequences that the Q2 is arranged successively be respectively # 1,2 ..., Q2-1,
Q2}；The index of the Q3 the second class bit subsequences pair is # { 1,2 ..., Q3 } respectively.In the ellipse of each solid border
Bit sequence be a first kind bit subsequence in first kind bit subsequence that the Q1 is arranged successively, solid line side
The serial number of frame is the index of the Q1 first kind bit subsequences being arranged successively.Bit in the ellipse of each dotted border
Sequence is a second class bit subsequence in the Q2 the second class bit subsequences being arranged successively, the sequence of dotted border
It number is the index of the Q2 the second class bit subsequences being arranged successively.Times of the Q3 the second class bit subsequence centerings
One second class bit subsequence is connected between the identical second class bit subsequence of two length for including by solid-line curve, boundless
The serial number of frame is the index of the Q3 the second class bit subsequences pair.
As one embodiment, the first subsequence and the second subsequence are the Q2 the second class bit being arranged successively
Any two the second class bit subsequence in sequence, the second class bit that first subsequence is arranged successively at the Q2
Position in subsequence is before second subsequence, and the bit number that second subsequence includes is no more than first son
The bit number that sequence includes.
As one embodiment, the Q3 the second class bit subsequence centering first in second bit sequence
The quantity of bit included by second class bit subsequence of a appearance is the Q3.
Embodiment 10
Embodiment 10 illustrates the schematic diagram of relationship between the first bit sequence and the second bit sequence, such as 10 institute of attached drawing
Show.
In embodiment 10, first bit sequence and second bit sequence are described in the application respectively
One operation is output and input, bit included by bit included by second bit sequence and first bit sequence
It is identical；First bit sequence is made of the first kind bit subsequence that Q1 is arranged successively, and the Q1 are arranged successively
First kind bit subsequence is respectively by 1,3 ..., and 2 times of Q1 subtracts the bit composition that 1 resulting difference is arranged successively again；It is described
The second class bit subsequence that second bit sequence is arranged successively by Q2 forms, the Q2 the second class bits being arranged successively
It include Q3 the second class bit subsequences pair, the Q3 the second any second class bits of class bit subsequence centering in subsequence
Subsequence is to including the identical second class bit subsequence of two length；The Q2 the second class bit subsequences being arranged successively
In any second class bit subsequence in a be up to bit belong to the sub- sequences of first kind bit that the Q1 is arranged successively
Any one first kind bit subsequence in column；The Q1 is greater than 1 positive integer, and the Q2 adds 1 sum and the Q1 and 2
Product it is equal, the Q2 subtract 1 difference it is equal with 2 product with the Q3.The Q3 the second class bit subsequence centerings are appointed
The second class bit that two the second class bit subsequences of one second class bit subsequence centering are arranged successively at the Q2
Position in sequence is continuous.
In fig. 10, first bit sequence is arranged successively by 25 bits and is formed, in first bit sequence
Bit by { x1, x2..., x25Indicate.The index for the first kind bit subsequences that the Q1 is arranged successively be respectively # 1,
2 ..., Q1-1, Q1 }；The index for the second class bit subsequences that the Q2 is arranged successively be respectively # 1,2 ..., Q2-1,
Q2}；The index of the Q3 the second class bit subsequences pair is # { 1,2 ..., Q3 } respectively.In the ellipse of each solid border
Bit sequence be a first kind bit subsequence in first kind bit subsequence that the Q1 is arranged successively, solid line side
The serial number of frame is the index of the Q1 first kind bit subsequences being arranged successively.Bit in the ellipse of each dotted border
Sequence is a second class bit subsequence in the Q2 the second class bit subsequences being arranged successively, the sequence of dotted border
It number is the index of the Q2 the second class bit subsequences being arranged successively.Times of the Q3 the second class bit subsequence centerings
One second class bit subsequence is connected between the identical second class bit subsequence of two length for including by solid-line curve, boundless
The serial number of frame is the index of the Q3 the second class bit subsequences pair.
As one embodiment, the first subsequence and the second subsequence are the Q2 the second class bit being arranged successively
Any two the second class bit subsequence in sequence, the second class bit that first subsequence is arranged successively at the Q2
Position in subsequence is before second subsequence, and the bit number that second subsequence includes is not less than first son
The bit number that sequence includes.
As one embodiment, the Q3 the second class bit subsequence centering first in second bit sequence
The quantity of bit included by second class bit subsequence of a appearance is 1.
Embodiment 11
Embodiment 11 illustrates the schematic diagram of relationship between the first bit sequence and the second bit sequence, such as 11 institute of attached drawing
Show.
In embodiment 11, first bit sequence and second bit sequence are described in the application respectively
One operation is output and input, bit included by bit included by second bit sequence and first bit sequence
It is identical；First bit sequence is made of the first kind bit subsequence that Q1 is arranged successively, and the Q1 are arranged successively
Preceding Q1-1 first kind bit subsequence in first kind bit subsequence is respectively by 1,3 ..., and it is resulting that 2 times of Q1 subtracts 3 again
The poor bit being arranged successively forms, the last one first kind ratio in the Q1 first kind bit subsequences being arranged successively
The bit that special subsequence is arranged successively by P forms, the positive integer for resulting difference that the Q1 that the P is less than 2 times subtracts 1；Described
The second class bit subsequence that two bit sequences are arranged successively by Q2 forms, the Q2 the second class bit being arranged successively
It include Q3 the second class bit subsequences pair, any second class bit of the Q3 the second class bit subsequence centerings in sequence
Sequence is to including the identical second class bit subsequence of two length；In the Q2 the second class bit subsequences being arranged successively
Any second class bit subsequence in a be up to bit belong to the first kind bit subsequences that the Q1 is arranged successively
In any one first kind bit subsequence；The Q1 is greater than 1 positive integer, and the Q2 adds 2 sum with the Q1's and 2
Product is equal, and the difference that the Q2 subtracts 2 is equal with 2 product with the Q3.Times of the Q3 the second class bit subsequence centerings
Two the second class bit subsequences of one second class bit subsequence centering are discontinuous in second bit sequence.
In attached drawing 11, first bit sequence is arranged successively by 22 bits and is formed, in first bit sequence
Bit by { x1, x2..., x22Indicate.The index for the first kind bit subsequences that the Q1 is arranged successively be respectively # 1,
2 ..., Q1-1, Q1 }；The index for the second class bit subsequences that the Q2 is arranged successively be respectively # 1,2 ..., Q2-1,
Q2}；The index of the Q3 the second class bit subsequences pair is # { 1,2 ..., Q3 } respectively.In the ellipse of each solid border
Bit sequence be a first kind bit subsequence in first kind bit subsequence that the Q1 is arranged successively, solid line side
The serial number of frame is the index of the Q1 first kind bit subsequences being arranged successively.Bit in the ellipse of each dotted border
Sequence is a second class bit subsequence in the Q2 the second class bit subsequences being arranged successively, the sequence of dotted border
It number is the index of the Q2 the second class bit subsequences being arranged successively.Times of the Q3 the second class bit subsequence centerings
One second class bit subsequence is connected between the identical second class bit subsequence of two length for including by solid-line curve, boundless
The serial number of frame is the index of the Q3 the second class bit subsequences pair.
Embodiment 12
Embodiment 12 illustrates the schematic diagram for generating the first wireless signal, as shown in Fig. 12.
In embodiment 12, third bit sequence is the input of the channel coding in the application, the first bit sequence
It is the output of the channel coding, first bit sequence and the second bit sequence are first behaviour in the application respectively
That makees outputs and inputs, and first wireless signal is that second bit sequence successively passes through modulation mapper, layer mapper,
Conversion precoder, precoding, resource particle mapper, the output after multicarrier symbol generation；Wherein, conversion precoder
It is optional.
As one embodiment, first operation is to interweave (interleaving).
As one embodiment, the channel coding includes rate-matched (rate matching).
As one embodiment, the channel coding is based on polarization (polar) coding.
As one embodiment, the channel coding is encoded based on Turbo.
As one embodiment, the channel coding is encoded based on LDPC.
As one embodiment, the channel coding is based on convolutional encoding.
As one embodiment, the third bit sequence includes the bit that positive integer is arranged successively.
As one embodiment, the bit in the third bit sequence is sequentially input the corresponding channel of the channel coding
In encoder.
As one embodiment, the multicarrier symbol is OFDM symbol.
As one embodiment, the multicarrier symbol is DFT-S-OFDM symbol.
As one embodiment, the multicarrier symbol is FBMC symbol.
Embodiment 13
Embodiment 13 illustrates the structural block diagram for the processing unit in first node, as shown in Fig. 13.In attached drawing
In 13, the processing unit 1300 in first node is mainly made of first processing module 1301 and the first sender module 1302.
In embodiment 13, first processing module 1301 executes the first operation；First sender module 1302 sends first
Wireless signal.
In embodiment 13, the first bit sequence and the second bit sequence are the input of first operation respectively and defeated
Out, bit included by second bit sequence is identical with bit included by first bit sequence；First ratio
The first kind bit subsequence that special sequence is arranged successively by Q1 forms, the Q1 first kind bit subsequences being arranged successively
In preceding Q1-1 first kind bit subsequence respectively by 1,3 ..., 2 times of Q1 subtracts the ratios that 3 resulting differences are arranged successively again
Spy's composition；The second class bit subsequence that second bit sequence is arranged successively by Q2 forms, and the Q2 are arranged successively
The second class bit subsequence in include Q3 the second class bit subsequences pair, the Q3 the second class bit subsequence centerings are appointed
One second class bit subsequence is to including the identical second class bit subsequence of two length；A second be arranged successively of the Q2
Be up to that a bit belongs to that the Q1 is arranged successively in any second class bit subsequence in class bit subsequence the
Any one first kind bit subsequence in a kind of bit subsequence；The Q1 and Q2 is greater than 1 positive integer respectively,
The Q3 is less than the nonnegative integer of the Q2.Second bit sequence is by first sender module 1302 for generating
First wireless signal.
As one embodiment, the first processing module 1301 also executes channel coding；Wherein, the first bit sequence
Column are the output of the channel coding.
As one embodiment, the Q2 adds 1 sum equal with 2 product with the Q1.
As one embodiment, the Q2 adds 2 sum equal with 2 product with the Q1.
As one embodiment, the first node is base station.
As one sub- embodiment of above-described embodiment, the first processing module 1301 includes in embodiment 4 { at transmitting
At least one of manage device 416, channel coding/interleaver 477, controller/processor 475, memory 476 }.
As one sub- embodiment of above-described embodiment, first sender module 1302 includes the { antenna in embodiment 4
420, transmitter 418, transmited processor 416, channel coding/interleaver 477, controller/processor 475, memory 476 } in
At least one of.
As one embodiment, the first node user equipment.
As one sub- embodiment of above-described embodiment, the first processing module 1301 includes in embodiment 4 { at transmitting
At least one of manage device 468, channel coding/interleaver 457, controller/processor 459, memory 460, data source 467 }.
As one sub- embodiment of above-described embodiment, first sender module 1302 includes the { antenna in embodiment 4
452, transmitter 454, transmited processor 468, channel coding/interleaver 457, controller/processor 459, memory 460, number
At least one of according to source 467 }.
Embodiment 14
Embodiment 14 illustrates the structural block diagram for the processing unit in second node, as shown in Fig. 14.In attached drawing
In 14, the processing unit 1400 in second node is mainly made of Second processing module 1401 and the first receiver module 1402.
In embodiment 14, Second processing module 1401 executes the second operation；First receiver module 1402 receives first
Wireless signal.
In embodiment 14, the first sequence of real numbers and the second sequence of real numbers are the output of second operation respectively and defeated
Enter, real number included by second sequence of real numbers is identical with real number included by first sequence of real numbers；Described first is real
The first kind real number subsequence that Number Sequence is arranged successively by Q1 forms, the Q1 first kind real number subsequences being arranged successively
In preceding Q1-1 first kind real number subsequence respectively by 1,3 ..., 2 times of Q1 subtracts the realities that 3 resulting differences are arranged successively again
Array at；The second class real number subsequence that second sequence of real numbers is arranged successively by Q2 forms, and the Q2 are arranged successively
The second class real number subsequence in include Q3 the second class real number subsequences pair, the Q3 the second class real number subsequence centerings are appointed
One second class real number subsequence is to including the identical second class real number subsequence of two length；A second be arranged successively of the Q2
Be up to that a real number belongs to that the Q1 is arranged successively in any second class real number subsequence in class real number subsequence the
Any one first kind real number subsequence in a kind of real number subsequence；The Q1 and Q2 is greater than 1 positive integer respectively,
The Q3 is less than the nonnegative integer of the Q2.First wireless signal is by the Second processing module 1401 for generating institute
State the second sequence of real numbers.
As one embodiment, the Second processing module 1401 also executes channel decoding；Wherein, the first real number sequence
Column are the inputs of the channel decoding.
As one embodiment, the Q2 adds 1 sum equal with 2 product with the Q1.
As one embodiment, the Q2 adds 2 sum equal with 2 product with the Q1.
As one embodiment, for the Q3 the second class real number subsequence centerings in second sequence of real numbers
The quantity of bit included by second class real number subsequence of first appearance is 1.
As one embodiment, for the Q3 the second class real number subsequence centerings in second sequence of real numbers
The quantity of bit included by second class real number subsequence of first appearance is Q3.
As one embodiment, the second node is user equipment.
As a sub- embodiment of above-described embodiment, the Second processing module 1401 includes { receiving in embodiment 4
Processor 456, channel decoding/deinterleaver 458, controller/processor 459, memory 460, data source 467 } at least
One of.
As a sub- embodiment of above-described embodiment, first receiver module 1402 includes the { day in embodiment 4
Line 452, receiver 454, reception processor 456, channel decoding deinterleaver 458, controller/processor 459, memory 460,
At least one of data source 467 }.
As one embodiment, the second node is user base station.
As a sub- embodiment of above-described embodiment, the Second processing module 1401 includes { receiving in embodiment 4
At least one of processor 470, channel decoding deinterleaver 478, controller/processor 475, memory 476 }.
As a sub- embodiment of above-described embodiment, first receiver module 1402 includes the { day in embodiment 4
Line 420, receiver 418 receive processor 470, channel decoding deinterleaver 478, controller/processor 475, memory 476 }
At least one of.
Embodiment 15
Embodiment 15 illustrates the schematic diagram of relationship between the first bit sequence and the second bit sequence, such as 15 institute of attached drawing
Show.
In embodiment 15, first bit sequence and second bit sequence are described in the application respectively
One operation is output and input, bit included by bit included by second bit sequence and first bit sequence
It is identical；First bit sequence is made of the first kind bit subsequence that Q1 is arranged successively, and the Q1 are arranged successively
Preceding Q1-1 first kind bit subsequence in first kind bit subsequence is respectively by 1,3 ..., and it is resulting that 2 times of Q1 subtracts 3 again
The poor bit being arranged successively forms, the last one first kind ratio in the Q1 first kind bit subsequences being arranged successively
The bit that special subsequence is arranged successively by P forms, the positive integer for resulting difference that the Q1 that the P is less than 2 times subtracts 1；Described
The second class bit subsequence that two bit sequences are arranged successively by Q2 forms, the Q2 the second class bit being arranged successively
It include Q3 the second class bit subsequences pair, any second class bit of the Q3 the second class bit subsequence centerings in sequence
Sequence is to including the identical second class bit subsequence of two length；In the Q2 the second class bit subsequences being arranged successively
Any second class bit subsequence in a be up to bit belong to the first kind bit subsequences that the Q1 is arranged successively
In any one first kind bit subsequence；The Q1 is greater than 1 positive integer, and the Q2 adds 2 sum with the Q1's and 2
Product is equal, and the difference that the Q2 subtracts 2 is equal with 2 product with the Q3.Times of the Q3 the second class bit subsequence centerings
Two the second class bit subsequences of one second class bit subsequence centering are discontinuous in second bit sequence.
In attached drawing 15, first bit sequence is arranged successively by 22 bits and is formed, in first bit sequence
Bit by { x1, x2..., x22Indicate.The index for the first kind bit subsequences that the Q1 is arranged successively be respectively # 1,
2 ..., Q1-1, Q1 }；The index for the second class bit subsequences that the Q2 is arranged successively be respectively # 1,2 ..., Q2-1,
Q2}；The index of the Q3 the second class bit subsequences pair is # { 1,2 ..., Q3 } respectively.In the ellipse of each solid border
Bit sequence be a first kind bit subsequence in first kind bit subsequence that the Q1 is arranged successively, solid line side
The serial number of frame is the index of the Q1 first kind bit subsequences being arranged successively.Bit in the ellipse of each dotted border
Sequence is a second class bit subsequence in the Q2 the second class bit subsequences being arranged successively, the sequence of dotted border
It number is the index of the Q2 the second class bit subsequences being arranged successively.Times of the Q3 the second class bit subsequence centerings
One second class bit subsequence is connected between the identical second class bit subsequence of two length for including by solid-line curve, boundless
The serial number of frame is the index of the Q3 the second class bit subsequences pair.
As one embodiment, for any second class bit subsequence of the Q3 the second class bit subsequence centerings
It is right, there are the second class bit sequence that Q5 is arranged successively among two the second class bit subsequences therein, the Q5 for
All second class bit subsequences of the Q3 the second class bit subsequence centering to be it is identical, the Q5 is positive integer.
Embodiment 16
Embodiment 16 illustrates the schematic diagram of relationship between the first bit sequence and the second bit sequence, such as 16 institute of attached drawing
Show.
In embodiment 16, first bit sequence and second bit sequence are described in the application respectively
One operation is output and input, bit included by bit included by second bit sequence and first bit sequence
It is identical；First bit sequence is made of the first kind bit subsequence that Q1 is arranged successively, and the Q1 are arranged successively
Preceding Q1-1 first kind bit subsequence in first kind bit subsequence is respectively by 1,3 ..., and it is resulting that 2 times of Q1 subtracts 3 again
The poor bit being arranged successively forms, the last one first kind ratio in the Q1 first kind bit subsequences being arranged successively
The bit that special subsequence is arranged successively by P forms, the positive integer for resulting difference that the Q1 that the P is less than 2 times subtracts 1；Described
The second class bit subsequence that two bit sequences are arranged successively by Q2 forms, the Q2 the second class bit being arranged successively
It include Q3 the second class bit subsequences pair, any second class bit of the Q3 the second class bit subsequence centerings in sequence
Sequence is to including the identical second class bit subsequence of two length；In the Q2 the second class bit subsequences being arranged successively
Any second class bit subsequence in a be up to bit belong to the first kind bit subsequences that the Q1 is arranged successively
In any one first kind bit subsequence；The Q1 is greater than 1 positive integer, and the Q2 adds 2 sum with the Q1's and 2
Product is equal, and the difference that the Q2 subtracts 2 is equal with 2 product with the Q3.Times of the Q3 the second class bit subsequence centerings
Two the second class bit subsequences of one second class bit subsequence centering are continuous in second bit sequence.
In figure 16, first bit sequence is arranged successively by 22 bits and is formed, in first bit sequence
Bit by { x1, x2..., x22Indicate.The index for the first kind bit subsequences that the Q1 is arranged successively be respectively # 1,
2 ..., Q1-1, Q1 }；The index for the second class bit subsequences that the Q2 is arranged successively be respectively # 1,2 ..., Q2-1,
Q2}；The index of the Q3 the second class bit subsequences pair is # { 1,2 ..., Q3 } respectively.In the ellipse of each solid border
Bit sequence be a first kind bit subsequence in first kind bit subsequence that the Q1 is arranged successively, solid line side
The serial number of frame is the index of the Q1 first kind bit subsequences being arranged successively.Bit in the ellipse of each dotted border
Sequence is a second class bit subsequence in the Q2 the second class bit subsequences being arranged successively, the sequence of dotted border
It number is the index of the Q2 the second class bit subsequences being arranged successively.Times of the Q3 the second class bit subsequence centerings
One second class bit subsequence is connected between the identical second class bit subsequence of two length for including by solid-line curve, boundless
The serial number of frame is the index of the Q3 the second class bit subsequences pair.
As one embodiment, the first subsequence and the second subsequence are the Q2 the second class bit being arranged successively
Any two the second class bit subsequence in sequence, the second class bit that first subsequence is arranged successively at the Q2
Position in subsequence is before second subsequence, and the bit number that second subsequence includes is no more than first son
The bit number that sequence includes.
As one embodiment, the Q3 the second class bit subsequence centering first in second bit sequence
The quantity of bit included by second class bit subsequence of a appearance is the Q3.
Embodiment 17
Embodiment 17 illustrates the schematic diagram of relationship between the first bit sequence and the second bit sequence, such as 17 institute of attached drawing
Show.
In embodiment 17, first bit sequence and second bit sequence are described in the application respectively
One operation is output and input, bit included by bit included by second bit sequence and first bit sequence
It is identical；First bit sequence is made of the first kind bit subsequence that Q1 is arranged successively, and the Q1 are arranged successively
Preceding Q1-1 first kind bit subsequence in first kind bit subsequence is respectively by 1,3 ..., and it is resulting that 2 times of Q1 subtracts 3 again
The poor bit being arranged successively forms, the last one first kind ratio in the Q1 first kind bit subsequences being arranged successively
The bit that special subsequence is arranged successively by P forms；The second class bit that second bit sequence is arranged successively by Q2
Sequence forms, and includes Q3 the second class bit subsequences pair in the Q2 the second class bit subsequences being arranged successively, described
Q3 the second any second class bit subsequences of class bit subsequence centering are to including identical second class bit of two length
Sequence；Be up to one ratio in any second class bit subsequence in the Q2 the second class bit subsequences being arranged successively
Spy belongs to any one first kind bit subsequence in the first kind bit subsequence that the Q1 are arranged successively；The Q1 is
Positive integer greater than 1, the positive integer for resulting difference that the Q1 that the P is no more than 2 times subtracts 1.
In figure 17, the first bit sequence correspondence={ x1,x2,x3,x4,…,x(Q1-1)^2+P, wherein z^2 indicates z
Square；The Q1 first kind bit subsequences being arranged successively are successively are as follows:
First kind bit subsequence #1:{ x1 }；
First kind bit subsequence #2:{ x2,x3,x4}；
…；
First kind bit subsequence #Q1-1:{ x(Q1-2)^2+1,x(Q1-2)^2+2,…,x(Q1-1)^2}；
First kind bit subsequence #Q1:{ x(Q1-1)^2+1,x(Q1-1)^2+2,…,x(Q1-1)^2+P}
As one embodiment, the P is equal to 2 times of the Q1 resulting difference that subtracts 1,2 times of the Q1 subtracts 1 resulting difference and institute
It is equal to state Q2, the Q1 subtracts 1, and resulting difference is equal with the Q3.
As a sub- embodiment of above-described embodiment, second class of the Q3 the second class bit subsequence centerings
The quantity of bit included by bit subsequence is 1,2,3 respectively ..., 1) Q3 (i.e. since 1, is successively increased.
As a sub- embodiment of above-described embodiment, the Q3 the second class bit subsequences are to being:
Second class bit subsequence is to #1:{ x(Q1-1)^2+1, { x(Q1-1)^2+P}；
Second class bit subsequence is to #2:{ x(Q1-1)^2+2,x(Q1-2)^2+1, { x(Q1-1)^2+P-1,x(Q1-1)^2}；
…；
Second class bit subsequence is to #Q3:{ x(Q1-1)^2+(P-1)/2,xQ1^2-3Q1+2,…,x2},{x(Q1-1)^2+(P-1)/2+2,
xQ1^2-3Q1+4,…,x4}；
As one embodiment, the P is less than or equal to Q1, and 2 times of the Q1 subtracts 2, and resulting difference is equal with the Q2,
The Q1 subtracts 2, and resulting difference is equal with the Q3.
As a sub- embodiment of above-described embodiment, second class of the Q3 the second class bit subsequence centerings
The quantity of bit included by bit subsequence is 1,2,3 respectively ..., 1) Q3 (i.e. since 1, is successively increased.
As a sub- embodiment of above-described embodiment, the Q3 the second class bit subsequences are to being:
Second class bit subsequence is to #1:{ x(Q1-1)^2+1, { x(Q1-1)^2}；
Second class bit subsequence is to #2:{ x(Q1-1)^2+2,x(Q1-2)^2+1, { x(Q1-1)^2-1,x(Q1-2)^2(P is greater than
1)；Alternatively, { x(Q1-2)^2+2,x(Q1-3)^2+1, { x(Q1-1)^2-1,x(Q1-2)^2(P is equal to 1)；
…；
Second class bit subsequence is to #Q3:{ x(Q1-1)^2+Q1-1,xQ1^2-3Q1+2,…,x2},{x(Q1-2)^2+Q1-1,
x(Q1-2)^2-Q1+3,…,x1(P be equal to the Q1 subtract 1 resulting difference)；Alternatively, { x(Q1-1)^2+Q1-2,xQ1^2-3Q1+1,…,x5},
{x(Q1-2)^2+Q1,x(Q1-3)^2+Q1-1,…,x4(P is equal to the Q1)；Alternatively, { x(Q1-2)^2+Q1-2,x(Q1-3)^2+Q1-3,…,
x2},{x(Q1-2)^2+Q1,x(Q1-3)^2+Q1-1,…,x4(P be less than the Q1 subtract 1 resulting difference).
As one embodiment, the P is greater than Q1 and the Q1 less than 2 times resulting difference that subtracts 1,2 times of the Q1 subtracts 2 gained
Difference it is equal with the Q2, the Q1 subtracts 2, and resulting difference is equal with the Q3.
As a sub- embodiment of above-described embodiment, second class of the Q3 the second class bit subsequence centerings
The quantity of bit included by bit subsequence is Q3 two positive integer neither waited respectively, and the Q3 a two neither waits just whole
Array is made of at the first integer set, first integer set all positive integers except the removing Q8 from 1 to Q3, and 2 times
The Q1 subtract 1 and subtract the resulting difference of P again it is equal with the Q8.
Those of ordinary skill in the art will appreciate that all or part of the steps in the above method can be referred to by program
Related hardware is enabled to complete, described program can store in computer readable storage medium, such as read-only memory, hard disk or light
Disk etc..Optionally, one or more integrated circuit can be used also to realize in all or part of the steps of above-described embodiment.Phase
It answers, each modular unit in above-described embodiment, can be realized using example, in hardware, it can also be by the form of software function module
It realizes, the application is not limited to the combination of the software and hardware of any particular form.User equipment, terminal and UE packet in the application
Include but be not limited to unmanned plane, the communication module on unmanned plane, telecontrolled aircraft, aircraft, baby plane, mobile phone, tablet computer, pen
Remember this, vehicular communication equipment, wireless sensor, card of surfing Internet, internet-of-things terminal, RFID terminal, NB-IOT terminal, MTC
(Machine Type Communication, machine type communication) terminal, eMTC (enhanced MTC, the MTC of enhancing) is eventually
End, data card, card of surfing Internet, vehicular communication equipment, inexpensive mobile phone, the equipment such as inexpensive tablet computer.Base station in the application
Including but not limited to macrocell base stations, microcell base station, Home eNodeB, relay base station, gNB (NR node B), TRP
Wireless telecom equipments such as (Transmitter Receiver Point transmit and receive node).
The above, the only preferred embodiment of the application, are not intended to limit the protection scope of the application.It is all
Within spirit herein and principle, any modification made, equivalent replacement, improve etc., it should be included in the protection of the application
Within the scope of.
Claims (16)
1. the method in the first node that be used to wirelessly communicate characterized by comprising
Execute the first operation；
Wherein, the first bit sequence and the second bit sequence are outputting and inputting for first operation respectively, second ratio
Bit included by special sequence is identical with bit included by first bit sequence；First bit sequence by Q1 according to
The first kind bit subsequence of secondary arrangement forms, and preceding Q1-1 in the Q1 first kind bit subsequences being arranged successively the
A kind of bit subsequence is respectively by 1,3 ..., and 2 times of Q1 subtracts the bit composition that 3 resulting differences are arranged successively again；Described
The second class bit subsequence that two bit sequences are arranged successively by Q2 forms, the Q2 the second class bit being arranged successively
It include Q3 the second class bit subsequences pair, any second class bit of the Q3 the second class bit subsequence centerings in sequence
Sequence is to including the identical second class bit subsequence of two length；In the Q2 the second class bit subsequences being arranged successively
Any second class bit subsequence in a be up to bit belong to the first kind bit subsequences that the Q1 is arranged successively
In any one first kind bit subsequence；The Q1 and Q2 is greater than 1 positive integer respectively, and the Q3 is less than institute
State the nonnegative integer of Q2.
2. the method according to claim 1, wherein including:
Execute channel coding；
Wherein, first bit sequence is the output of the channel coding.
3. method according to claim 1 or 2 characterized by comprising
Send the first wireless signal；
Wherein, second bit sequence be used to generate first wireless signal.
4. according to claim 1 to method described in any claim in 3, which is characterized in that the Q2 add 1 sum with it is described
Q1 is equal with 2 product.
5. according to claim 1 to method described in any claim in 3, which is characterized in that the Q2 add 2 sum with it is described
Q1 is equal with 2 product.
6. the method according to claim 1, which is characterized in that the first node is base station；
Or the first node is user equipment.
7. the method in the second node that be used to wirelessly communicate characterized by comprising
Execute the second operation；
Wherein, the first sequence of real numbers and the second sequence of real numbers are the output and input of second operation respectively, and described second is real
Real number included by Number Sequence is identical with real number included by first sequence of real numbers；First sequence of real numbers by Q1 according to
The first kind real number subsequence of secondary arrangement forms, and preceding Q1-1 in the Q1 first kind real number subsequences being arranged successively the
A kind of real number subsequence is respectively by 1,3 ..., and 2 times of Q1 subtracts the real number composition that 3 resulting differences are arranged successively again；Described
The second class real number subsequence that two sequence of real numbers are arranged successively by Q2 forms, the Q2 the second class real number being arranged successively
It include Q3 the second class real number subsequences pair, any second class real number of the Q3 the second class real number subsequence centerings in sequence
Sequence is to including the identical second class real number subsequence of two length；In the Q2 the second class real number subsequences being arranged successively
Any second class real number subsequence in a be up to real number belong to the first kind real number subsequences that the Q1 is arranged successively
In any one first kind real number subsequence；The Q1 and Q2 is greater than 1 positive integer respectively, and the Q3 is less than institute
State the nonnegative integer of Q2.
8. the method according to the description of claim 7 is characterized in that including:
Execute channel decoding；
Wherein, first sequence of real numbers is the input of the channel decoding.
9. method according to claim 7 or 8 characterized by comprising
Receive the first wireless signal；
Wherein, first wireless signal be used to generate second sequence of real numbers.
10. the method according to any claim in claim 7 to 9, which is characterized in that the Q2 adds 1 sum and institute
It is equal with 2 product to state Q1.
11. the method according to any claim in claim 7 to 9, which is characterized in that the Q2 adds 2 sum and institute
It is equal with 2 product to state Q1.
12. the method according to any claim in claim 7 to 10, which is characterized in that the second node is to use
Family equipment；Or the second node is base station.
13. the equipment in the first node that be used to wirelessly communicate characterized by comprising
First processing module executes the first operation；
Wherein, the first bit sequence and the second bit sequence are outputting and inputting for first operation respectively, second ratio
Bit included by special sequence is identical with bit included by first bit sequence；First bit sequence by Q1 according to
The first kind bit subsequence of secondary arrangement forms, and preceding Q1-1 in the Q1 first kind bit subsequences being arranged successively the
A kind of bit subsequence is respectively by 1,3 ..., and 2 times of Q1 subtracts the bit composition that 3 resulting differences are arranged successively again；Described
The second class bit subsequence that two bit sequences are arranged successively by Q2 forms, the Q2 the second class bit being arranged successively
It include Q3 the second class bit subsequences pair, any second class bit of the Q3 the second class bit subsequence centerings in sequence
Sequence is to including the identical second class bit subsequence of two length；In the Q2 the second class bit subsequences being arranged successively
Any second class bit subsequence in a be up to bit belong to the first kind bit subsequences that the Q1 is arranged successively
In any one first kind bit subsequence；The Q1 and Q2 is greater than 1 positive integer respectively, and the Q3 is less than institute
State the nonnegative integer of Q2.
14. the equipment in first node according to claim 13 characterized by comprising
First sender module sends the first wireless signal；
Wherein, second bit sequence be used to generate first wireless signal.
15. the equipment in the second node that be used to wirelessly communicate characterized by comprising
Second processing module executes the second operation；
Wherein, the first sequence of real numbers and the second sequence of real numbers are the output and input of second operation respectively, and described second is real
Real number included by Number Sequence is identical with real number included by first sequence of real numbers；First sequence of real numbers by Q1 according to
The first kind real number subsequence of secondary arrangement forms, and preceding Q1-1 in the Q1 first kind real number subsequences being arranged successively the
A kind of real number subsequence is respectively by 1,3 ..., and 2 times of Q1 subtracts the real number composition that 3 resulting differences are arranged successively again；Described
The second class real number subsequence that two sequence of real numbers are arranged successively by Q2 forms, the Q2 the second class real number being arranged successively
It include Q3 the second class real number subsequences pair, any second class real number of the Q3 the second class real number subsequence centerings in sequence
Sequence is to including the identical second class real number subsequence of two length；In the Q2 the second class real number subsequences being arranged successively
Any second class real number subsequence in a be up to real number belong to the first kind real number subsequences that the Q1 is arranged successively
In any one first kind real number subsequence；The Q1 and Q2 is greater than 1 positive integer respectively, and the Q3 is less than institute
State the nonnegative integer of Q2.
16. the equipment in second node according to claim 15 characterized by comprising
First receiver module receives the first wireless signal；
Wherein, first wireless signal be used to generate second sequence of real numbers.
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| CN112688756A (en) * | 2020-12-22 | 2021-04-20 | 重庆邮电大学 | Method and device for generating signal by two-couple length QPSKZ complementary sequence pair |
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