Nothing Special   »   [go: up one dir, main page]

CN109446125B - DDR read-write arbiter and method - Google Patents

DDR read-write arbiter and method Download PDF

Info

Publication number
CN109446125B
CN109446125B CN201811171175.3A CN201811171175A CN109446125B CN 109446125 B CN109446125 B CN 109446125B CN 201811171175 A CN201811171175 A CN 201811171175A CN 109446125 B CN109446125 B CN 109446125B
Authority
CN
China
Prior art keywords
read
write
data
unit
ddr
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201811171175.3A
Other languages
Chinese (zh)
Other versions
CN109446125A (en
Inventor
唐东升
魏恒
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Wuhan Gewei Electronic Technology Co Ltd
Original Assignee
Wuhan Gewei Electronic Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Wuhan Gewei Electronic Technology Co Ltd filed Critical Wuhan Gewei Electronic Technology Co Ltd
Priority to CN201811171175.3A priority Critical patent/CN109446125B/en
Publication of CN109446125A publication Critical patent/CN109446125A/en
Application granted granted Critical
Publication of CN109446125B publication Critical patent/CN109446125B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/161—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1673—Details of memory controller using buffers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/18—Handling requests for interconnection or transfer for access to memory bus based on priority control

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)
  • Communication Control (AREA)
  • Information Transfer Systems (AREA)

Abstract

The invention discloses a DDR read-write arbiter and a method thereof, wherein the DDR read-write arbiter mainly comprises a read conversion unit, a write conversion unit, a fair arbitration unit, a command splitting unit, a flow control protection unit, a handshake logic unit, a routing control unit, a first FIFO unit, a second FIFO unit and a third FIFO unit. The invention can realize parallel access of multiple paths of read-write users; writing the conversion from the user interface and the read user interface to the arbiter interface, and carrying out sectional processing on the application of the user; data buffer management of a read user and a write user; fair arbitration is realized for multiple users; disassembling the application of the read-write user into a command stream and a data stream which can be executed by the DDR controller; DDR flow control protection mechanism; the user reads the data route.

Description

DDR read-write arbiter and method
Technical Field
The invention relates to DDR, in particular to DDR read-write arbiter and arbitration method.
Background
DDR memory has been widely used in various product solutions today. Currently, many CPUs incorporate DDR controllers, and the operating system and applications determine the scheduling process for the DDR controllers. However, for special digital circuit designs with high real-time requirements, the scheduling problem of FPGA or ASIC chips for DDR is not as easy to control as for software systems. In the FPGA field, xilinx and Intel both offer mature and free DDR controller IPs, but these IPs are all for one user. In a system design, there may be multiple modules that require simultaneous access to the DDR controller. An arbiter is generally adopted to solve the problem of allocation of the usage rights of multiple users to the DDR controller. In a simpler arbiter, the whole access period is generally allocated to a certain user, and the processes of handshaking, waiting and the like during the period waste much time, and finally, the access efficiency of DDR is not improved. The access behavior characteristics of different users are different: some access data are large, if the arbiter makes all data accessed at one time, other users' applications may not be responded later, resulting in system errors; some writing users have small data volume, after the writing application is initiated, the writing data is delayed, or the data bandwidth of the writing users cannot keep up with the speed of the DDR controller; and the rate of processing read data is not as fast as that of the DDR controller by some read users, so that the DDR controller needs to be accessed continuously after the read data is processed by the users in order to avoid cache overflow. This is why DDR controllers are not efficient in access. The DDR read-write arbitration method provided by the invention can better solve the problems.
Disclosure of Invention
The invention aims to provide a DDR read-write arbitration method, which is mainly used for improving the access efficiency of DDR when multiple users access DDR memory in parallel in the field of programmable logic systems or ASICs.
The technical scheme adopted by the invention for achieving the purposes is as follows:
there is provided a DDR read-write arbiter comprising:
the writing conversion units are used for subdividing writing operation of writing data with a certain length applied by a user into a plurality of small batches of writing application and submitting the small batches of writing application to the command splitting unit;
the read conversion units are used for subdividing the read operation of reading the data with a certain length applied by the user into a plurality of small batches of read applications and submitting the small batches of read applications to the command splitting unit;
the command splitting unit is used for splitting the small batch of read and write commands into commands which can be recognized by the DDR controller, storing the read and write commands into the first FIFO unit and storing the write data into the second FIFO unit;
the fairness arbitration unit is used for numbering each read user and each write user, arbitrating the priority of each read user and each write user, generating a routing table and storing the routing table in the third FIFO unit;
the flow control protection unit is used for monitoring whether the first FIFO unit and the second FIFO unit have enough allowance, if not, the command splitting unit is suspended to split the commands of the current batch;
the handshake logic unit is used for reading the read command, the write command and the write data from the first FIFO unit and the second FIFO unit respectively and sending the read command, the write command and the write data to the DDR controller according to the handshake requirement of the DDR controller;
and the routing control unit is used for acquiring the routing table from the third FIFO unit, and performing routing selection according to the routing table when the DDR controller returns data.
With the technical scheme, when the read conversion unit and the write conversion unit divide small batches, the batch size is set to be 1/2 or 1/4 of the ROW length of DDR.
The reading conversion unit is further used for calculating unreturned data of the DDR controller and determining whether to continue to submit the reading application according to the unreturned data, specifically recording the data of the reading data which is applied to the DDR controller in a common way, recording how many pieces of the reading data are returned by the DDR controller in a common way, wherein the difference between the data is the unreturned data of the DDR controller, the residual data quantity in the second FIFO unit and the maximum batch number are added, and if the sum is greater than the depth L of the second FIFO unit, the reading conversion unit does not submit the reading application any more.
With the above technical scheme, when the sum of the unreturned data of the DDR controller, the residual data quantity in the second FIFO unit and the maximum batch number is greater than L-4, the read conversion unit does not submit the read application.
The write conversion unit is further configured to determine whether the second FIFO unit has enough data space, and if so, continue to submit the write application of the current batch.
The DDR read-write arbiter is characterized in that the flow control protection unit is specifically used for monitoring the pre-filling state of the first FIFO unit and the second FIFO unit, and when the first FIFO unit is pre-filled, the read command and the write command need to wait; when the second FIFO element is pre-full, the write command pauses and the read command continues to split.
The invention also provides a DDR read-write arbitration method, which comprises the following steps:
subdividing read and write operations of a plurality of read users and write users into a plurality of small-batch read and write applications;
splitting the small batch of read and write commands into commands which can be identified by the DDR controller, storing the read and write commands into a first FIFO unit, and storing write data into a second FIFO unit;
numbering each read user and each write user, arbitrating the priority of each read user and each write user, generating a routing table and storing the routing table in a third FIFO unit;
monitoring whether the first FIFO unit and the second FIFO unit have enough allowance, if not, suspending command splitting of the current batch;
reading a read command, a write command and write data from the first FIFO unit and the second FIFO unit respectively, and sending the read command, the write command and the write data to the DDR controller according to the handshake requirement of the DDR controller;
and acquiring a routing table from the third FIFO unit, and performing routing according to the routing table when the DDR controller returns data.
In the case of the above-described technical scheme, the batch size is set to 1/2 or 1/4 of the ROW length of DDR when small batches are subdivided.
According to the technical scheme, the data which is not returned by the DDR controller is calculated, whether to continue submitting the read application is determined, specifically, the data of the read data which is applied to the DDR controller in a common direction is recorded, the total number of the read data which is returned by the DDR controller is recorded, the difference between the data which is not returned by the DDR controller is the data which is not returned by the DDR controller, the residual data quantity in the second FIFO unit and the maximum batch number are added, if the sum is larger than L-4, the read application is not submitted by the read conversion unit, and L is the depth of the second FIFO unit.
When responding to the read user application, the next arbitrated application valid write user leads the write data into the second FIFO unit in advance.
The invention has the beneficial effects that: the invention expands the single user read-write interface of the DDR controller into a read interface and a write interface which support multi-user concurrent access. Each read user and write user enjoys equal opportunity to be served, i.e. avoids the situation that one party monopolizes the DDR bus for a long time. And when multiple users access concurrently, the higher DDR use efficiency can be ensured (the efficiency can reach more than 80% when accessing in batches).
Furthermore, compared with the DDR control read-write interface, the read-write interface for the user has the advantages that the operation process is simpler and more convenient and easy to realize. Fully excavate DDR space and time resource, not only improve system performance, but also reduce design cost.
Drawings
The invention will be further described with reference to the accompanying drawings and embodiments, in which:
FIG. 1 is a schematic diagram of a DDR read/write arbiter according to an embodiment of the present invention.
Fig. 2 is an external interface of the write switching unit.
Fig. 3 is an external interface of the read-conversion unit.
Fig. 4 is a command application interface timing illustration.
FIG. 5 is a timing illustration of a write data stream interface.
Fig. 6 is a fair arbitration example.
FIG. 7 is a flow chart of DDR read/write arbitration according to an embodiment of the invention.
Detailed Description
The present invention will be described in further detail with reference to the drawings and examples, in order to make the objects, technical solutions and advantages of the present invention more apparent. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention.
The DDR read-write arbiter of the invention has a structure shown in figure 1, and mainly comprises a read conversion unit, a write conversion unit, a fairness arbitration unit, a command splitting unit, a flow control protection unit, a handshake logic unit, a route control unit, a FIFO1, a FIFO2 and a FIFO3.
The writing conversion units are used for subdividing writing operation of writing data with a certain length applied by a user into a plurality of small batches of writing application and submitting the small batches of writing application to the command splitting unit;
the read conversion units are used for subdividing the read operation of reading the data with a certain length applied by the user into a plurality of small batches of read applications and submitting the small batches of read applications to the command splitting unit;
the command splitting unit is used for splitting the small batch of read and write commands into commands which can be recognized by the DDR controller, storing the read and write commands into the FIFO1 and storing the write data into the second FIFO unit;
a fairness arbitration unit for numbering each read user and write user, arbitrating their priority, and generating a routing table to store in FIFO 3;
the flow control protection unit is used for monitoring whether the FIFO1 and the FIFO2 have enough allowance, and if not, the command splitting unit pauses the command splitting of the current batch;
the handshake logic unit is used for reading the read command, the write command and the write data from the FIFO1 and the FIFO2 respectively and sending the read command, the write command and the write data to the DDR controller according to the handshake requirement of the DDR controller;
and the routing control unit is used for acquiring the routing table from the FIFO3, and performing routing selection according to the routing table when the DDR controller returns data.
The external interface of the write switching unit is shown in fig. 2. The write conversion unit comprises a write command batch control module and a write FIFO module, a write user can apply for write operation of data with any length once, the write command batch control module subdivides the application into a plurality of small-batch write applications, and the small-batch write applications are submitted to the fairness arbitration unit. The data of the writing user is firstly buffered in the writing FIFO module, and after the DDR arbiter responds to the application, the data in the writing FIFO module is forwarded to the arbiter.
The external interface of the read-conversion unit is shown in fig. 3. The read conversion unit comprises a read command batch control module and a read FIFO module, a read user can apply for the read operation of data with any length once, the read command batch control module subdivides the application into a plurality of small-batch read applications, and the small-batch read applications are submitted to the fairness arbitration unit. The read data output by the route control unit is firstly buffered in the read FIFO module, and the data is taken away from the read FIFO module when the read user is ready.
And the fairness arbitration unit ensures that a plurality of read-write users enjoy equal service opportunities. The other characteristic is that when responding to the application of the read user, the next arbitrated application is effective, the write data can be imported into the write data FIFO in advance, and the throughput rate of the arbiter is further improved.
The command splitting unit is used for further splitting the small batch of read-write commands into commands which can be recognized by the DDR controller. FIFO1 buffers write commands (including addresses) of the DDR controller, FIFO2 buffers write data of the DDR controller. The arbitration logic needs to guarantee that the two FIFOs are safe by means of the judgment of the flow control protection unit, otherwise, command splitting of the current batch is suspended, and execution is continued after enough margin exists between the FIFO1 and the FIFO 2. Handshake logic, which implements the timing required by the DDR controller, derives the command stream and the write data stream from the FIFO.
The fairness arbitration unit outputs a routing table stored in FIFO3 for use by the routing control logic.
The user clocks of the read and write switching units may be independent of the arbitration unit (and subsequent other units), as well as the bit width of the user data. FIFOs (see fig. 2 and 3) inside the read and write switching units are used for buffering the data stream on the one hand and for clock domain switching and data bit width switching on the other hand.
The interfaces between the read conversion unit and the write conversion unit and the user adopt signal handshakes of cmd_addr, cmd_len, cmd_req and cmd_rdy. cmd_addr represents the starting address at which access is requested; cmd_len represents the total length of the access requested this time; when cmd_req is high, indicating an application access; when cmd_rdy is high, this indicates that the application is responding. After cmd_req is pulled high, it is necessary to keep the high state until cmd_rdy goes high. If the user still has a write request at a later time, cmd_req may continue to be pulled high, and if no write request has been made at a later time, cmd_req needs to be pulled low immediately (in effect at the next beat of cmd_rdy pull high). Fig. 4 reflects the timing relationship between these several signals. At time t1, the application gets a response, and the next beat continuously sends the application (cmd_req maintains a high level); at time t1, the application gets a response, but does not continue with the application after that (cmd_req pulled low). The handshake logic writes the control flow to the DDR controller, also implemented with such an interface.
And the transmission interface for writing the user data adopts data, data_valid and data_rdy to carry out handshake. Wherein, data represents data to be written, data_valid represents that the data of the sender requests to be written to the receiver, data_rdy represents that the receiver is ready, and data is successfully written only when the data_valid and the data_rdy are simultaneously high. The timing relationship of these 3 signals is shown in fig. 5, and D0 to D4 are successively written successfully without repetition. Handshake logic writes transmit data to the DDR controller, also implemented with this interface.
Preferably, to meet the timing interface shown in fig. 5, the sender of the data (such as the user) may use a pre-read mechanism of FIFO, i.e. the data is always ready in advance. When the read enable of the FIFO is active, the next read data is taken from the FIFO. The valid is obtained by inverting the empty of the FIFO, and when the receiving side sends out rdy and generates the read enable of the FIFO, the next read data will be ready at the next beat. If the next beat of data is not ready (FIFO empty), then empty must be high, with the corresponding valid low. At this time, the data is invalid even if rdy given by the receiving side is high.
Preferably, to satisfy the timing interface shown in fig. 5, the receiving side (e.g., the write transfer unit) may invert the FIFO full (all full) signal as rdy. Rdy is high when there is sufficient buffer space in the FIFO to represent that data can be written. Write enable of the FIFO is obtained by valid and rdy and operations. To improve timing, the result of the AND can be tapped (data is also tapped synchronously) via flip-Flop, and since this logic is done using the FIFO pre-full signal, there is no concern that the FIFO is truly full after the tap. For example, for a 512 depth FIFO, it is safe to set the pre-full threshold to 510 or less.
Both read and write switching units use the idea of batch operation. The batch is to segment the data actually accessed by the user into N batches, and submit the N batches to the fairness arbitration unit. For example, there are two users a and B, a is divided into segments A1, A2, … …, an, and B is divided into segments B1, B2, … …, bm. After submitting these applications to the arbitration unit, the final served order may become A1, B1, A2, B2, … …. The advantage of this approach is that a and B can be considered to be serviced simultaneously as a whole. If B is left to wait for all data of a to be accessed, then B may be misplaced because the service did not respond in time.
The determination of batch size is also taught. Research shows that continuous or continuous writing (burst operation, address continuous) to DDR memory can greatly improve DDR access efficiency. If the read-write interleaving is performed, the efficiency is reduced even if the addresses are consecutive. From this point of view, the larger the batch length, the better. But if too large, other problems may result. 1. The buffer overhead for the read and write users is greater. 2. The service time for a certain user must be long due to the too large batch, and other users may be left 'empty', etc. accordingly, resulting in a decrease in the efficiency of arbitration.
Preferably, the batch size is set to 1/2 or 1/4 of the ROW length of DDR, so that the effect is preferable. The actual access length of the user is not necessarily an integer multiple of the batch size, so batch processing logic needs to determine whether the batch is currently the last batch. If so, the access length of the batch needs to be adjusted. For example, the read user applies to access 3589 data, and the length of the batch operation is 256. Then the user's application will be made in 15 batches, the first 14 batches being 256 in length and the last 4 in length.
After the write user applies to access the DDR, the subsequent write data stream may be temporarily not ready. Even if it is ready soon, the data rate of the potential write user cannot match the rate of the DDR controller. To solve this problem, the write switching unit sends out a current batch of write requests to the fair arbitration unit after determining that there is enough data (greater than or equal to the current segment size) in the FIFO. Therefore, the arbiter is prevented from waiting the user independently, and the saved time can provide service for other users.
When reading DDR data, there is a large delay (typically several tens of clock cycles) in returning the read data from the time of the previously sent read instruction. Therefore, for read transitions, it is anticipated in advance whether a FIFO that buffers user read data may overflow. For example, assuming a FIFO depth of 512, 360 data remain in the current FIFO, there are 32 read data not returned by the DDR controller (due to latency) and the read user still has a request for read data at this time, the batch size is 128. In this case, if the read converting unit continues to submit the read application of the 128 data to the DDR controller, overflow of the FIFO may be caused. Because 360+32+128>512, if the read user does not fetch data from the FIFO at this time, the data returned by the subsequent DDR must be written to the FIFO, eventually resulting in an overflow.
As a preferred solution, the method for the read conversion unit to calculate that the DDR controller does not return data: the cnt1 is used for recording the number of read data which are applied to the DDR controller from one side, the cnt2 is used for recording how many read data are returned from the DDR controller, and the cnt1 minus the cnt2 is the data cnt_diff which are not returned by the DDR. At this time, cnt_diff, the amount of data remaining in the FIFO, and the maximum batch number are added, and if the total number of data is greater than the depth L of the FIFO, the read conversion unit cannot continue submitting the read application to the DDR arbiter at this time. In actual operation, a certain margin is ensured, and the L-4 is used as a comparison threshold to be safer.
And the fairness arbitration unit is used for numbering each read user and each write user. Preferably, the fair arbitration unit records the number for the priority adjustment of the next arbitration every time the fair arbitration unit responds to one user. Fig. 6 depicts a process for arbitrating for 4 users. When usr_id is 0, the priority of usr1 is highest, usr2 times; when usr_id is 1, the priority of usr2 is highest, usr3 times; … …; when usr_id is 3, the priority of usr0 is highest, usr1 times. The arbitration logic can only give a rdy signal for one user at a time, indicating that the request of the current user passes, usr_id is updated to the user ID that was just passed in the next cycle. At time t1, 4 users all have applications, but when the usr_id is 0, the application of the user1 passes first, and then the applications of the user2, the user3 and the user0 are performed. At time t6, although usr_id is 1, there is no application by user2, so that usr3 has a higher priority than user1, so that application by user3 passes, and then usr_id becomes 3.
The command splitting unit further splits the user command passing through the application. The read command stream and the write command stream are stored in FIFO1 and the data stream is stored in FIFO 2. And the flow control protection unit is used for monitoring the pre-filling state of the FIFO1 and the FIFO2 and providing judgment conditions for the arbitration unit. When FIFO1 is pre-full, it is necessary to wait, either for a read command or for a write command. When FIFO2 is pre-full, the write command may be suspended without affecting the de-assembly of the read command. This effect benefits from the parallel arbitration mechanism of the arbitration logic for the read and write users. As a preferred scheme, the FIFO1 buffer depth is 64, the FIFO2 buffer depth is 32, and the two FIFOs are built by using logic resources (resources such as Block RAM or M9K are not needed). The FIFO1 pre-full threshold is set to 60 and the FIFO2 pre-full threshold is set to 28.
The routing table output by the arbitration logic, which consists of the user_id and the data of the readings applied by the user, is stored in the FIFO3. When the DDR controller returns data, the DDR controller counts the data, and the user to which the data returned currently belongs can be known by combining a routing table, so that the routing is realized. The update of the routing table accords with the rule of first-in first-out, and is suitable for being realized by using the FIFO. To reduce routing delay and allow for timing, the FIFO enables a pre-read mechanism. And decoding the valid of each user by using the user_id information output by the FIFO, wherein the design can be satisfied only by one clock beat delay. Write enable of FIFO3 is provided by arbitration logic. The read enable of FIFO3 needs to determine whether the data returned in the DDR controller corresponds to the last read data of the current user_id.
The above units and the adopted schemes are related, namely the general method for forming the DDR read-write arbiter of the patent, as shown in FIG. 7, the DDR read-write arbitration method mainly comprises the following steps:
s1, subdividing reading and writing operations of a reading user and a writing user into a plurality of small-batch reading and writing applications;
s2, further splitting the small batches of read and write commands into commands which can be identified by the DDR controller, storing the read and write commands into the FIFO1, and storing the write data into the FIFO2;
s3, numbering each read user and each write user, judging the priority of each read user and each write user, generating a routing table and storing the routing table in the FIFO 3;
s4, monitoring whether the units of the FIFO1 and the FIFO2 have enough allowance, if not, suspending command splitting of the current batch;
s5, reading the read command, the write command and the write data from the FIFO1 and the FIFO2 units respectively, and sending the read command, the write command and the write data to the DDR controller according to the handshake requirement of the DDR controller;
s6, acquiring a routing table from the FIFO3 unit, and performing routing selection according to the routing table when the DDR controller returns data.
The write user can apply for write operation of data with any length at a time, the write conversion unit subdivides the application into a plurality of small-batch write applications, and the small-batch write applications are submitted to the fairness arbitration unit. The data of the writing user is firstly cached in the FIFO, and when the DDR arbiter responds to the application, the data in the FIFO is forwarded to the arbiter.
The reading user can apply for the reading operation of any length data at a time, and the reading conversion unit subdivides the application into a plurality of small-batch reading applications and submits the small-batch reading applications to the fairness arbitration unit. The read data output by the routing unit is firstly cached in the FIFO, and the read data is taken out of the FIFO when the read user is ready. And the fairness arbitration unit ensures that a plurality of read-write users enjoy equal service opportunities. The other characteristic is that when responding to the application of the read user, the next arbitrated application is effective, the write data can be imported into the write data FIFO in advance, and the throughput rate of the arbiter is further improved. The command splitting unit is used for further splitting the small batch of read-write commands into commands which can be recognized by the DDR controller. FIFO1 buffers write commands (including addresses) of the DDR controller, FIFO2 buffers write data of the DDR controller. The arbitration logic needs to guarantee that the two FIFOs are safe by means of the judgment of the flow control protection unit, otherwise, command splitting of the current batch is suspended, and execution is continued after enough margin exists between the FIFO1 and the FIFO 2. Handshake logic, which implements the timing required by the DDR controller, derives the command stream and the write data stream from the FIFO. The fairness arbitration unit outputs a routing table stored in FIFO3 for use by the routing control logic.
The FIFO1 is mainly used for storing commands of the DDR controller; the FIFO2 is mainly used for storing write data of the DDR controller; the FIFO3 is mainly used for storing and reading a user routing table; the flow control protection module is used for detecting the pre-filling state of the FIFO1 and the FIFO2, and the result is transmitted to the fairness arbitration module; the routing control module is mainly used for acquiring a routing table from the FIFO3 and forwarding read data of the DDR controller to each read conversion module according to the user ID; handshake logic function: commands and write data of the DDR controller are respectively read out from the FIFO1 and the FIFO2 and sent to the DDR controller according to the handshake requirement of the DDR controller (the specific mode depends on the specification of the DDR controller).
The invention can realize the following functions: multiple paths of read-write users access in parallel; writing the conversion from the user interface and the read user interface to the arbiter interface, and carrying out sectional processing on the application of the user; realizing data cache management of a read user and a write user; fair arbitration is realized for multiple users; disassembling the application of the read-write user into a command stream and a data stream which can be executed by the DDR controller; DDR flow control protection mechanism; the user reads the data route.
In summary, the invention expands the single user read-write interface of the DDR controller into a read interface and a write interface supporting multi-user concurrent access. Each read user and write user enjoys equal opportunity to be served, i.e. avoids the situation that one party monopolizes the DDR bus for a long time. And when multiple users access concurrently, the higher DDR use efficiency can be ensured (the efficiency can reach more than 80% when accessing in batches). Furthermore, compared with the DDR control read-write interface, the read-write interface for the user has the advantages that the operation process is simpler and more convenient and easy to realize. Fully excavate DDR space and time resource, not only improve system performance, but also reduce design cost.
It will be understood that modifications and variations will be apparent to those skilled in the art from the foregoing description, and it is intended that all such modifications and variations be included within the scope of the following claims.

Claims (8)

1. A DDR read/write arbiter comprising:
the writing conversion units are used for subdividing writing operation of writing data with a certain length applied by a user into a plurality of small batches of writing application and submitting the small batches of writing application to the command splitting unit;
the read conversion units are used for subdividing the read operation of reading the data with a certain length applied by the user into a plurality of small batches of read applications and submitting the small batches of read applications to the command splitting unit; the read conversion unit is further used for calculating unreturned data of the DDR controller and determining whether to continue submitting the read application or not, specifically recording the data of the read data which are applied to the DDR controller from one side, recording how many read data are returned from the DDR controller, wherein the difference between the data is the unreturned data of the DDR controller, the residual data quantity in the second FIFO unit and the maximum batch number are added, and if the sum is greater than the depth L of the second FIFO unit, the read conversion unit does not submit the read application any more;
the command splitting unit is used for splitting the small batch of read and write commands into commands which can be recognized by the DDR controller, storing the read and write commands into the first FIFO unit and storing the write data into the second FIFO unit;
the fairness arbitration unit is used for numbering each read user and each write user, arbitrating the priority of each read user and each write user, generating a routing table and storing the routing table in the third FIFO unit;
the flow control protection unit is used for monitoring whether the first FIFO unit and the second FIFO unit have enough allowance, if not, the command splitting unit is suspended to split the commands of the current batch;
the handshake logic unit is used for reading the read command, the write command and the write data from the first FIFO unit and the second FIFO unit respectively and sending the read command, the write command and the write data to the DDR controller according to the handshake requirement of the DDR controller;
and the routing control unit is used for acquiring the routing table from the third FIFO unit, and performing routing selection according to the routing table when the DDR controller returns data.
2. The DDR read write arbiter of claim 1, wherein the read switch unit and the write switch unit, when subdividing small batches, set the batch size to 1/2 or 1/4 of the ROW length of the DDR.
3. The DDR read write arbiter of claim 1, wherein the read switch unit no longer submits a read request when the data not returned by the DDR controller, the amount of data remaining in the second FIFO unit, the maximum number of batches, is greater than L-4.
4. The DDR read/write arbiter of claim 1, wherein the write switch unit is further configured to determine whether there is sufficient data space in the second FIFO unit, and if so, to continue submitting write requests of the current lot.
5. The DDR read-write arbiter of claim 1, wherein the flow control protection unit is specifically configured to monitor a pre-full state of the first FIFO unit and the second FIFO unit, and when the first FIFO unit is pre-full, both read and write commands need to wait; when the second FIFO element is pre-full, the write command pauses and the read command continues to split.
6. A DDR read-write arbitration method is characterized by comprising the following steps:
subdividing read and write operations of a plurality of read users and write users into a plurality of small-batch read and write applications;
splitting the small batch of read and write commands into commands which can be identified by the DDR controller, storing the read and write commands into a first FIFO unit, and storing write data into a second FIFO unit; calculating unreturned data of the DDR controller and determining whether to continue to submit a read application according to the unreturned data, specifically recording the data of the read data which are applied to the DDR controller altogether, recording how many read data are returned by the DDR controller altogether, wherein the difference between the data is the unreturned data of the DDR controller, the residual data quantity in the second FIFO unit and the maximum batch number are added, if the sum is greater than L-4, the read application is not submitted by the read conversion unit any more, and L is the depth of the second FIFO unit;
numbering each read user and each write user, arbitrating the priority of each read user and each write user, generating a routing table and storing the routing table in a third FIFO unit;
monitoring whether the first FIFO unit and the second FIFO unit have enough allowance, if not, suspending command splitting of the current batch;
reading a read command, a write command and write data from the first FIFO unit and the second FIFO unit respectively, and sending the read command, the write command and the write data to the DDR controller according to the handshake requirement of the DDR controller;
and acquiring a routing table from the third FIFO unit, and performing routing according to the routing table when the DDR controller returns data.
7. The DDR read/write arbitration method of claim 6, wherein when small batches are subdivided, a batch size is set to 1/2 or 1/4 of a ROW length of DDR.
8. The DDR read write arbitration method of claim 6, wherein in response to a read user request, the next write user who is arbitrated to be active, write data thereof is imported into the second FIFO unit in advance.
CN201811171175.3A 2018-10-09 2018-10-09 DDR read-write arbiter and method Active CN109446125B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201811171175.3A CN109446125B (en) 2018-10-09 2018-10-09 DDR read-write arbiter and method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201811171175.3A CN109446125B (en) 2018-10-09 2018-10-09 DDR read-write arbiter and method

Publications (2)

Publication Number Publication Date
CN109446125A CN109446125A (en) 2019-03-08
CN109446125B true CN109446125B (en) 2024-04-02

Family

ID=65545586

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201811171175.3A Active CN109446125B (en) 2018-10-09 2018-10-09 DDR read-write arbiter and method

Country Status (1)

Country Link
CN (1) CN109446125B (en)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110413540B (en) * 2019-06-28 2021-07-16 苏州浪潮智能科技有限公司 Method, system, equipment and storage medium for FPGA data caching
CN110516329B (en) * 2019-08-15 2022-02-18 上海天数智芯半导体有限公司 Digital circuit design method for solving multi-access storage unit cluster conflict through reservation mechanism
CN111091854A (en) * 2019-11-21 2020-05-01 中国航空工业集团公司西安航空计算技术研究所 Command processor and DDR read-write access circuit
CN110968534B (en) * 2019-11-26 2021-11-30 航天恒星科技有限公司 Multi-channel fragment merging processing method and system based on FPGA
CN110910921A (en) * 2019-11-29 2020-03-24 深圳市国微电子有限公司 Command read-write method and device and computer storage medium
CN111610934A (en) * 2020-05-22 2020-09-01 上海大骋医疗科技有限公司 DDR controller and control method
CN111783167B (en) * 2020-07-24 2024-10-01 Oppo广东移动通信有限公司 FIFO read-write control circuit, chip, electronic device and data transmission method
CN112052205B (en) * 2020-08-31 2022-07-08 浙江双成电气有限公司 DDR3 multi-port read-write storage management method based on FPGA
CN112052206B (en) * 2020-08-31 2023-03-28 浙江双成电气有限公司 Multi-port data storage system based on arbitration
CN112559399A (en) * 2020-11-27 2021-03-26 山东云海国创云计算装备产业创新中心有限公司 DDR controller with multiple AXI interfaces and control method thereof
CN112948293A (en) * 2021-02-26 2021-06-11 浪潮电子信息产业股份有限公司 DDR arbiter and DDR controller chip of multi-user interface
CN114036085B (en) * 2021-09-24 2024-04-12 北京无线电测量研究所 DDR 4-based multitasking read-write scheduling method, computer equipment and storage medium

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101876946A (en) * 2009-05-01 2010-11-03 索尼公司 Storage control device and memory control methods
CN105868134A (en) * 2016-04-14 2016-08-17 烽火通信科技股份有限公司 High-performance multi-port DDR (double data rate) controller and method for implementing same
CN106233270A (en) * 2014-04-29 2016-12-14 华为技术有限公司 Share Memory Controller and using method thereof
CN107835989A (en) * 2015-07-13 2018-03-23 华为技术有限公司 Shared storage control and the method using shared storage control

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009193107A (en) * 2008-02-12 2009-08-27 Panasonic Corp Memory access device
TWI433163B (en) * 2009-12-23 2014-04-01 Mstar Semiconductor Inc Memory controller and associated controlling method

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101876946A (en) * 2009-05-01 2010-11-03 索尼公司 Storage control device and memory control methods
CN106233270A (en) * 2014-04-29 2016-12-14 华为技术有限公司 Share Memory Controller and using method thereof
CN107835989A (en) * 2015-07-13 2018-03-23 华为技术有限公司 Shared storage control and the method using shared storage control
CN105868134A (en) * 2016-04-14 2016-08-17 烽火通信科技股份有限公司 High-performance multi-port DDR (double data rate) controller and method for implementing same

Also Published As

Publication number Publication date
CN109446125A (en) 2019-03-08

Similar Documents

Publication Publication Date Title
CN109446125B (en) DDR read-write arbiter and method
KR100716950B1 (en) Bus system
US5444858A (en) Computer systems and methods for pipelined transfer of data between modules
JP4778199B2 (en) Data transfer apparatus and data transfer method
US7107415B2 (en) Posted write buffers and methods of posting write requests in memory modules
JP4124491B2 (en) Packet routing switch that controls access to shared memory at different data rates
US10210117B2 (en) Computing architecture with peripherals
KR100841139B1 (en) A method and apparatus to manage memory access requests
US8095744B2 (en) Device for controlling access from a plurality of masters to shared memory composed of a plurality of banks each having a plurality of pages
CN102841869B (en) Multi-channel I2C controller based on FPGA
WO2011089660A1 (en) Bus arbitration device
CN103543954A (en) Data storage management method and device
CN101504633A (en) Multi-channel DMA controller
US5793994A (en) Synchronous event posting by a high throughput bus
CN112948293A (en) DDR arbiter and DDR controller chip of multi-user interface
US6415367B1 (en) Apparatus for reducing asynchronous service latency in a time slot-based memory arbitration scheme
US20040199706A1 (en) Apparatus for use in a computer systems
JP2008544359A (en) Memory controller
JP7493311B2 (en) BUS SYSTEM AND CONTROL METHOD THEREOF
US6412049B1 (en) Method for minimizing CPU memory latency while transferring streaming data
US6584531B1 (en) Arbitration circuit with plural arbitration processors using memory bank history
CN109145397A (en) A kind of external memory arbitration structure for supporting parallel pipelining process to access
CN113821457A (en) High-performance read-write linked list caching device and method
CN113342724A (en) Data transmission method and device based on FPGA
JPH10307787A (en) Buffer memory device

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant