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CN109390353A - 半导体元件及其制作方法 - Google Patents

半导体元件及其制作方法 Download PDF

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Publication number
CN109390353A
CN109390353A CN201710690789.1A CN201710690789A CN109390353A CN 109390353 A CN109390353 A CN 109390353A CN 201710690789 A CN201710690789 A CN 201710690789A CN 109390353 A CN109390353 A CN 109390353A
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CN
China
Prior art keywords
layer
semiconductor element
dielectric layer
semiconductor
passive device
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Pending
Application number
CN201710690789.1A
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English (en)
Inventor
李文深
智晓愿
陈星星
温晋炀
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United Microelectronics Corp
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United Microelectronics Corp
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Priority to CN201710690789.1A priority Critical patent/CN109390353A/zh
Priority to US15/691,757 priority patent/US20190051666A1/en
Publication of CN109390353A publication Critical patent/CN109390353A/zh
Pending legal-status Critical Current

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Abstract

本发明公开一种半导体元件及其制作方法。该半导体元件包含：一基材，具有一前侧面与一背侧面，其中该基材包含一半导体层以及一埋入绝缘层；至少一晶体管，设于该半导体层上；一层间介电层，设于该前侧面，覆盖该至少一晶体管；一接触结构，贯穿该层间介电层、该半导体层及该埋入绝缘层；一硅化金属层，在该背侧面上覆盖住该接触结构的一端面；及一被动元件，设于该基材的该背侧面上，其中该接触结构电连接至该被动元件。

Description

半导体元件及其制作方法
技术领域
本发明涉及半导体技术领域，特别是涉及一种硅覆绝缘(silicon-on-insulator，SOI)半导体元件及其制作方法。
背景技术
相较于构建在硅基底中的半导体元件，使用硅覆绝缘(silicon-on-insulator，SOI)技术制造的半导体元件通常可以表现出一定的性能改进。一般而言，SOI芯片包括半导体元件层(semiconductor device layer)、衬底层(base layer)及诸如埋入氧化物或BOX层的绝缘层，其中绝缘层物理地分离并电性隔离半导体元件层与衬底层。电路元件如晶体管等则是被制作在半导体元件层中。
在采用SOI技术制造的半导体元件中，有时需要在芯片的背面加工(背侧制作工艺)，以进一步制作出其它的电路元件，例如，电感或电容等被动元件。因此，有需要在芯片中形成能够电连接至芯片背面的导电接触结构(body contact)。然而，现有技术为了保护制作导电接触结构过程中不受蚀刻剂如四甲基氢氧化铵(TMAH)的侵蚀，需另以绝缘衬层保护导电接触结构，此作法的缺点在于导电接触结构会产生明显的感应电荷效应。
发明内容
本发明的主要目的在于提供一种改良的半导体元件及其制作方法，可以解决上述现有技术的不足与缺点。
为达上述目的，本发明提供一种半导体元件，包含：一基材，具有一前侧面与一背侧面，其中基材包含一半导体层以及一埋入绝缘层；至少一晶体管，设于半导体层上；一层间介电层，设于前侧面，覆盖晶体管；一接触结构，贯穿层间介电层、半导体层及埋入绝缘层；一硅化金属层，在背侧面上覆盖住接触结构的一端面；及一被动元件，设于基材的背侧面上，其中接触结构电连接至被动元件。
根据本发明一实施例，接触结构包含一导电衬层及一金属层，其中该金属层被该导电衬层包围住。
根据本发明一实施例，其中导电衬层直接接触半导体层。
根据本发明一实施例，其中硅化金属层包含硅化镍、硅化钴或硅化钨。
根据本发明一实施例，其中被动元件包含一电感、一电容或一电阻。
根据本发明一实施例，其中硅化金属层直接接触被动元件的一接触垫。
根据本发明一实施例，其中背侧面上另包含一第一介电层及一第二介电层，其中接触垫设于第一介电层中，被动元件设于第二介电层中。
本发明另提供一种制作半导体元件的方法。首先提供一硅覆绝缘晶片，具有一前侧面与一背侧面，其中硅覆绝缘晶片包含一半导体层、一埋入绝缘层及一衬底层。再于半导体层上形成至少一晶体管。再于前侧面上形成一层间介电层，使其覆盖晶体管。接着形成一贯穿层间介电层、半导体层及埋入绝缘层的接触洞，其中接触洞的底部显露出部分衬底层。再于接触洞的底部所显露出的部分衬底层上形成一硅化金属层。再将接触洞以一导电材料填满，如此形成一接触结构。再于背侧面上形成一被动元件，其中接触结构电连接至被动元件。
为让本发明的上述目的、特征及优点能更明显易懂，下文特举优选实施方式，并配合所附的附图，作详细说明如下。然而如下的优选实施方式与附图仅供参考与说明用，并非用来对本发明加以限制者。
附图说明
图1至图14为依据本发明一实施例所绘示的一种半导体元件的制作方法的剖面示意图，其中图14显示出本发明的半导体元件剖面结构。
主要元件符号说明
100 硅覆绝缘晶片(基材)
100a 前侧面
100b 背侧面
101 半导体层
102 埋入绝缘层
103 衬底层
110 晶体管
111 栅极
112 栅极介电层
113 源极掺杂区
114 漏极掺杂区
115 间隙壁
121 蚀刻停止层
122 层间介电层
125、126、127、128 接触洞
125a 底部
131 金属层
132 硅化金属层
140 导电材料
141 导电衬层
142 金属层
145、146、147、148 接触结构
151 阻障氧化层
160 导电材料
161 导电衬层
162 金属层
170 金属层间介电层
171 钝化层(保护层)
180 金属内连线结构
200 元件晶片
201 临时基板
301 第一介电层
302 第二介电层
312 接触垫
320 被动元件
306 钝化层(保护层)
具体实施方式
在下文中，将参照附图说明细节，该些附图中的内容也构成说明书细节描述的一部分，并且以可实行该实施例的特例描述方式来绘示。下文实施例已描述足够的细节使该领域的一般技术人士得以具以实施。
当然，也可采行其他的实施例，或是在不悖离文中所述实施例的前提下作出任何结构性、逻辑性、及电性上的改变。因此，下文的细节描述不应被视为是限制，反之，其中所包含的实施例将由随附的权利要求来加以界定。
本发明公开一种硅覆绝缘(silicon-on-insulator，SOI)半导体元件及其制作方法。所述SOI半导体元件，例如，可以被应用在射频(RF)元件技术领域，但不限于此。
请参阅图1至图14，其为依据本发明一实施例所绘示的一种半导体元件的制作方法的剖面示意图。如图1所示，提供一硅覆绝缘晶片(或基材)100，具有一前侧面100a与一背侧面100b，其中硅覆绝缘晶片包含一半导体层101、一埋入绝缘层102及一衬底层103。埋入绝缘层102物理地分离并电性隔离半导体层101与衬底层103。
根据本发明一实施例，半导体层101可以包括硅，例如单晶硅，埋入绝缘层102可以包括二氧化硅，衬底层103可以包括硅，但不限于此。
接着，在半导体层101上形成至少一晶体管110。需理解的是，半导体层101上可以形成有多个晶体管或其他电子元件，为简化说明，图中仅一单一个晶体管110例示。根据本发明一实施例，晶体管110可以包含一栅极111、一栅极介电层112设于栅极111与半导体层101之间、一源极掺杂区113，及一漏极掺杂区114。在栅极111的侧壁上可以形成一间隙壁115。
接着，在前侧面100a的半导体层101上及晶体管110上依序形成一蚀刻停止层121及一层间介电层122。根据本发明一实施例，蚀刻停止层121可以是氮化硅层，但不限于此。根据本发明一实施例，层间介电层122可以是二氧化硅层，但不限于此。
如图2所示，接着形成一贯穿层间介电层122、蚀刻停止层121、半导体层101及埋入绝缘层102的接触洞125，其中接触洞125的底部125a显露出部分的衬底层103。
如图3至图5所示，接着进行一硅化金属制作工艺。先在前侧面100a的层间介电层122上及接触洞125的内表面上形成一金属层131(图3)，例如，镍、钴或钨等。接着，进行一快速热退火(RTP)制作工艺，在接触洞125的底部125a所显露出的部分的衬底层103上形成一硅化金属层132(图4)。根据本发明一实施例，硅化金属层132可以包含硅化镍、硅化钴或硅化钨，但不限于此。接着，将未反应的剩余金属层131去除，在接触洞125的底部125a留下硅化金属层132(图5)。
如图6所示，再将接触洞125以一导电材料140填满，例如，导电材料140可以包括一导电衬层141及一金属层142，其中在接触洞125内金属层142被导电衬层141包围住。根据本发明一实施例，例如，金属层142为一钨金属层。导电衬层141直接接触半导体层101。
如图7所示，接着进行一钨金属化学机械研磨制作工艺，将层间介电层122上的多余导电材料140研磨去除，如此在接触洞125内形成一接触结构145。
如图8所示，在完成前述钨金属化学机械研磨制作工艺之后，接着在层间介电层122上及接触结构145的表面上形成一阻障氧化层151。
如图9所示，接着在阻障氧化层151、层间介电层122及蚀刻停止层121中以蚀刻方法形成晶体管110上的接触洞126、127及128，其中接触洞126连通栅极111，接触洞127连通源极掺杂区113，接触洞128连通漏极掺杂区114。再将接触洞126、127及128以一导电材料160填满，例如，导电材料160可以包括一导电衬层161及一金属层162。根据本发明一实施例，例如，金属层162为一钨金属层。
如图10所示，接着进行一钨金属化学机械研磨制作工艺，将层间介电层122上的多余导电材料160及阻障氧化层151研磨去除，如此形成分别电连接栅极111、源极掺杂区113、漏极掺杂区114的接触结构146、147、148。
如图11所示，接着在层间介电层122上及接触结构145、146、147、148上形成金属层间介电层(inter-metal dielectric layer)170以及金属内连线结构180。其中金属层间介电层170可以包含多层介电材料或绝缘层，而金属内连线结构180可以分别形成在所述多层介电材料或绝缘层中。此前侧面100a上的金属化制作工艺为周知技艺，故其细节不另赘述。接着，可以在金属层间介电层170上形成一钝化层(或保护层)171。此时，即完成前侧面100a上的制作工艺步骤，形成一元件晶片200。
如图12所示，接着将一临时基板201接合至层间介电层122上的钝化层171上。为方便说明后续于背侧面上进行的制作工艺步骤，图12中与图11中的元件晶片200上、下反转，此时临时基板201在最下方，而衬底层103在最上方。
如图13所示，在完成临时基板201的接合步骤后，接着薄化衬底层103，直到硅化金属层132被显露出来。根据本发明一实施例，薄化衬底层103的作法可以利用研磨或蚀刻等方式，但不限于此。根据本发明一实施例，衬底层103可以被完全研磨去除，显露出埋入绝缘层102，但不限于此。
如图14所示，接着于背侧面100b的埋入绝缘层102上形成一第一介电层301。接着，在第一介电层301上形成一接触垫312，其中接触垫312直接接触硅化金属层132。根据本发明一实施例，接触垫312可以包含铜，但不限于此。接触垫312可以是利用铜镶嵌制作工艺形成。
接着，在第一介电层301上形成一第二介电层302。此外，另于背侧面100b上的第二介电层302中形成一被动元件320，其中被动元件320包含一电感、一电容或一电阻。第二介电层302可以包含多层介电材料或绝缘层，而被动元件320可以分层形成在所述多层介电材料或绝缘层中。此背侧面100b上的被动元件制作工艺为周知技艺，故其细节不另赘述。
根据本发明一实施例，接触结构144电连接至被动元件320，其中被动元件320经由接触垫312及硅化金属层132电连接至接触结构144。最后再于第二介电层302上形成一钝化层(或保护层)306。最后，可以将临时基板201去除，即完成本发明制作半导体元件的方法。
从图14中可看出本发明的半导体元件，包含：一基材100，具有一前侧面100a与一背侧面100b，其中基材100包含一半导体层101以及一埋入绝缘层102；至少一晶体管110，设于半导体层101上；一层间介电层122，设于前侧面100a，覆盖晶体管110；一接触结构145，贯穿层间介电层122、半导体层101及埋入绝缘层102；一硅化金属层132，于背侧面100b上覆盖住接触结构145的一端面；及一被动元件320，设于基材100的背侧面100b上，其中接触结构145电连接至被动元件320。
根据本发明一实施例，接触结构145包含一导电衬层141及一金属层142，其中金属层142被导电衬层141包围住。
根据本发明一实施例，其中导电衬层141直接接触半导体层101。
根据本发明一实施例，其中硅化金属层132包含硅化镍、硅化钴或硅化钨。
根据本发明一实施例，其中被动元件320包含一电感、一电容或一电阻。
根据本发明一实施例，其中硅化金属层132直接接触被动元件320的一接触垫312。
根据本发明一实施例，其中背侧面100b上另包含一第一介电层301及一第二介电层302，其中接触垫312设于第一介电层301中，被动元件320设于第二介电层302中。
以上所述仅为本发明的优选实施例，凡依本发明权利要求所做的均等变化与修饰，都应属本发明的涵盖范围。

Claims (14)

1.一种半导体元件，包含：
基材，具有一前侧面与一背侧面，其中该基材包含半导体层以及埋入绝缘层；
至少一晶体管，设于该半导体层上；
层间介电层，设于该前侧面，覆盖该至少一晶体管；
接触结构，贯穿该层间介电层、该半导体层及该埋入绝缘层；
硅化金属层，在该背侧面上覆盖住该接触结构的一端面；及
被动元件，设于该基材的该背侧面上，其中该接触结构电连接至该被动元件。
2.如权利要求1所述的半导体元件，其中该接触结构包含导电衬层及金属层，其中该金属层被该导电衬层包围住。
3.如权利要求2所述的半导体元件，其中该导电衬层直接接触该半导体层。
4.如权利要求1所述的半导体元件，其中该硅化金属层包含硅化镍、硅化钴或硅化钨。
5.如权利要求1所述的半导体元件，其中该被动元件包含电感、电容或电阻。
6.如权利要求1所述的半导体元件，其中该硅化金属层直接接触该被动元件的一接触垫。
7.如权利要求1所述的半导体元件，其中该背侧面上另包含第一介电层及第二介电层，其中该接触垫设于该第一介电层中，该被动元件设于该第二介电层中。
8.一种制作半导体元件的方法，包含：
提供一硅覆绝缘晶片，具有一前侧面与一背侧面，其中该硅覆绝缘晶片包含半导体层、埋入绝缘层及衬底层；
在该半导体层上形成至少一晶体管；
在该前侧面上形成一层间介电层，使其覆盖该至少一晶体管；
形成一贯穿该层间介电层、该半导体层及该埋入绝缘层的接触洞，其中该接触洞的底部显露出部分该衬底层；
在该接触洞的底部所显露出的部分该衬底层上形成一硅化金属层；
将该接触洞以一导电材料填满，如此形成一接触结构；及
在该背侧面上形成一被动元件，其中该接触结构电连接至该被动元件。
9.如权利要求8所述的制作半导体元件的方法，其中另包含：
在该层间介电层上接合一临时基板；及
薄化该衬底层，直到该硅化金属层被显露出来。
10.如权利要求9所述的制作半导体元件的方法，其中另包含：
在该背侧面上形成一第一介电层；
在该第一介电层中形成一接触垫，其中该接触垫直接接触该硅化金属层；
在该第一介电层上形成一第二介电层；及
在该第二介电层上形成一钝化层，其中该被动元件经由该接触垫及该硅化金属层电连接至该接触结构。
11.如权利要求10所述的制作半导体元件的方法，其中该被动元件包含电感、电容或电阻。
12.如权利要求8所述的制作半导体元件的方法，其中该接触结构包含导电衬层及金属层，其中该金属层被该导电衬层包围住。
13.如权利要求12所述的制作半导体元件的方法，其中该导电衬层直接接触该半导体层。
14.如权利要求8所述的制作半导体元件的方法，其中该硅化金属层包含硅化镍、硅化钴或硅化钨。
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CN105023908A (zh) * 2014-04-30 2015-11-04 台湾积体电路制造股份有限公司 复合接触插塞结构及其制造方法
CN106504985A (zh) * 2015-09-04 2017-03-15 爱思开海力士有限公司 半导体结构及其制造方法

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