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CN109376853A - Echo State Networks export aixs cylinder circuit - Google Patents

Echo State Networks export aixs cylinder circuit Download PDF

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Publication number
CN109376853A
CN109376853A CN201811255479.8A CN201811255479A CN109376853A CN 109376853 A CN109376853 A CN 109376853A CN 201811255479 A CN201811255479 A CN 201811255479A CN 109376853 A CN109376853 A CN 109376853A
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value
control module
termination
matrix
buffer
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CN109376853B (en
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廖永波
李红梅
李文昌
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University of Electronic Science and Technology of China
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University of Electronic Science and Technology of China
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    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/06—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
    • G06N3/063—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means

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Abstract

Echo State Networks export aixs cylinder circuit, are related to nerual network technique.The present invention includes: clock signal input terminal, X vector registor, first counter, first control module, second control module, first multiplier, enable signal generator, inverse matrix operation device, B matrix buffer, Y-direction amount register, the second counter, third control module, 4th control module, second multiplier, matrix multiplier, first control module, the second control module, third control module, the 4th control module are used to extract serial number and its identical element of control terminal input value from the vector registor connecting with its input terminal.Using technology of the invention, the calculating of position power is to propose that the mode of circuit calculates based on patent, input data, computing unit, memory length and operational capability determine in the circuit, so the position weight obtained by the circuit computing directly matches with hardware neural network, solves the unmatched risk of software and hardware.

Description

Echo State Networks export aixs cylinder circuit
Technical field
The present invention relates to nerual network techniques.
Background technique
Echo state network framework is described as Fig. 1, round expression storage unit in figure, rectangular representation module.Outside per moment Portion inputs teacher signal to (u1~uL, y1~yM), and teacher signal is vector, is stored in U cell and Y unit, random number hair respectively Raw device module generates input weight matrix, reservoir weight matrix and feedback weight matrix at random, respectively deposit Win unit, W unit, Wback unit, for subsequent calls.Reservoir module calculates middle layer state value x1~xK of network and is stored in X Unit.Training module carries out the calculating of output weight and is sent into Wout unit.Yy1~yyM indicates network reality output vector.
In the prior art, power validation testing in general position is calculated by application of the CPU or GPU to confirmation, so Afterwards in the position weight write-in hardware neural network calculated, this method can configure position power by hardware neural network and be deposited The floating-point operation bit length of storage space length and hardware is limited, and has the unmatched risk of interface between software and hardware.
Summary of the invention
The technical problem to be solved by the invention is to provide the Echo State Networks outputs that a kind of hardware mode is realized Aixs cylinder circuit has the characteristics that high reliability and efficient.
The present invention solve the technical problem the technical solution adopted is that, Echo State Networks export aixs cylinder circuit, It is characterised in that it includes following units:
Clock signal input terminal, for receiving clock signal；
X vector registor, for storing the X vector that dimension is K；
First counter, input terminal connect clock signal input terminal, and the first counter has i value output end and j value defeated Outlet exports i value and j value when for receiving clock trigger signal；
The i value initial value is 1, and using K value as a cycle, i value with each clock trigger signal circulation increase 1 until J=K；
The j value initial value is 1, and j value increases 1 until j=K when i value is equal to K each time；
First control module, input termination X vector registor, control termination i value output end, output termination first Buffer；
Second control module, input termination X vector registor, control termination j value output end, output termination second Buffer；
First multiplier, two input terminal connect the first buffer and the second buffer respectively, and output termination D matrix is slow Storage；
Enable signal generator is connect with i value output end and j value output end, and output termination inverse matrix operation device makes Energy end, for exporting enable signal to inverse matrix operation device in i=K and j=M；
Inverse matrix operation device, for making inversion operation to the matrix of D buffer storage when receiving enable signal；
B matrix buffer, connect with the output end of inverse matrix operation device, for storing the output of inverse matrix operation device；
Y-direction amount register, for storing the Y-direction amount that dimension is M；
Second counter, input terminal connect clock signal input terminal, and the second counter has h value output end and g value defeated Outlet；I value and j value are exported when for receiving clock trigger signal；
The h value initial value is 1, and using M value as a cycle, h value with each clock trigger signal circulation increase 1 until G=M；
The g value initial value is 1, and g value increases 1 until g=K when h value is equal to M each time；
Third control module, input termination X vector registor, control termination h value output end, output termination third Buffer；
4th control module, input termination Y-direction amount register, control termination g value output end, output termination the 4th Buffer；
Second multiplier, two input terminal connect third buffer and the 4th buffer respectively, and output termination a matrix is slow Storage；
Matrix multiplier, two input terminal connect B matrix buffer and A matrix buffer, output termination C matrix respectively Buffer；
First control module, the second control module, third control module, the 4th control module from it for inputting It holds and extracts serial number element identical with its control terminal input value in the vector registor of connection.
The clock trigger signal is rising edge clock.
Using technology of the invention, the calculating of position power is to propose that the mode of circuit calculates based on patent, input data, meter It calculates unit, memory length and operational capability to determine in the circuit, so the position weight obtained by the circuit computing is straight It connects and matches with hardware neural network, solve the unmatched risk of software and hardware.
Detailed description of the invention
Fig. 1 is echo state network architecture diagram.
Fig. 2 is training module circuit structure diagram of the invention.
Specific embodiment
Referring to fig. 2.
In Fig. 2, the mark of each section and each section corresponding relationship of the present invention are as follows:
Counter 1 --- the first counter
Counter 2 --- the second counter
X --- X vector registor
Y --- Y-direction amount register
Control module 1 --- the first control module
Control module 2 --- the second control module
Control module 3 --- third control module
Control module 4 --- the 4th control module
Temp1 --- the first buffer
Temp2 --- the second buffer
Temp3 --- third buffer
Temp4 --- the 4th buffer
A --- A matrix buffer
B --- B matrix buffer
C --- C matrix buffer
D --- D matrix buffer
dij--- D matrix element register
ahg--- A matrix element register
The present invention provides a kind of hardware implementation modes of training module, specifically include:
Clock signal input terminal, for receiving clock signal；
X vector registor, for storing the X vector that dimension is K；
First counter, input terminal connect clock signal input terminal, and the first counter has i value output end and j value defeated Outlet exports i value and j value when for receiving clock trigger signal；
The i value initial value is 1, and using K value as a cycle, i value with each clock trigger signal circulation increase 1 until J=K；For example, initial value i=1, after receiving a rising edge clock, i increases 1... until i=K, receives a clock again later Rising edge, i value become initial value 1 from K, hand of a clock circular flow when being equivalent to, referred to as " circulation increases 1 ".
The j value initial value is 1, and j value increases 1 until j=K when i value is equal to K each time；
First control module, input termination X vector registor, control termination i value output end, output termination first Buffer；
Second control module, input termination X vector registor, control termination j value output end, output termination second Buffer；
First multiplier, two input terminal connect the first buffer and the second buffer respectively, and output end passes through D matrix Element register connects D matrix buffer；
Enable signal generator is connect with i value output end and j value output end, and output termination inverse matrix operation device makes Energy end, for exporting enable signal to inverse matrix operation device in i=K and j=M；
Inverse matrix operation device, for making inversion operation to the matrix of D buffer storage when receiving enable signal；
B matrix buffer, connect with the output end of inverse matrix operation device, for storing the output of inverse matrix operation device；
Y-direction amount register, for storing the Y-direction amount that dimension is M；
Second counter, input terminal connect clock signal input terminal, and the second counter has h value output end and g value defeated Outlet；I value and j value are exported when for receiving clock trigger signal；
The h value initial value is 1, and using M value as a cycle, h value with each clock trigger signal circulation increase 1 until G=M；
The g value initial value is 1, and g value increases 1 until g=K when h value is equal to M each time；
Third control module, input termination X vector registor, control termination h value output end, output termination third Buffer；
4th control module, input termination Y-direction amount register, control termination g value output end, output termination the 4th Buffer；
Second multiplier, two input terminal connect third buffer and the 4th buffer respectively, and output end passes through A matrix Element register connects A matrix buffer；
Matrix multiplier, two input terminal connect B matrix buffer and A matrix buffer, output termination C matrix respectively Buffer；
First control module, the second control module, third control module, the 4th control module from it for inputting It holds and extracts serial number element identical with its control terminal input value in the vector registor of connection.

Claims (2)

1. Echo State Networks export aixs cylinder circuit, which is characterized in that including following units:
Clock signal input terminal, for receiving clock signal；
X vector registor, for storing the X vector that dimension is K；
First counter, input terminal connect clock signal input terminal, and the first counter has i value output end and j value output end, I value and j value are exported when for receiving clock trigger signal；
The i value initial value is 1, and using K value as a cycle, and i value increases 1 until j=with each clock trigger signal circulation K；
The j value initial value is 1, and j value increases 1 until j=K when i value is equal to K each time；
First control module, input termination X vector registor, control termination i value output end, the first caching of output termination Device；
Second control module, input termination X vector registor, control termination j value output end, the second caching of output termination Device；
First multiplier, two input terminal connect the first buffer and the second buffer, output termination D matrix caching respectively Device；
Enable signal generator is connect with i value output end and j value output end, the enable end of output termination inverse matrix operation device, For exporting enable signal to inverse matrix operation device in i=K and j=M；
Inverse matrix operation device, for making inversion operation to the matrix of D buffer storage when receiving enable signal；
B matrix buffer, connect with the output end of inverse matrix operation device, for storing the output of inverse matrix operation device；
Y-direction amount register, for storing the Y-direction amount that dimension is M；
Second counter, input terminal connect clock signal input terminal, and the second counter has h value output end and g value output end； I value and j value are exported when for receiving clock trigger signal；
The h value initial value is 1, and using M value as a cycle, and h value increases 1 until g=with each clock trigger signal circulation M；
The g value initial value is 1, and when h value is equal to M each time, g value increases 1 until g=K；
Third control module, input termination X vector registor, control termination h value output end, output termination third caching Device；
4th control module, input termination Y-direction amount register, control termination g value output end, the 4th caching of output termination Device；
Second multiplier, two input terminal connect third buffer and the 4th buffer, output termination A matrix caching respectively Device；
Matrix multiplier, two input terminal connect B matrix buffer and A matrix buffer, output termination C matrix caching respectively Device；
First control module, the second control module, third control module, the 4th control module are used to connect from its input terminal Serial number element identical with its control terminal input value is extracted in the vector registor connect.
2. Echo State Networks as described in claim 1 export aixs cylinder circuit, which is characterized in that the clock triggering letter Number be rising edge clock.
CN201811255479.8A 2018-10-26 2018-10-26 Echo state neural network output axon circuit Active CN109376853B (en)

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