CN109358256A - The arrester on-line monitoring system of synchronized sampling is realized in RS485 communication - Google Patents
The arrester on-line monitoring system of synchronized sampling is realized in RS485 communication Download PDFInfo
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- CN109358256A CN109358256A CN201811565836.0A CN201811565836A CN109358256A CN 109358256 A CN109358256 A CN 109358256A CN 201811565836 A CN201811565836 A CN 201811565836A CN 109358256 A CN109358256 A CN 109358256A
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
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Abstract
The present invention provides the arrester on-line monitoring systems that synchronized sampling is realized in a kind of RS485 communication, including host and multiple slaves, slave is used to monitor the electric signal on multiple arresters respectively, host reads the data of each slave acquisition and carries out analytical calculation, obtain the relevant parameter of arrester, it is connected between host and each slave by RS485 interface, the connecting line of the RS485 interface serves not only as the communication wire between host and each slave, simultaneously, as the synchronous signal line between host and each slave, it is controlled for sampling time of the host to each slave, realize synchronized sampling, and, the synchronous sampling control when configuration of communication baud rate when as RS485 communication wire is to as RS485 synchronous signal line does not have an impact.System provided by the present invention had both realized the communication between slave, and had also realized the synchronized sampling between slave, and synchronous accuracy is high only by the way that RS485 all the way is arranged.
Description
Technical field
The present invention relates to communication applications technical fields, more specifically, being related to a kind of based on realization synchronization in RS485 communication
The arrester on-line monitoring system of sampling.
Background technique
Arrester on-line monitoring system, by a host and Duo Tai slave machine.Multiple arresters share a voltage letter
Number, in general, the voltage signal on host supervision arrester, monitor detects the electric current letter of multiple arresters as slave
Number.The little deviation of phase between voltage signal and current signal and between multiple current signals, to multiple major parameters
Calculated result is all affected, and then has a significant impact to the superiority and inferiority for the performance for judging arrester, so to voltage signal and more
Stringent synchronization is wanted in the monitoring of a current signal, that is, realizes the synchronized sampling of all voltage and current signals as far as possible.
Existing arrester, in the network that host and multiple detectors are made up of RS485, host and monitor data
Between communication use RS485 signal wire all the way.In addition there are also RS485 signals all the way, are individually used for host and control each monitor
Realize the synchronized sampling of monitor and host.
Such two-way RS485 signal wire, increases cable cost and human cost.And it is same using communication command control
It is all to just starting sampling after sample command analysis processing, and order analysis process can be hard due to each slave when step sampling
Part and software run part difference and cause the time deviation of synchronized sampling excessive.In addition, two-way RS485 signal wire means to lead
And must be there are two UART interface with the single-chip microcontroller in slave, the range of choice of single-chip microcontroller becomes smaller, and increased costs.
Summary of the invention
For above-mentioned defect existing in the prior art, the object of the present invention is to provide one kind based on real in RS485 communication
The arrester on-line monitoring system of existing synchronized sampling, can be realized each data acquisition unit synchronized sampling in system.
In order to achieve the above objectives, the technical solution adopted in the present invention is as follows:
The arrester on-line monitoring system of synchronized sampling, including host and multiple slaves are realized in a kind of RS485 communication, from
Machine is used to monitor the electric signal on multiple arresters respectively, and host reads the data of each slave acquisition and carries out analytical calculation, obtains
It to the relevant parameter of arrester, is connected between host and each slave by RS485 interface, the connecting line of the RS485 interface is not
Only as the communication wire between host and each slave, meanwhile, as the synchronous signal line between host and each slave, it is used for
Host controls the sampling time of each slave, realizes synchronized sampling, and, communication wave when as RS485 communication wire
The synchronous sampling control when configuration of special rate is to as RS485 synchronous signal line does not have an impact.
The data transmission line of host connects its external interrupt pin, and host sends synchronized sampling order, host to each slave
And then a data are sent, the start bit of the data occurs as synchronous sampling signal to trigger host external interrupt pin
It interrupts；The data receiver line of slave connects its external interrupt pin, after the synchronized sampling order that slave receives host sending,
The data for waiting receiving host to send, the start bit of the data is as synchronous sampling signal to trigger slave external interrupt pin
It interrupts.
Host starts sampling in external interrupt service routine, and slave starts sampling in external interrupt service routine.
The external interrupt priority of cpu controller in host is configured to the highest priority in its all interruption；Slave
In the external interrupt priority of cpu controller be configured to the highest priority in its all interruption.
The triggering of the interrupt signal in external interrupt pin in host is configured to trigger interruption from high to low；In slave
The triggering of interrupt signal in external interrupt pin is configured to trigger interruption from high to low.
Host is according to the numbers of a certain number of data of the parameter sampling being set in advance or certain time length；Slave is according to master
The number of a certain number of data of parameter sampling or certain time length to oneself is set in advance in machine.
Synchronized sampling order is the data of a byte.
Synchronized sampling order is the data of multiple bytes.
Host controls each slave by road RS485, so that host is to the sampling of voltage and each slave to electric current
Sampling realize synchronize, specifically include:
Host sends synchronized sampling warning order
When needing to synchronize sampling, host first sends sampling warning order, and transmission order aft engine will do necessary
Preparation, including allow external interrupt, interrupt identification is reset；
Slave receives sampling warning order
After slave receives sampling warning order, necessary preparation is done, including allow external interrupt, interrupt identification is clear
Zero；
Host sends sample command
After sample command is sent, host can generate external interrupt, can generate interrupt identification, trigger in external interrupt
Or starting sampling, and external interrupt is forbidden to generate again, until sending new sampling warning order again；
Slave receives sample command
After slave receives sample command, external interrupt is also produced, sampling is triggered or started in external interrupt, and
External interrupt is forbidden to generate again, until receiving the new sampling warning order of host transmission again；
Respective data are sent to host and carry out calculation processing by each slave.The method of the calculation processing is the normal of this field
Rule method, including the methods of Fourier's variation, convolutional calculation.
Slave includes voltage detector and multiple current detectors, for monitoring the voltage signal on multiple arresters respectively
And current signal.
Slave includes multiple current detectors, for monitoring the current signal on multiple arresters respectively, on arrester
Voltage signal is by host supervision.
Compared with prior art, the present invention have it is following the utility model has the advantages that
Arrester on-line monitoring system disclosed by the invention based on realization synchronized sampling in RS485 communication:
1, system only passes through setting RS485 all the way, has both realized the communication between slave, also realizes between slave
Synchronized sampling；
2, synchronized sampling is using the same signal position on communication data line, for example the start bit that data are sent is as synchronization
Signal, synchronous precision are more acurrate.
Detailed description of the invention
Upon reading the detailed description of non-limiting embodiments with reference to the following drawings, other feature of the invention,
Objects and advantages will become more apparent upon:
Fig. 1 is the system structure diagram of one embodiment of the invention；
Fig. 2 is hardware principle structural block diagram of the invention；
Fig. 3 is synchronized sampling process schematic of the present invention；
Fig. 4 is host main program flow chart of the present invention；
Fig. 5 is host external interrupt service routine flow chart of the present invention；
Fig. 6 is interrupt service routine flow chart outside slave of the present invention；
Fig. 7 is slave main program flow chart of the present invention.
Specific embodiment
The present invention is described in detail combined with specific embodiments below.Following embodiment will be helpful to the technology of this field
Personnel further understand the present invention, but the invention is not limited in any way.It should be pointed out that the ordinary skill of this field
For personnel, without departing from the inventive concept of the premise, several changes and improvements can also be made.These belong to the present invention
Protection scope.
The present invention provides the arrester on-line monitoring system that synchronized sampling is realized in a kind of RS485 communication, as shown in Figure 1,
Including host and multiple slaves.Slave includes voltage detector and multiple current detectors.Voltage detector is lightning-arrest for monitoring
The voltage signal of device, current detector is for monitoring the current signal flowed through on arrester.The data sampling and electricity of voltage signal
The synchronization signal flowed between the data sampling of signal is completed by the RS485 signal wire between host and slave.Have inside host
Host CPU, host CPU have UART interface, and UART interface is converted to RS485 connection by RS485 chip.Have inside each slave from
CPU has UART interface from CPU, and UART interface is converted to RS485 connection by RS485 chip；Pass through between host and slave
The connection of RS485 line, realizes communication.The data transmission line of host CPU is also connected with an interrupt signal line of host CPU, from the data of CPU
It receives line and also connects an interrupt signal line from CPU；When synchronized sampling, synchronization signal is generated in the data transmission line of host CPU,
It host CPU and is interrupted simultaneously from CPU, and starts respective ADC sampling simultaneously, and then realize the synchronized sampling of host and slave.
After sampling, the data that host reads each slave are calculated, and obtain the relevant parameter of arrester.
The principle of UART communication:
UART, which sends data, to be sent according to position, is sent one 8 data and generally to be sent 10 positions, wherein further including
There are start bit and stop position, specific data transmission sequence is: start bit, 8 data bit, stop positions.UART sends signal and exists
It is high level when not sending data, and start bit when sending data is low level, this in UART communication process can be used
A start bit is as synchronization signal.According to this synchronization signal, needs host CPU and from CPU while starting respective sampled signal.
The synchronous of hardware signal is realized:
It realizes synchronized sampling, is realized on hardware by signal wire.The hardware connection structure of host and slave such as Fig. 2
It is shown.Host and slave are communicated by RS485 in system, and the interface that RS485 chip is connected with CPU is UART interface.Communication
In the process, the signal that the transmission data line TXD_M of host CPU and the reception data line RXD_S from CPU are generated is identical and synchronous,
This signal wire can be used as synchronous signal line.
One embodiment of the invention, host CPU use STM32F103VCT6 chip, system clock frequency: 72MHz clock, from
CPU uses STM32F103C8T6 chip, and the configuration of system frequency and timer is identical with host CPU.
The configuration of UART interface:
UART is communicated for connecting RS485 chip.Host CPU meets RS485 using UART1, configures baud rate 115200,
8 data bit, 1 stop position, no parity.UART3 connection RS485 chip is used from CPU, configures baud rate 115200,8
Position data bit, 1 stop position, no parity.
The configuration and interrupt processing of external interrupt:
Host CPU external interrupt uses PC0 pin, connects the transmission signal wire TX of UART.Failing edge triggering is configured to interrupt.
PA2 pin is used from CPU external interrupt, connects the reception signal wire RX of UART.Failing edge triggering is configured to interrupt.Master and slave CPU
Outer interruption can be carried out the setting forbidden and allowed, that is, forbid interrupt generate and allow interrupt generate.
Start sampling in interruption.
Specific implementation process, as shown in figure 3, including the following:
Host sends warning order: when needing to synchronize sampling, host first sends synchronized sampling warning order.It sends
Order aft engine will do necessary preparation, and specially permission external interrupt, interrupt identification are reset.
After slave receives warning order, same preparation is done, allows external interrupt, interrupt identification is reset.
Host sends synchronized sampling order: when synch command is sent, host can generate external interrupt, in interrupt routine
Middle starting sampling, juxtaposition interrupt identification.
Slave generates external interrupt simultaneously, starts sampling, juxtaposition interrupt identification in interrupt routine.
Host sends synchronous warning order data packet, 16 binary data packets: " 55 AA, 31 54 49 4D, 45 0D 0A "
Host sends synchronously sampled data packet, 16 binary data packets: " 55 AA 32 "
Workflow:
Host main program flow chart, as shown in Figure 4.Host main flow is host during synchronized sampling, quasi- from initiating
Standby sampling samples the program execution flow of end to the end.
Host external interrupt program, as shown in Figure 5.
Slave main program flow chart, as shown in Figure 6.Slave main flow be slave in the process of running, from receive prepare
The program execution flow that sample command is completed to sampling processing.
Interrupt service routine outside slave: as shown in Figure 7.
Specific embodiments of the present invention are described above.It is to be appreciated that the invention is not limited to above-mentioned
Particular implementation, those skilled in the art can make a variety of changes or modify within the scope of the claims, this not shadow
Ring substantive content of the invention.In the absence of conflict, the feature in embodiments herein and embodiment can any phase
Mutually combination.
Claims (10)
1. realizing the arrester on-line monitoring system of synchronized sampling in a kind of RS485 communication, which is characterized in that including host and more
A slave, slave are used to monitor the electric signal on multiple arresters respectively, and host reads the data of each slave acquisition and divided
Analysis calculates, and obtains the relevant parameter of arrester, is connected between host and each slave by RS485 interface, RS485 interface connecting line
The communication wire between host and each slave is served not only as, meanwhile, as the synchronous signal line between host and each slave, use
It is controlled in sampling time of the host to each slave, realizes synchronized sampling, and, communication when as RS485 communication wire
The synchronous sampling control when configuration of baud rate is to as RS485 synchronous signal line does not have an impact.
2. realizing the arrester on-line monitoring system of synchronized sampling in RS485 communication according to claim 1, feature exists
In the data transmission line of host connects its external interrupt pin, and host sends synchronized sampling order to each slave, and host is and then
A data are sent, the start bit of the data is interrupted as synchronous sampling signal to trigger host external interrupt pin；
The data receiver line of slave connects its external interrupt pin, after the synchronized sampling order that slave receives host sending, waits
The start bit of the data that receiving host is sent, the data occurs as synchronous sampling signal to trigger slave external interrupt pin
It interrupts.
3. realizing the arrester on-line monitoring system of synchronized sampling in RS485 communication according to claim 2, feature exists
In the external interrupt priority of the cpu controller in host and slave processors is each configured to the highest priority in its all interruption.
4. realizing the arrester on-line monitoring system of synchronized sampling in RS485 communication according to claim 2, feature exists
In the triggering of the interrupt signal in external interrupt pin in host and slave processors is each configured to trigger interruption from high to low.
5. realizing the arrester on-line monitoring system of synchronized sampling in RS485 communication according to claim 2, feature exists
In, host according to the number of a certain number of data of the parameter sampling being set in advance or certain time length；Slave is mentioned according to host
Preceding setting is to a certain number of data of parameter sampling of slave or the number of certain time length.
6. realizing the arrester on-line monitoring system of synchronized sampling in RS485 communication according to claim 2, feature exists
In synchronized sampling order is the data of a byte.
7. realizing the arrester on-line monitoring system of synchronized sampling in RS485 communication according to claim 2, feature exists
In synchronized sampling order is the data of multiple bytes.
8. realizing the arrester on-line monitoring system of synchronized sampling in RS485 communication according to claim 2, feature exists
In, host realizes the synchronous of each slave signal sampling, it specifically includes:
Host sends synchronized sampling warning order
When needing to synchronize sampling, host first sends sampling warning order, and necessary preparation will be done by sending order aft engine
Work, including allow external interrupt, interrupt identification is reset；
Slave receives sampling warning order
After slave receives sampling warning order, necessary preparation is done, including allow external interrupt, interrupt identification is reset；
Host sends sample command
After sample command is sent, host can generate external interrupt, can generate interrupt identification, trigger or open in external interrupt
Dynamic sampling, and external interrupt is forbidden to generate again, until sending new sampling warning order again；
Slave receives sample command
After slave receives sample command, external interrupt is also produced, triggered in external interrupt or starts sampling, and is forbidden
External interrupt generates again, until receiving the new sampling warning order of host transmission again；
Respective data are sent to host and carry out calculation processing by each slave.
9. realizing the arrester on-line monitoring system of synchronized sampling in RS485 communication according to claim 1, feature exists
In slave includes voltage detector and multiple current detectors, for monitoring voltage signal and electricity on multiple arresters respectively
Flow signal.
10. realizing the arrester on-line monitoring system of synchronized sampling, feature in RS485 communication according to claim 1
It is, slave includes multiple current detectors, the voltage for monitoring the current signal on multiple arresters respectively, on arrester
Signal is by host supervision.
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| CN114401182A (en) * | 2022-01-06 | 2022-04-26 | 浙江南都能源互联网有限公司 | RS485 power station based main and standby communication method and system |
| CN114443551A (en) * | 2021-12-25 | 2022-05-06 | 苏州浪潮智能科技有限公司 | Method, system, equipment and medium for realizing I2C communication by single line |
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