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CN109309123B - 半导体元件及其制作方法 - Google Patents

半导体元件及其制作方法 Download PDF

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CN109309123B
CN109309123B CN201710628502.2A CN201710628502A CN109309123B CN 109309123 B CN109309123 B CN 109309123B CN 201710628502 A CN201710628502 A CN 201710628502A CN 109309123 B CN109309123 B CN 109309123B
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dielectric layer
gate dielectric
active region
trench
gate
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CN109309123A (zh
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吕佐文
吴劲苇
詹电针
林哲平
詹书俨
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Fujian Jinhua Integrated Circuit Co Ltd
United Microelectronics Corp
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Fujian Jinhua Integrated Circuit Co Ltd
United Microelectronics Corp
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Abstract

本发明公开一种半导体元件及其制作方法。该半导体元件包含有一半导体衬底，具有一栅极沟槽，穿过主动区域及围绕主动区域的一沟槽绝缘区域，其中栅极沟槽显露出主动区域的侧壁及沟槽绝缘结构的侧壁，其中沟槽绝缘结构包含一孔隙；一第一栅极介电层，共形的覆盖住主动区域的侧壁及沟槽绝缘区域的侧壁，其中孔隙被第一栅极介电层填满；一第二栅极介电层，从主动区域的侧壁上生长出来；及一栅极，设于栅极沟槽中。

Description

半导体元件及其制作方法
技术领域
本发明涉及半导体技术领域，特别是涉及一种半导体元件及其制作方法。
背景技术
由于电子元件如动态随机存取存储器元件的尺寸越来越小，用来隔离半导体元件沟槽绝缘区域内可能会形成孔隙，后续在栅极沟槽填入栅极材料时，如氮化钛，则会沿着此孔隙形成氮化钛突出(TiN excursion)现象，导致字符线与字符线串扰(WL-WL crosstalk)问题。
本发明于是提出一种改良的半导体元件及其制作方法，可以解决上述现有技术的问题与不足。
发明内容
本发明的主要目的在于提供一种改良的半导体元件，可以改善栅极介电层品质，并改善现有技术的缺点。
本发明一实施例公开一种半导体元件，包含有一半导体衬底，具有一栅极沟槽，穿过一主动区域及围绕所述主动区域的一沟槽绝缘区域，其中所述栅极沟槽显露出所述主动区域的一侧壁及所述沟槽绝缘结构的一侧壁，其中所述沟槽绝缘结构包含一孔隙；一第一栅极介电层，共形的覆盖住所述主动区域的侧壁及所述沟槽绝缘区域的侧壁，其中所述孔隙被所述第一栅极介电层填满；一第二栅极介电层，从所述主动区域的侧壁上生长出来；及一栅极，设于所述栅极沟槽中。
根据本发明另一实施例公开一种半导体元件的制作方法。先提供一半导体衬底，其上具有一主动区域及围绕所述主动区域的一沟槽绝缘区域。再于所述半导体衬底中形成一栅极沟槽，穿过所述主动区域及所述沟槽绝缘区域，其中所述栅极沟槽显露出所述主动区域的一侧壁及所述沟槽绝缘区域的一侧壁，其中所述沟槽绝缘区域包含一孔隙。再于所述栅极沟槽的内壁上沉积一第一栅极介电层，其中所述第一栅极介电层，共形的覆盖住所述主动区域的侧壁及所述沟槽绝缘区域的侧壁，且所述孔隙被所述第一栅极介电层填满。再进行一临场蒸气产生(ISSG)制作工艺，在所述主动区域的侧壁上，热生长出一第二栅极介电层。
为让本发明上述目的、特征及优点能更明显易懂，下文特举优选实施方式，并配合所附的附图，作详细说明如下。然而优选实施方式与附图仅供参考与说明用，并非用来对本发明加以限制者。
附图说明
图1至图6为本发明一实施例所绘示的制作半导体元件的方法，其中:
图1例示本发明一实施例半导体元件的部分布局上视图；
图2为沿着图1中切线I-I’的剖面示意图；
图3为一立体透视图，例示图1中沿着一栅极沟槽中所看到的沟槽绝缘区域的孔隙；及
图4至图6则是在不同阶段沿着图1中切线I-I’的剖面示意图。
主要元件符号说明
1 半导体元件
10 半导体衬底
101 主动区域
101a 侧壁
102 沟槽绝缘区域
102a 侧壁
102b 孔隙
112 绝缘层
121～124 栅极沟槽
130 第一栅极介电层
140 第二栅极介电层
150 栅极
具体实施方式
接下来的详细叙述是参照相关附图所示内容，用来说明可依据本发明具体实行的实施例。这些实施例已提供足够的细节，可使本领域技术人员充分了解并具体实行本发明。在不悖离本发明的范围内，仍可做结构或电性上的修改，并应用在其他实施例上。
因此，以下详细描述并非用来对本发明加以限制。本发明涵盖的范围由其权利要求界定。与本发明权利要求具均等意义者，也应属本发明涵盖的范围。
本发明有关于一种半导体集成电路结构，例如，动态随机存取存储器结构，形成在栅极沟槽内的栅极介电层结构包含一原子层沉积(atomic layer deposition，ALD)氧化层及一临场蒸气产生(in-situ steam generation，ISSG)氧化层，可以改善栅极介电层品质，并改善现有技术的缺点，例如，沟槽绝缘区域的孔隙产生的氮化钛突出现象，及字符线与字符线串扰(WL-WL cross talk)问题。
请参阅图1至图6，其为依据本发明一实施例所绘示的制作半导体元件1的方法。其中，图1例示本发明一实施例半导体元件1的部分布局上视图，图2为沿着图1中切线I-I’的剖面示意图，图3为一立体透视图，例示图1中沿着一栅极沟槽中所看到的沟槽绝缘区域的孔隙，图4至图6则是在不同阶段沿着图1中切线I-I’的剖面示意图。
首先，如图1至图3所示，提供一半导体衬底10，其上具有主动区域101及围绕所述主动区域101的沟槽绝缘区域102。图1中所示的布局结构可以是一存储器阵列区域，但不限于此。各主动区域101具有一长轴，沿着一参考a轴方向延伸。根据本发明一实施例，在各主动区域101中将形成凹入式栅极晶体管存取元件。
根据本发明一实施例，半导体衬底10可以是一硅基底，在沟槽绝缘区域102包括一绝缘层112，例如，二氧化硅层。
在形成沟槽绝缘区域102及主动区域101之后，接着于所述半导体衬底10中形成栅极沟槽121～124，穿过主动区域101及所述沟槽绝缘区域102，其中，栅极沟槽121～124是沿着参考y轴方向延伸。
如图3所示，以栅极沟槽122为例，栅极沟槽122显露出所述主动区域101的一侧壁101a及所述沟槽绝缘区域102的一侧壁102a，其中所述沟槽绝缘区域102包含一孔隙102b。
如前所述，沟槽绝缘区域102内的孔隙102b，后续在栅极沟槽121～124填入栅极材料时，如氮化钛，则会沿着此孔隙102b形成氮化钛突出(TiN excursion)现象，导致字符线与字符线串扰(WL-WL cross talk)问题。本发明是针对上述现有技术的问题与不足，提出一种改良的半导体元件及其制作方法。
如图4所示，在形成栅极沟槽121～124后，接着于所述栅极沟槽121～124的内壁上及半导体衬底10的上表面，全面的沉积一第一栅极介电层130，其中所述第一栅极介电层130，共形的覆盖住所述主动区域101的侧壁101a及所述沟槽绝缘区域102的侧壁102a，且所述孔隙102b被所述第一栅极介电层130填满。
根据本发明一实施例，所述第一栅极介电层130包含一原子层沉积(atomic layerdeposition，ALD)氧化层，是利用一原子层沉积(atomic layer deposition，ALD)法沉积而成的二氧化硅层。根据本发明一实施例，所述第一栅极介电层130的厚度介于40至60埃(angstrom)，例如50埃。
接着，如图5所示，进行一临场蒸气产生(ISSG)制作工艺，在所述栅极沟槽121～124内的所述主动区域101的侧壁101a上，热生长出一第二栅极介电层140。故所述第二栅极介电层140为一临场蒸气产生(in-situ steam generation，ISSG)氧化层。
根据本发明一实施例，所述临场蒸气产生制作工艺系在约1000℃的温度下，并且在含有氢气、氧气及氮气的环境中进行。根据本发明一实施例，于所述临场蒸气产生制作工艺，所述氢气的体积百分比为25％至40％(一般称为高蒸气(high-steam)条件)，例如，在氢气的体积百分比为33％的条件下进行。
根据本发明一实施例，于所述临场蒸气产生制作工艺，所述氢气的流量介于1至10标准升每分钟(slm)，所述氮气的流量小于10slm，氧气的流量介于2至10slm。
在前述通过氢气的体积百分比为33％的高蒸气(high-steam)条件下进行临场蒸气产生制作工艺，可以形成高品质的二氧化硅栅极介电层。此外，通过在所述临场蒸气产生制作工艺中通入氮气(流量小于10slm)，将浸透时间(soak time)延长，例如介于14至36秒之间，因而能提升栅极介电层的漏电流特性。
最后，如图6所示，在所述主动区域101的侧壁101a上，热生长出所述第二栅极介电层140后，再于所述栅极沟槽121～124形成一栅极150。根据本发明一实施例，栅极150可以包含一氮化钛层及一钨金属层。
以上所述仅为本发明之优选实施例，凡依本发明权利要求所做的均等变化与修饰，都应属本发明的涵盖范围。

Claims (11)

1.一种半导体元件，包含有:
半导体衬底，具有栅极沟槽，穿过一主动区域及围绕所述主动区域的一沟槽绝缘区域，其中所述栅极沟槽显露出所述主动区域的一侧壁及所述沟槽绝缘结构的一侧壁，其中所述沟槽绝缘结构包含一孔隙；
第一栅极介电层，共形的覆盖住所述主动区域的侧壁及所述沟槽绝缘区域的侧壁，其中所述孔隙被所述第一栅极介电层填满；
第二栅极介电层，从所述主动区域的侧壁上生长出来，其中所述第二栅极介电层与所述第一栅极介电层直接接触；及
栅极，设于所述栅极沟槽中。
2.如权利要求1所述的半导体元件，其中所述第一栅极介电层包含原子层沉积(atomiclayer deposition，ALD)氧化层。
3.如权利要求2所述的半导体元件，其中所述第一栅极介电层的厚度介于40至60埃(angstrom)。
4.如权利要求1所述的半导体元件，其中所述第二栅极介电层包含临场蒸气产生(in-situ steam generation，ISSG)氧化层。
5.一种半导体元件的制作方法，包含有:
提供一半导体衬底，其上具有一主动区域及围绕所述主动区域的一沟槽绝缘区域；
在所述半导体衬底中形成一栅极沟槽，穿过所述主动区域及所述沟槽绝缘区域，其中所述栅极沟槽显露出所述主动区域的一侧壁及所述沟槽绝缘区域的一侧壁，其中所述沟槽绝缘区域包含一孔隙；
在所述栅极沟槽的内壁上沉积一第一栅极介电层，其中所述第一栅极介电层，共形的覆盖住所述主动区域的侧壁及所述沟槽绝缘区域的侧壁，且所述孔隙被所述第一栅极介电层填满；
进行一临场蒸气产生(ISSG)制作工艺，在所述主动区域的侧壁上，热生长出一第二栅极介电层，其中所述第二栅极介电层与所述第一栅极介电层直接接触。
6.如权利要求5所述的半导体元件的制作方法，其中另包含:
在所述主动区域的侧壁上，热生长出所述第二栅极介电层后，再于所述栅极沟槽形成一栅极。
7.如权利要求5所述的半导体元件的制作方法，其中所述临场蒸气产生制作工艺是在1000℃的温度下，并且在含有氢气、氧气及氮气的环境中进行。
8.如权利要求7所述的半导体元件的制作方法，其中于所述临场蒸气产生制作工艺，所述氢气的体积百分比为25％至40％。
9.如权利要求7所述的半导体元件的制作方法，其中于所述临场蒸气产生制作工艺，所述氢气的流量介于1至10标准升每分钟(slm)。
10.如权利要求7所述的半导体元件的制作方法，其中于所述临场蒸气产生制作工艺，所述氮气的流量小于10标准升每分钟(slm)。
11.如权利要求7所述的半导体元件的制作方法，其中于所述临场蒸气产生制作工艺，所述氧气的流量介于2至10标准升每分钟(slm)。
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