CN109217869B

CN109217869B - PLL phase rotator system and method

Info

Publication number: CN109217869B
Application number: CN201710533639.XA
Authority: CN
Inventors: 雷恺; 李奕乐
Original assignee: Lattice Semiconductor Corp
Current assignee: Lattice Semiconductor Corp
Priority date: 2017-07-03
Filing date: 2017-07-03
Publication date: 2024-04-05
Anticipated expiration: 2037-07-03
Also published as: CN109217869A

Abstract

An integrated circuit may need a clock capable of generating a target phase and frequency. In one example, an apparatus includes an oscillator, a selection circuit, and a conversion circuit. The oscillator is operable to generate a plurality of clock signals in a first format, the plurality of clock signals having the same frequency and different phases. The selection circuit is operable to select an intermediate clock having a target phase based on the selection signal from the plurality of oscillation clocks. The conversion circuit may be operable to convert the selected intermediate clock to a target clock of the second format, the target clock having a target phase. The selection circuit and the conversion circuit may be formed in an integrated circuit, wherein the oscillator is external to the integrated circuit. Alternatively, the oscillator may be integrated with the selection circuit and the conversion circuit.

Description

PLL phase rotator system and method

Technical Field

The present disclosure relates generally to Phase Locked Loops (PLLs) and, in one or more particular aspects, to multi-phase clock generation using PLLs.

Background

Electronic devices such as mobile phones and tablet computers are continually designed with more functionality and even more integration, with less power consumption and longer battery time. These implementations are achieved by reducing power consumption in all aspects of the device including the integrated circuit that performs these types of functions. Voltage Controlled Oscillators (VCOs) are widely used in these electronic devices and more particularly in integrated circuits such as various silicon chips on these devices. VCOs are used in PLLs to provide for the use of various components for controlling and synchronizing such integrated circuits for synchronizing data transmissions and the like. Such integrated circuits, particularly Radio Frequency (RF) circuits, may require various clocks with different phases. There are many schemes to design VCOs with multiple phases. One of the conventional architectures uses a voltage-to-current converter (V2I) and a current controlled oscillator (ICO). However, these conventional schemes consume considerable power.

Disclosure of Invention

In one disclosed example embodiment, an apparatus is presented that includes an oscillator, a selection circuit, and a conversion circuit. The oscillator is operable to generate a plurality of clock signals in a first format, the plurality of clock signals having the same frequency and different phases. The selection circuit is operable to select an intermediate clock having a target phase based on the selection signal from the plurality of oscillation clocks. The conversion circuit may be operable to convert the selected intermediate clock to a target clock of the second format, the target clock having a target phase.

The summary is provided to introduce a selection of concepts in a simplified form that are further described below in the detailed description. This summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used to limit the scope of the claimed subject matter.

Drawings

The foregoing and other objects, features and advantages of the disclosure will be apparent from the following more particular descriptions of exemplary embodiments of the disclosure as illustrated in the accompanying drawings wherein like reference numbers generally represent like parts throughout the exemplary embodiments of the disclosure.

Fig. 1 shows a schematic architecture of a conventional phase rotator;

FIG. 2 shows an example of the selection of clocks with different phases from E2C in FIG. 1;

FIG. 3 illustrates a phase rotator according to one embodiment of the present disclosure;

FIG. 4 illustrates an example of clock combining for in-phase and quadrature clocks according to one embodiment of the present disclosure;

FIG. 5 shows an example of the selection circuit of FIG. 3;

FIG. 6 shows another example of the selection circuit of FIG. 3;

fig. 7 illustrates a PLL according to one embodiment of the disclosure; and

fig. 8 illustrates a method of selecting a target clock according to one embodiment of the present disclosure.

Detailed Description

The present disclosure will now be discussed with reference to several embodiments. It should be understood that these embodiments are discussed only in order to enable a person of ordinary skill in the art to better understand and thus practice the present disclosure, and are not meant to imply any limitation on the scope of the present disclosure.

As used herein, the term "comprising" and variants thereof are to be interpreted as meaning "including but not limited to" open-ended terms. The term "based on" is to be interpreted as "based at least in part on". The terms "embodiment" and "one embodiment" are to be interpreted as "at least one embodiment. The term "another embodiment" is to be interpreted as "at least one other embodiment". The terms "first," "second," and the like, may refer to different or the same object. The term "ECL" may refer to emitter-coupled logic, the term "CMOS" may refer to complementary metal oxide semiconductors, and the term "E2C" may refer to ECL to CMOS. Other explicit and implicit definitions are also possible below.

Some specific values or ranges of values may be referred to in the following description. It should be understood that these numerical values and numerical ranges are merely exemplary, which may be advantageous to put the concepts of the present disclosure into practice. However, the description of these examples is not intended to limit the scope of the present disclosure in any way. These values or ranges of values may be set otherwise, depending on the particular application and requirements.

As described above, VCOs may be widely used in integrated circuits and extended for electronic devices to provide clocks with different phases, and may consume a significant amount of power relative to an overall power consumption budget.

Fig. 1 shows a schematic architecture of a conventional phase rotator 100. The conventional phase rotator 100 may be used to generate in-phase and quadrature clocks for use in a PLL. As shown, the phase rotator 100 includes a VCO 101, an E2C circuit 108, and a MUX 100.VCO 101 includes a switch 102, a voltage-to-current converter (V2I) 104, and a current-controlled oscillation clock 106, and is operable to generate a voltage-controlled oscillation clock. V2I 104 is operable to convert the voltage signal received from switch 102 into a current signal proportional to the voltage signal. ICO 106 is operable to generate one or more clock signals based on the received current signal.

In fig. 1, n+1 clocks Clk < n:0> are generated. These use different phases with the same frequency and typically distributed evenly over 360 degrees, and these clocks are in the Current Mode Logic (CML) format. In embodiments herein, CML may be used interchangeably with ECL. CML format clocks cannot be used directly for CMOS chips and therefore need to be converted to CMOS format clocks. E2C 108 is a conventional circuit that can convert a clock in CML format to a clock in CMOS format. Although the embodiments herein are described with reference to conversion from CML format to CMOS format, this is by way of example only and is not limiting as to the scope of the present disclosure. In alternative embodiments, the conversion may be between various formats including Low Voltage Differential Signaling (LVDS), ECL, CML, transistor-transistor logic (TTL), and the like. For example, the conversion can be between ECL and TTL.

For some applications, such as Field Programmable Gate Arrays (FPGAs), graphics Processing Units (GPUs), and Microcontrollers (MCUs), customers need to tune the IQ phase of the output to meet timing requirements. In FIG. 1, E2C 108 is operable to convert n+1 clocks Clk < n:0> to CMOS formatted clocks Clk_c < n:0>. MUX 110 is operable to select an in-phase clock Clk_i and a quadrature clock Clk_q. The in-phase clock clk_i and the quadrature clock clk_q are 90 degrees out of phase from each other. Although fig. 1 shows a quadrature system that outputs clocks that differ in phase by 90 degrees from each other, it is understood that phase rotator 100 may output clocks with phase differences of other degrees.

Since there are "n+1" clocks, one coarse tuning method is to rotate the IQ phase of the output clock. For example, clk2 and Clk4 are initially rotated, while Clk5 and Clk7 are finally selected after tuning. By using this approach, the use of a large delay chain to tune the output clock can be avoided, which saves power and area and improves noise performance.

In one example, assume that n=7, E2C 108 converts 8 clocks in CML format to 8 clocks in CMOS format, as shown in fig. 2. Each clock is 45 degrees or more different than the other clocks. This conversion consumes a considerable amount of power. However, as shown in fig. 2, only 2 clocks are selected as the target clock, since only in-phase and quadrature clocks are required for most references such as wireless, clock Data Recovery (CDR), delay chain loop (DLL), and data path. This means that the other 6 clocks of the CMOS format and their conversion are wasted. Although n=7 is assumed in the present example, this is merely an example and is not intended to limit the scope of the present disclosure. In alternative embodiments, n may be 3, 15, or other odd numbers.

In contrast to the above, embodiments of the present disclosure provide a phase rotator consuming ultra-low power and a PLL including the same. By selecting the target clock before switching the clocks, only the target clock is switched. This approach avoids switching all clocks, and thus power for switching the desired clock can be saved.

Fig. 3 illustrates a phase rotator 200 according to one embodiment of the present disclosure. The phase rotator 200 includes a VCO 101, a selection circuit 210, and an E2C circuit 208.VCO 101 includes a switch 102, a voltage-to-current converter (V2I) 104, and a current-controlled oscillator 106, and VCO 101 is operable to generate a voltage-controlled oscillation clock. V2I 104 is operable to convert the voltage signal received from switch 102 into a current signal proportional to the voltage signal. The ICO 106 is operable to generate one or more oscillating clocks based on the received current signal.

In fig. 3, n+1 clocks Clk < n:0> in CML format are generated by the generating means 202. The generating means 202 comprises the ICO 106, the selection circuit 210 and the E2C 208 and is operable to generate a clock based on the current received from the V2I 104. The clock is variable based on characteristics including the current amplitude received from the V2I 104. n clocks are delivered to the selection circuit 210. The selection circuit 210 selects the in-phase clock clk_i_e and the quadrature clock clk_q_e of the CML format from n clocks as intermediate IQ clocks having a target phase based on the selection signal Sel < m:0>. Sel < m:0> represents m+1 kinds of selection signals used to select a target clock. In one example, sel < m:0> is intended to select any pair in the IQ clock while keeping clk_i_e ahead of clk_q_e by 90 degrees. E2C 208 receives the intermediate in-phase clock Clk_i_e and the quadrature clock Clk_q_e having the target phases from selection circuit 210 and is operable to convert the in-phase clock Clk_i_e and the quadrature clock Clk_q_e to the target clocks Clk_i and Clk_q, respectively, without changing the phases. The converted in-phase clock clk_i_e and quadrature clock clk_q_e are then applied to the CMOS circuit.

Fig. 4 illustrates an example of in-phase and quadrature clocks according to one embodiment of the present disclosure. In the example of n=7, there will be 8 clocks, each differing from the other by 45 degrees or multiples of 45 degrees. The numbers in fig. 4 represent clocks. For example, "0" means a first clock having a phase of 0 degrees, "1" means a second clock having a phase of 45 degrees. For systems where IQ clocks are desired, 8 combinations may be provided. For example, the first clock "0" may be output only together with the third clock "2" or the 7 th clock "6". Although 8 clocks with different phases are shown in fig. 4, this is merely an example and does not limit the scope of the present disclosure. In alternative embodiments, other amounts of clocks may be used, such as 16 clocks or 4 clocks.

Fig. 5 shows an example of the selection circuit 210 in fig. 3. The selection circuit 210 includes an in-phase switch group 212 and a quadrature switch group 214. Switch groups 212 and 214 may be formed of Metal Oxide (MOS) transistors. Although the switch in fig. 5 is shown as a MOS transistor, this is merely an example and does not limit the scope of the present disclosure. In alternative embodiments, bipolar transistors or other switches may be used.

Switch groups 212 and 214 each include 8 MOS transistors, each transistor receiving a respective clock from clocks Clk <0> -Clk <7 >. For example, MOS transistor 2121 in-phase switch group 212 receives clock 2122 Clk <0>, and MOS 2141 in quadrature switch group 214 receives clock 2142 Clk <2>. The gates of the MOS transistors are coupled to receive a select signal, such as Sel < m:0> in fig. 3, so that only one MOS transistor in the in-phase switch group 212 and only one MOS transistor in the quadrature switch group 214 are turned on at the same time. For example, the clock 2122 clk <0> and the clock 2142 clk <2> are output from the in-phase switch group 212 and the quadrature switch group 214 at the same timing as an intermediate clock having a target phase. Similar mechanisms apply to other clocks in the plurality of clocks Clk <0> -Clk <7> and corresponding MOS transistors in the in-phase switch group 212 and the quadrature switch group 214.

In the circuit configuration of fig. 5, one MOS transistor is used at each input to achieve signal multiplexing, which reduces ICO loading and improves ICO speed and phase noise. This approach is feasible due to the fact that adjacent clocks cannot be selected as IQ clocks when n > =7.

Fig. 6 shows another example of the selection circuit 210 in fig. 3. The selection circuit 210 includes a switch network group 216 that includes 8 switch cells. The switch network group 216 is composed of MOS transistors. Although the switch in fig. 6 is shown as a MOS transistor, this is merely an example and does not limit the scope of the present disclosure. In alternative embodiments, bipolar transistors or other switches may be used. The gate of the MOS transistor is coupled to receive a select signal, such as Sel < m:0> in FIG. 3.

Each switching unit comprises a series connection of MOS transistors coupled to receive a respective oscillating clock. For example, the switching unit 2181 may operate to receive the clock 2160 clk <0>, and the switching unit 2182 may operate to receive the clock 2162 clk <2>. For example, the switching unit 2181 includes MOS transistors 2101 and 2102 connected in series. The series connected MOS transistors can significantly mitigate adjacent signal decoupling. This is because the n-gates connected in series have better isolation, which can greatly reduce signal coupling compared to the single gate design shown in fig. 5. The 8 switching units are operable to selectively turn on the switching units and turn off the other switching units based on the selection signal, so that the vibration clock having the target phase is output from the turned-on switching units as an intermediate clock.

For example, assuming Clk <0> and Clk <2> are intermediate IQ clocks having a target phase, the selection signals are configured such that the gates of the MOS transistors in the switch units 2181, 2182, 2183, and 2184 are all applied with a high voltage, and the gates of the MOS transistors in the other switch groups are all applied with a low voltage. In this case, the MOS transistors in the switching units 2181, 2182, 2183, and 2184 are controlled to be on, and the other MOS transistors are controlled to be off. Thus, clock 2160 Clk <0> is output as Clk_i, and clock 2162 Clk <2> is output as Clk_q. Similar mechanisms apply to other situations, such as "1" and "3" in fig. 4 being output as an intermediate clock with a target phase.

By using the arrangement of fig. 6, processing margin, voltage and temperature (PVT) variations have been significantly improved compared to conventional delay chain based architectures. The configuration of fig. 6 is shown as an illustration only and is not intended to limit the scope of the present disclosure. Although 8 oscillation clocks and IQ intermediate signals are shown in this example, this is merely illustrative and is not intended to limit the scope of the present disclosure. Other configurations for different numbers of oscillation clocks and different intermediate clocks are also possible. In an alternative embodiment, 16 oscillation signals may be used, and 4 intermediate clock signals uniformly distributed over 360 degrees may be selected simultaneously.

Fig. 7 illustrates a PLL 300 according to one embodiment of the disclosure. PLL 300 includes, among other components, voltage-to-current converter 104, generating device 202 coupled to voltage-to-current converter 104. The generating means 202 is operable to generate a clock based on the current received from the voltage-to-current converter 104. The phase and amplitude of the clock are variable based on the current.

Fig. 8 illustrates a method 400 of selecting a target clock according to one embodiment of the present disclosure. At 401, a plurality of oscillation clocks in a first format are generated. The plurality of oscillation clocks have the same frequency and different phases. At 404, an intermediate clock having a target phase is selected from the plurality of oscillating clocks based on the selection signal. At 406, the intermediate clock in the first format is converted to the target clock in the second format.

The following enumerates some example implementations of the present disclosure.

In some embodiments, an apparatus comprises: an oscillator, a selection circuit and a conversion circuit. The oscillator is operable to generate a plurality of oscillating clocks in a first format, the plurality of oscillating clocks having a same frequency and different phases. The selection circuit is operable to select an intermediate clock having a target phase from the plurality of oscillation clocks based on the selection signal. The conversion circuit is operable to convert the selected intermediate clock to a target clock of a second format, the target clock having the target phase. The oscillator may be formed external to or integrated with the integrated circuit comprising the selection circuit and the conversion circuit. It will be appreciated from the present disclosure describing the selection circuit and the conversion circuit that this does not imply a separation between logic elements that perform these functions, or that this does not imply that the selection circuit and the conversion circuit are different circuits. Rather, an integrated circuit may be designed as an element that performs two functions, and in this implementation, the terms of these elements perform the corresponding functions.

In some embodiments, the first format is a Current Mode Logic (CML) and the second format is a Complementary Metal Oxide Semiconductor (CMOS) format.

In some embodiments, the selection circuit is operable to select an intermediate in-phase clock having a first target phase and an intermediate quadrature clock having a second target phase, the first target phase and the second target phase being 90 degrees from each other.

In some embodiments, the conversion circuit is operable to convert the intermediate in-phase clock to a target in-phase clock. The conversion circuit is also operable to convert the intermediate quadrature clock to a target quadrature clock.

In some embodiments, the plurality of oscillating clocks comprises 8 clocks, the 8 clocks being 45 degrees or multiples of 45 degrees apart from each other.

In some embodiments, the selection circuit includes a plurality of switching units, each switching unit receiving a respective oscillating clock. The plurality of switching units are operable to be selectively turned on based on the selection signal such that the received oscillation clock output from the turned-on switching unit is the intermediate clock.

In some embodiments, each switching unit includes MOS transistors connected in series.

In some embodiments, the selection circuit includes an in-phase switch group operable to select the intermediate in-phase clock and a quadrature switch group operable to select the intermediate quadrature clock. The in-phase switch group includes a first plurality of MOS transistors, each having an end for receiving a corresponding oscillation clock and another end connected to other MOS transistors of the first plurality of MOS transistors, so that only the oscillation clock having the target phase is selectively output from the in-phase switch group based on a selection signal delivered to gates of the first plurality of MOS transistors. The quadrature switch group includes a second plurality of MOS transistors, each MOS transistor having an end for receiving a respective oscillation clock and another end connected to other MOS transistors of the second plurality of MOS transistors, so that only the oscillation clock having the target phase is selectively output from the quadrature switch group based on a selection signal delivered to gates of the second plurality of MOS transistors.

Some embodiments relate to a Phase Locked Loop (PLL) device. The PLL device includes: a voltage-to-current converter and a device coupled to the voltage-to-current converter. The apparatus coupled to the voltage-to-current converter comprises: an oscillator, a selection circuit and a conversion circuit. The oscillator is operable to generate a plurality of oscillating clocks in a first format, the plurality of oscillating clocks having a same frequency and different phases. The selection circuit is operable to select an intermediate clock having a target phase from the plurality of oscillation clocks based on the selection signal. The conversion circuit is operable to convert the selected intermediate clock to a target clock of a second format, the target clock having the target phase.

Some embodiments relate to a method. The method comprises the following steps: generating a plurality of oscillation clocks of a first format, the plurality of oscillation clocks having the same frequency and different phases; selecting an intermediate clock having a target phase from the plurality of oscillation clocks based on a selection signal; and converting the selected intermediate clock to a target clock having a second format of the target phase.

In some embodiments, selecting the intermediate clock having the target phase comprises:

an intermediate in-phase clock having a first target phase and an intermediate quadrature clock having a second target phase are selected, the first target phase and the second target phase differing from each other by 90 degrees.

In some embodiments, converting the intermediate clock to the target clock of the second format comprises: converting the intermediate in-phase clock of the first format to a target in-phase clock of the second format; and converting the intermediate quadrature clock of the first format to a target quadrature clock of the second format.

In some embodiments, the plurality of oscillating clocks is 8 clocks, the 8 clocks being 45 degrees or multiples of 45 degrees apart from each other.

The foregoing description of the embodiments of the present disclosure has been presented for purposes of illustration and description, and is not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the various embodiments described. The terminology used herein was chosen in order to best explain the principles of the embodiments, the practical application, or the improvement of technology in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. An apparatus (202), comprising:

an oscillator (106) operable to generate a plurality of oscillating clocks in a first format, the plurality of oscillating clocks having the same frequency and different phases;

a selection circuit (210) operable to select an intermediate clock having a target phase from the plurality of oscillation clocks based on a selection signal, wherein the selection circuit (210) is operable to select an intermediate in-phase clock having a first target phase and an intermediate quadrature clock having a second target phase, the first target phase and the second target phase being 90 degrees out of phase with each other; and

a conversion circuit (208) is operable to convert the selected intermediate clock to a target clock of a second format, the target clock having the target phase.

2. The apparatus (202) of claim 1, wherein the first format is a Current Mode Logic (CML) and the second format is a Complementary Metal Oxide Semiconductor (CMOS) format.

3. The apparatus (202) of claim 1, wherein the conversion circuit (208) is operable to convert the intermediate in-phase clock to a target in-phase clock; and

the conversion circuit (208) is also operable to convert the intermediate quadrature clock to a target quadrature clock.

4. The apparatus (202) of claim 1, wherein the plurality of oscillating clocks comprises 8 clocks, the 8 clocks differing from each other by 45 degrees or multiples of 45 degrees.

5. The apparatus (202) of claim 1, wherein said selection circuit (210) comprises a plurality of switching units (2181, 2182), each receiving a respective oscillating clock;

the plurality of switching units (2181, 2182) are operable to be selectively turned on based on the selection signal such that the received oscillating clock output from the turned-on switching units is the intermediate clock.

6. The apparatus (202) of claim 5, wherein each switching unit (2181, 2182) comprises MOS transistors (2101, 2102) connected in series.

7. The apparatus (202) of claim 1, wherein the selection circuit (210) comprises an in-phase switch group (212) operable to select the intermediate in-phase clock and a quadrature switch group (214) operable to select the intermediate quadrature clock;

the in-phase switch group (212) includes a first plurality of MOS transistors (2121), each MOS transistor (2121) having an end for receiving a respective oscillation clock and another end connected to the other MOS transistors of the first plurality of MOS transistors, thereby selectively outputting the oscillation clock having the target phase only from the in-phase switch group based on a selection signal delivered to gates of the first plurality of MOS transistors; and

the quadrature switch group (214) includes a second plurality of MOS transistors (2141), each MOS transistor (2141) having an end for receiving a respective oscillation clock and another end connected to other MOS transistors of the second plurality of MOS transistors, such that only the oscillation clock having the target phase is selectively output from the quadrature switch group based on a selection signal delivered to gates of the second plurality of MOS transistors.

8. A Phase Locked Loop (PLL) device (300), comprising:

a voltage-to-current converter (104); and

the apparatus (202) of claim 1, coupled to the voltage-to-current converter (104).

9. A method (400) comprising:

generating a plurality of oscillation clocks of a first format, the plurality of oscillation clocks having the same frequency and different phases;

selecting an intermediate clock having a target phase from the plurality of oscillation clocks based on a selection signal, wherein selecting the intermediate clock having the target phase comprises: selecting an intermediate in-phase clock having a first target phase and an intermediate quadrature clock having a second target phase, the first target phase and the second target phase differing from each other by 90 degrees; and

the selected intermediate clock is converted to a target clock having a second format of the target phase.

10. The method (400) of claim 9, wherein the first format is a Current Mode Logic (CML) and the second format is a Complementary Metal Oxide Semiconductor (CMOS) format.

11. The method (400) of claim 9, wherein converting the intermediate clock to the target clock of the second format comprises:

converting the intermediate in-phase clock of the first format to a target in-phase clock of the second format; and

the intermediate quadrature clock of the first format is converted to a target quadrature clock of the second format.

12. The method (400) of claim 9, wherein the plurality of oscillating clocks is 8 clocks, the 8 clocks differing from each other by 45 degrees or multiples of 45 degrees.