CN109216157A - The method of back surface of the wafer sealing - Google Patents
The method of back surface of the wafer sealing Download PDFInfo
- Publication number
- CN109216157A CN109216157A CN201710541857.8A CN201710541857A CN109216157A CN 109216157 A CN109216157 A CN 109216157A CN 201710541857 A CN201710541857 A CN 201710541857A CN 109216157 A CN109216157 A CN 109216157A
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- wafer
- back surface
- wafer substrates
- edge
- substrates
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02002—Preparing wafers
- H01L21/02005—Preparing bulk and homogeneous wafers
- H01L21/02008—Multistep processes
- H01L21/0201—Specific process step
- H01L21/02016—Backside treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
Abstract
The present invention provides a kind of method of back surface of the wafer sealing, comprising the following steps: provides the wafer substrates for completing two-sided, edge and notch polishing；Polysilicon layer is formed at the back side of the wafer substrates；Polysilicon at wafer substrates dorsal edge oblique angle is removed using the method that edge oxide polishes；Positive polishing and cleaning are carried out to the wafer substrates.It uses the method for the present invention to carry out sealing backside to wafer substrates before grown epitaxial layer on the wafer substrates, can effectively prevent the problem of auto-dope occur when epitaxial wafer, method is easy to implement, simple and practical.
Description
Technical field
The present invention relates to technical field of semiconductors, more particularly to a kind of method of back surface of the wafer sealing.
Background technique
Front wafer surface growth have explication electrically and physically property epitaxial layer, be made on chip it is various
The initial step of device.For grown epitaxial layer, the support that chip is generally mated pedestal is placed in epitaxial reaction chamber room, is promoted
The temperature of reaction chamber, such as it is warming up to 800-1150 degrees Celsius, it is passed through reaction gas, reacts the gas with chip, in crystalline substance
Piece front forms epitaxial layer.In order to grow one layer of crystalline silicon on silicon, silane gas, such as trichlorosilane can be passed through
(TCS), the front of silicon wafer is flowed through.
Before front wafer surface deposits epitaxial layer, auto-dope in order to prevent generally requires to seal before epitaxial diposition brilliant
The piece back side.Auto-dope typically refers to discharge dopant or pollutant from back surface of the wafer, and front is released in epitaxial deposition process
The deposition of the dopant or pollutant put.In the case where back surface of the wafer is sealed and is lacked, since epitaxial diposition needs high-temperature process,
Auto-dope would generally occur in epitaxial deposition process.Auto-dope is particularly disadvantageous for the production of device, because in the epitaxial diposition phase
Between be deposited on the dopant of front wafer surface and pollutant and can change the electrology characteristic of epitaxial layer, such as change resistivity.Dopant
It is usually deposited at fringe region of the front wafer surface relative to central area with pollutant, therefore, the electrology characteristic of gained epitaxial layer,
Due to auto-dope, the variation on direction is had.Specifically, due to auto-dope, additional dopant can be along the certain of chip
Area deposition can change on the heart to the diametrical direction in these regions in the wafer so as to cause the resistivity of epitaxial layer.?
In practical application, if the electrology characteristic of epitaxial layer is required quite uniformly, to be drawn by auto-dope on the entire front of chip
The variation of epitaxial layer electrology characteristic risen is very unfavorable, and may cause chip produced and discarded, especially pair
In the substrate wafer of heavy doping.
Existing sealing backside technique generally uses the two-sided formation polysilicon layer or low temperature oxide layer in wafer substrates, so
Layer protecting film is pasted at the back side of chip afterwards, then with wet chemical etching technique method by the polysilicon layer or low-temperature oxidation of front wafer surface
Layer removal.The process flow is more complex, and needs to purchase additional film sticking equipment.
Summary of the invention
In view of prior art described above, the purpose of the present invention is to provide a kind of methods of back surface of the wafer sealing, are used for
Solve the problems, such as auto-dope occur when epitaxial wafer in the prior art.
In order to achieve the above objects and other related objects, the present invention provides a kind of method of back surface of the wafer sealing, including with
Lower step:
One wafer substrates for completing two-sided, edge and notch polishing are provided；
Polysilicon layer is formed at the back side of the wafer substrates；
Using the polycrystalline at method removal wafer substrates dorsal edge oblique angle (bevel) of edge oxide polishing
Silicon；
Positive polishing and cleaning are carried out to the wafer substrates.
Optionally, the two-sided of the wafer substrates, edge and notch is completed using colloidal silica dispersion slurry to polish.
Optionally, the polysilicon layer is obtained using Low Pressure Chemical Vapor Deposition.
Optionally, it uses chemical mechanical grinding (CMP) slurry including cerium oxide to carry out edge oxide to polish to realize
It removes bevel angle.
Still optionally further, the thickness that bevel angle is removed is less than or equal to 3mm.
In order to achieve the above objects and other related objects, the present invention also provides a kind of methods of epitaxial wafer, outside carrying out
Before prolonging growth, sealing backside is carried out to wafer substrates using the method for aforementioned wafer sealing backside, is then served as a contrast in the chip
The front grown epitaxial layer at bottom.
As described above, the method that back surface of the wafer of the invention seals, has the advantages that
The present invention is formed with polysilicon layer as sealant in back surface of the wafer, and edge oxygen is used after forming polysilicon layer
The method of compound polishing is purged back surface of the wafer bevel angle, is carried out using this method to back surface of the wafer before epitaxial growth
Sealing can effectively prevent the problem of auto-dope occur when epitaxial wafer, and method is easy to implement, simple and practical.
Detailed description of the invention
Fig. 1 is shown as the schematic diagram of back surface of the wafer encapsulating method provided in an embodiment of the present invention.
Fig. 2 a-2d is shown as back surface of the wafer sealing and the process flow of grown epitaxial layer signal provided in an embodiment of the present invention
Figure.
Specific embodiment
Illustrate embodiments of the present invention below by way of specific specific example, those skilled in the art can be by this specification
Other advantages and efficacy of the present invention can be easily understood for disclosed content.The present invention can also pass through in addition different specific realities
The mode of applying is embodied or practiced, the various details in this specification can also based on different viewpoints and application, without departing from
Various modifications or alterations are carried out under spirit of the invention.It should be noted that in the absence of conflict, following embodiment and implementation
Feature in example can be combined with each other.
It should be noted that illustrating the basic structure that only the invention is illustrated in a schematic way provided in following embodiment
Think, only shown in schema then with related component in the present invention rather than component count, shape and size when according to actual implementation
Draw, when actual implementation kenel, quantity and the ratio of each component can arbitrarily change for one kind, and its assembly layout kenel
It is likely more complexity.
Existing sealing backside technique generally uses the two-sided formation polysilicon layer or low temperature oxide layer in wafer substrates, so
Layer protecting film is pasted at the back side of chip afterwards, then with wet chemical etching technique method by the polysilicon layer or low-temperature oxidation of front wafer surface
Layer removal.The process flow is more complex, and needs to purchase additional film sticking equipment.Occur certainly when in order to effectively prevent epitaxial wafer
The problem of doping, the present embodiment will provide a kind of new method that the back surface of the wafer that can be used for epitaxial growth seals.
Referring to Fig. 1, a kind of method of back surface of the wafer sealing provided in this embodiment, comprising the following steps:
S1 provides the wafer substrates for completing two-sided, edge and notch polishing；
S2 forms polysilicon layer at the back side of the wafer substrates；
S3 removes the polysilicon at wafer substrates dorsal edge oblique angle using the method for edge oxide polishing；
S4 carries out positive polishing and cleaning to the wafer substrates.
In epitaxy technique, before carrying out epitaxial growth, this method can be used, sealing backside is carried out to wafer substrates, then
Again in the front grown epitaxial layer of the wafer substrates, to avoid auto-doping phenomenon, to be conducive to improve epitaxial layer entire
The uniformity of electricity and physical property in wafer substrates.
The method of back surface of the wafer sealing provided in this embodiment is further described with reference to the accompanying drawing.
Firstly, preparing a piece of wafer substrates for completing two-sided, edge and notch polishing.The wafer substrates, which can be, partly to be led
Body wafer, such as Silicon Wafer.
In the present embodiment, colloidal silica dispersion slurry or other suitable throwings can be used by completing two-sided, edge and notch polishing
Light slurry.Wherein, chip is two-sided, the process of edge and notch polishing can use the known skill of those skilled in the art
Art means, therefore this will not be repeated here.
Then, polysilicon layer is formed at the back side of the wafer substrates.Forming the polysilicon layer can be using chemical gas
It mutually deposits, such as the methods of low-pressure chemical vapor deposition (LPCVD).In the present embodiment, using a low-pressure chemical vapor deposition furnace,
One layer of polysilicon layer of backside deposition of the wafer substrates.Form the skill that polysilicon layer can be known using those skilled in the art
Art means, actual conditions and parameter those skilled in the art can choose according to the actual situation.
As shown in Figure 2 a, after the step, there is polysilicon layer 200 ' in the backside deposition of wafer substrates 100.
Next, as shown in Figure 2 b, being removed using the method for edge oxide polishing (edge oxide polishing)
Polysilicon layer 200 ' at the 100 dorsal edge oblique angle of wafer substrates, is finally remained at 100 back side of wafer substrates
Polysilicon layer is polysilicon sealant 200.
It specifically, can be using chemical mechanical grinding (CMP) slurry or other suitable polishing slurries including cerium oxide
Edge oxide polishing is carried out, to realize that bevel angle is removed.The thickness that bevel angle is removed can be 0-3mm.
Then, positive polishing and cleaning are carried out to the wafer substrates 100, the back surface of the wafer for obtaining can be used for extension is close
Envelope.As shown in Figure 2 c, the back surface of the wafer sealing obtained is overleaf equipped with polysilicon sealant 200, and at the back side of the chip
Remove bevel angle.The technological means that polishing and cleaning method in the step can use those skilled in the art known,
Therefore this will not be repeated here.
Finally, as shown in Figure 2 d, it can be outer in the front growth of the wafer substrates 100 according to the needs of practical application
Prolong layer 300.
In conclusion the present invention is formed with polysilicon layer as sealing in back surface of the wafer, and forming polysilicon layer back
The method of edge oxide cmp is purged back surface of the wafer bevel angle, using this method to back surface of the wafer before epitaxial growth
Being sealed can effectively prevent the problem of auto-dope occur when epitaxial wafer, and method is easy to implement, simple and practical.
So the present invention effectively overcomes various shortcoming in the prior art and has high industrial utilization value.
The above-described embodiments merely illustrate the principles and effects of the present invention, and is not intended to limit the present invention.It is any ripe
The personage for knowing this technology all without departing from the spirit and scope of the present invention, carries out modifications and changes to above-described embodiment.Cause
This, institute is complete without departing from the spirit and technical ideas disclosed in the present invention by those of ordinary skill in the art such as
At all equivalent modifications or change, should be covered by the claims of the present invention.
Claims (6)
1. a kind of method of back surface of the wafer sealing, which is characterized in that the described method comprises the following steps:
One wafer substrates for completing two-sided, edge and notch polishing are provided；
Polysilicon layer is formed at the back side of the wafer substrates；
Polysilicon at wafer substrates dorsal edge oblique angle is removed using the method that edge oxide polishes；
Positive polishing and cleaning are carried out to the wafer substrates.
2. the method for back surface of the wafer sealing according to claim 1, it is characterised in that: complete institute using colloidal silica dispersion slurry
State the two-sided of wafer substrates, edge and notch polishing.
3. the method for back surface of the wafer sealing according to claim 1, it is characterised in that: the polysilicon layer uses low pressure
Vapour deposition process is learned to obtain.
4. the method for back surface of the wafer sealing according to claim 1, it is characterised in that: using the chemical machine for including cerium oxide
Tool grinding slurry carries out edge oxide polishing to realize that bevel angle is removed.
5. the method for back surface of the wafer sealing according to claim 4, it is characterised in that: the thickness that bevel angle is removed is less than
Equal to 3mm.
6. a kind of method of epitaxial wafer, it is characterised in that: before carrying out epitaxial growth, using any in claim 1-5
The method of back surface of the wafer sealing described in carries out sealing backside to wafer substrates, then in the front growth of the wafer substrates
Epitaxial layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710541857.8A CN109216157A (en) | 2017-07-04 | 2017-07-04 | The method of back surface of the wafer sealing |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710541857.8A CN109216157A (en) | 2017-07-04 | 2017-07-04 | The method of back surface of the wafer sealing |
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| Publication Number | Publication Date |
|---|---|
| CN109216157A true CN109216157A (en) | 2019-01-15 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710541857.8A Pending CN109216157A (en) | 2017-07-04 | 2017-07-04 | The method of back surface of the wafer sealing |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113802184A (en) * | 2021-08-25 | 2021-12-17 | 东莞市天域半导体科技有限公司 | Method for quickly removing deposits on back of wafer in silicon carbide epitaxial process |
Citations (8)
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|---|---|---|---|---|
| US4608095A (en) * | 1983-02-14 | 1986-08-26 | Monsanto Company | Gettering |
| US5998283A (en) * | 1996-08-19 | 1999-12-07 | Shin-Etsu Handotai Co., Ltd. | Silicon wafer having plasma CVD gettering layer with components/composition changing in depth-wise direction and method of manufacturing the silicon wafer |
| US6013564A (en) * | 1996-10-03 | 2000-01-11 | Nec Corporation | Method of manufacturing semiconductor wafer without mirror polishing after formation of blocking film |
| CN1685478A (en) * | 2002-09-25 | 2005-10-19 | 硅电子股份公司 | Two layer LTO backside seal for a wafer |
| CN101638557A (en) * | 2008-08-01 | 2010-02-03 | 安集微电子（上海）有限公司 | Chemi-mechanical polishing liquid |
| CN101740525A (en) * | 2008-11-24 | 2010-06-16 | 合晶科技股份有限公司 | Encapsulation structure for wafer backside |
| CN106158768A (en) * | 2015-04-17 | 2016-11-23 | 上海申和热磁电子有限公司 | Trimming composite back seal coat structure and manufacture method thereof is had for silicon chip |
| WO2017026092A1 (en) * | 2015-08-07 | 2017-02-16 | 信越半導体株式会社 | Semiconductor wafer manufacturing method |
-
2017
- 2017-07-04 CN CN201710541857.8A patent/CN109216157A/en active Pending
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4608095A (en) * | 1983-02-14 | 1986-08-26 | Monsanto Company | Gettering |
| US5998283A (en) * | 1996-08-19 | 1999-12-07 | Shin-Etsu Handotai Co., Ltd. | Silicon wafer having plasma CVD gettering layer with components/composition changing in depth-wise direction and method of manufacturing the silicon wafer |
| US6013564A (en) * | 1996-10-03 | 2000-01-11 | Nec Corporation | Method of manufacturing semiconductor wafer without mirror polishing after formation of blocking film |
| CN1685478A (en) * | 2002-09-25 | 2005-10-19 | 硅电子股份公司 | Two layer LTO backside seal for a wafer |
| CN101638557A (en) * | 2008-08-01 | 2010-02-03 | 安集微电子（上海）有限公司 | Chemi-mechanical polishing liquid |
| CN101740525A (en) * | 2008-11-24 | 2010-06-16 | 合晶科技股份有限公司 | Encapsulation structure for wafer backside |
| CN106158768A (en) * | 2015-04-17 | 2016-11-23 | 上海申和热磁电子有限公司 | Trimming composite back seal coat structure and manufacture method thereof is had for silicon chip |
| WO2017026092A1 (en) * | 2015-08-07 | 2017-02-16 | 信越半導体株式会社 | Semiconductor wafer manufacturing method |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113802184A (en) * | 2021-08-25 | 2021-12-17 | 东莞市天域半导体科技有限公司 | Method for quickly removing deposits on back of wafer in silicon carbide epitaxial process |
| CN113802184B (en) * | 2021-08-25 | 2022-06-28 | 东莞市天域半导体科技有限公司 | Method for quickly removing deposits on back of wafer in silicon carbide epitaxial process |
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Application publication date: 20190115 |