CN109167613A - A kind of multicast antijam communication terminal hardware structure - Google Patents
A kind of multicast antijam communication terminal hardware structure Download PDFInfo
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- CN109167613A CN109167613A CN201811276711.6A CN201811276711A CN109167613A CN 109167613 A CN109167613 A CN 109167613A CN 201811276711 A CN201811276711 A CN 201811276711A CN 109167613 A CN109167613 A CN 109167613A
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- 238000004891 communication Methods 0.000 title claims abstract description 21
- 238000006243 chemical reaction Methods 0.000 claims description 14
- 230000010365 information processing Effects 0.000 claims description 14
- 238000005070 sampling Methods 0.000 claims description 4
- 238000001228 spectrum Methods 0.000 claims description 4
- 238000013139 quantization Methods 0.000 claims description 3
- 230000001360 synchronised effect Effects 0.000 claims description 3
- 238000005516 engineering process Methods 0.000 abstract description 3
- 230000005540 biological transmission Effects 0.000 abstract description 2
- 238000010586 diagram Methods 0.000 description 8
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- 238000012986 modification Methods 0.000 description 2
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- 238000003786 synthesis reaction Methods 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/38—Transceivers, i.e. devices in which transmitter and receiver form a structural unit and in which at least one part is used for functions of transmitting and receiving
- H04B1/40—Circuits
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/06—Receivers
- H04B1/10—Means associated with receiver for limiting or suppressing noise or interference
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/69—Spread spectrum techniques
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/69—Spread spectrum techniques
- H04B1/713—Spread spectrum techniques using frequency hopping
- H04B1/7136—Arrangements for generation of hop frequencies, e.g. using a bank of frequency sources, using continuous tuning or using a transform
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/69—Spread spectrum techniques
- H04B1/713—Spread spectrum techniques using frequency hopping
- H04B1/715—Interference-related aspects
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/69—Spread spectrum techniques
- H04B2001/6908—Spread spectrum techniques using time hopping
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/69—Spread spectrum techniques
- H04B1/713—Spread spectrum techniques using frequency hopping
- H04B1/715—Interference-related aspects
- H04B2001/7152—Interference-related aspects with means for suppressing interference
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- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Transceivers (AREA)
Abstract
The invention belongs to wireless communication technology fields, and in particular to it is a kind of for frequency hopping+jump when multicast antijam communication terminal hardware structure.The hardware structure uses parallel multi-channel, the receiver architecture of Small Universal and wideband digital frequency agility transmitter architecture, realizes the reception and transmission of the full working frequency range of communication terminal equipment, has multicast function.
Description
Technical Field
The invention belongs to the technical field of wireless communication, and particularly relates to a hardware architecture of a one-transmitter multi-receiver anti-interference communication terminal aiming at frequency hopping and time hopping.
Background
With the development of electronic countermeasure technology, the electromagnetic environment of communication is increasingly severe, and an anti-interference communication system keeps receiving a desired communication signal and simultaneously suppresses the influence of an interference signal to the maximum extent. The frequency hopping communication is an evasive anti-interference communication system, and has strong anti-interference capability and good confidentiality. On the basis, a time hopping technology is adopted, the pulse is compressed, the frequency spectrum is further widened, the power spectral density is reduced, meanwhile, the information is discretized in a time domain and a frequency domain two-dimensional space, the random performance is better, and the anti-interference and confidentiality performance is stronger. Therefore, the anti-interference communication system based on frequency hopping and time hopping has great research value and wide market prospect.
Disclosure of Invention
Technical problem to be solved
The invention provides a hardware architecture of a one-transmitting and multi-receiving anti-interference communication terminal, which aims to solve the technical problem of how to improve the anti-interference performance of the one-transmitting and multi-receiving communication terminal.
(II) technical scheme
In order to solve the technical problem, the invention provides a hardware architecture of a one-transmitter-multiple-receiver anti-interference communication terminal, which comprises a radio frequency transceiver switch, a radio frequency power division network, a programmable radio frequency channel module, a high-performance signal and information processing module, an interface control module, an orthogonal modulation up-conversion module, a power amplifier module and a radio frequency filter bank; wherein,
for a receiver channel of a hardware architecture, a wireless radio frequency signal received by an antenna sequentially passes through a radio frequency transceiving switch, a radio frequency power distribution network and a multi-channel programmable radio frequency channel module, and is subjected to multi-channel synchronous parallel high-speed analog-to-digital conversion circuit quantization sampling, baseband signal demodulation and comprehensive digital information processing through a high-performance signal and information processing module, so that service data is received and is interacted with the outside through an interface control module;
for a transmitter channel of a hardware architecture, service data is preprocessed by an interface control module, high-speed time hopping + frequency hopping, broadband digital frequency agility and high-speed digital-to-analog conversion are carried out through a high-performance signal and information processing module, orthogonal modulation and frequency spectrum shifting are completed through an orthogonal modulation up-conversion module, and signals are transmitted to a space through an antenna after sequentially passing through a power amplifier module, a radio frequency filter bank and a radio frequency transceiving switch.
Optionally, the hardware architecture further includes an integrated power management module, configured to supply power to each part in the hardware architecture.
Optionally, the multi-programmable radio frequency channel module is a multi-channel programmable radio frequency channel module.
(III) advantageous effects
The hardware architecture of the anti-interference communication terminal with one transmitting end and multiple receiving ends, which is provided by the invention, adopts a parallel multi-channel, small and universal receiver architecture and a broadband digital agile frequency transmitter architecture, realizes the receiving and transmitting of the communication terminal at the full working frequency band, and has the functions of one transmitting end and multiple receiving ends.
Drawings
Fig. 1 is a schematic block diagram of a hardware architecture of a one-transmitter-multiple-receiver anti-interference communication terminal according to the present embodiment;
FIG. 2 is a block diagram of the high performance signal and information processing module hardware in this embodiment;
FIG. 3 is a schematic block diagram of hardware of the programmable RF channel module in this embodiment;
fig. 4 is a schematic block diagram of the hardware of the rf filter bank in this embodiment.
Detailed Description
In order to make the objects, contents and advantages of the present invention clearer, the following detailed description of the embodiments of the present invention will be made in conjunction with the accompanying drawings and examples.
The embodiment provides a hardware architecture of a one-to-many-receive anti-interference communication terminal, and a functional block diagram of the hardware architecture is shown in fig. 1. This embodiment is illustrated with one transmission and four receptions as an example. The hardware architecture comprises a radio frequency receiving and transmitting switch, a radio frequency power distribution network, a programmable radio frequency channel module, a high-performance signal and information processing module, an interface control module, a quadrature modulation up-conversion module, a power amplifier module, a radio frequency filter bank and a comprehensive power management module.
The integrated power management module is used for supplying power to all parts of the whole hardware architecture.
For the receiver channel of the hardware architecture, a wireless radio frequency signal received by an antenna sequentially passes through a radio frequency transceiving switch, a radio frequency power distribution network and a multi-channel programmable radio frequency channel module, and is subjected to multi-channel synchronous parallel high-speed analog-digital conversion circuit quantization sampling, baseband signal demodulation and comprehensive digital information processing through a high-performance signal and information processing module, so that service data is received and is interacted with the outside through an interface control module.
For the transmitter channel of the hardware architecture, service data is preprocessed by an interface control module, high-speed time hopping, frequency hopping, broadband digital frequency agility and high-speed digital-to-analog conversion are carried out through a high-performance signal and information processing module, orthogonal modulation and frequency spectrum shifting are completed through an orthogonal modulation up-conversion module, and signals are transmitted to the space through an antenna after sequentially passing through a power amplifier module, a radio frequency filter bank and a radio frequency transceiving switch.
In the hardware architecture of this embodiment, the high-performance signal and information processing module includes a baseband signal processor FPGA, a digital signal processor DSP, a memory (SDRAM, Flash), an intermediate frequency signal processing circuit, a high-speed ADC intermediate frequency signal sampling circuit, a high-speed TxDAC signal shaping circuit, an orthogonal modulation up-conversion circuit, a radio frequency small signal amplifying circuit, a clock distribution management circuit, a power management circuit, an internal interface circuit, and a loading/configuration/test circuit, and a hardware schematic block diagram thereof is shown in fig. 2.
The programmable rf channel module mainly implements functions of rf filtering, low noise amplification, local oscillation frequency synthesis and filtering, down-conversion, intermediate frequency filtering, intermediate frequency amplification, and the like on an input rf signal, and a hardware schematic block diagram thereof is shown in fig. 3.
The rf filter bank is composed of an rf select switch, an rf band pass filter, an rf switch control circuit, and the like, and a hardware schematic block diagram thereof is shown in fig. 4.
The above description is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, several modifications and variations can be made without departing from the technical principle of the present invention, and these modifications and variations should also be regarded as the protection scope of the present invention.
Claims (3)
1. A hardware architecture of a one-transmitter-multiple-receiver anti-interference communication terminal is characterized in that the hardware architecture comprises a radio frequency transceiver switch, a radio frequency power division network, a programmable radio frequency channel module, a high-performance signal and information processing module, an interface control module, a quadrature modulation up-conversion module, a power amplifier module and a radio frequency filter bank; wherein,
for the receiver channel of the hardware architecture, a wireless radio frequency signal received by an antenna sequentially passes through a radio frequency transceiving switch, a radio frequency power distribution network and a multi-channel programmable radio frequency channel module, and is subjected to multi-channel synchronous parallel high-speed analog-to-digital conversion circuit quantization sampling, baseband signal demodulation and comprehensive digital information processing through a high-performance signal and information processing module, so that service data is received and is interacted with the outside through an interface control module;
for the transmitter channel of the hardware architecture, service data is preprocessed by an interface control module, high-speed time hopping, frequency hopping, broadband digital frequency agility and high-speed digital-to-analog conversion are carried out through a high-performance signal and information processing module, orthogonal modulation and frequency spectrum shifting are completed through an orthogonal modulation up-conversion module, and signals are transmitted to the space through an antenna after sequentially passing through a power amplifier module, a radio frequency filter bank and a radio frequency transceiving switch.
2. The hardware architecture of claim 1, wherein the hardware architecture further comprises an integrated power management module to provide power to portions of the hardware architecture.
3. The hardware architecture of claim 1, wherein the multi-programmable radio frequency channel module is a multi-channel programmable radio frequency channel module.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811276711.6A CN109167613A (en) | 2018-10-30 | 2018-10-30 | A kind of multicast antijam communication terminal hardware structure |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201811276711.6A CN109167613A (en) | 2018-10-30 | 2018-10-30 | A kind of multicast antijam communication terminal hardware structure |
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| CN109167613A true CN109167613A (en) | 2019-01-08 |
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| CN201811276711.6A Pending CN109167613A (en) | 2018-10-30 | 2018-10-30 | A kind of multicast antijam communication terminal hardware structure |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110245735A (en) * | 2019-07-05 | 2019-09-17 | 深圳市章誉物联技术有限公司 | A kind of demixing scan sense channel RFID controller |
| CN111865382A (en) * | 2019-04-26 | 2020-10-30 | 华为技术有限公司 | Signal transmission circuit, signal reception circuit, electronic device, and base station |
| CN112994742A (en) * | 2019-12-16 | 2021-06-18 | 鹤壁天海电子信息系统有限公司 | Method for realizing frequency hopping synchronization, receiver and communication equipment |
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| CN101425816A (en) * | 2008-09-26 | 2009-05-06 | 中国科学院微电子研究所 | Transceiver for wireless ultra-wideband and method for transceiving signal by transceiver |
| CN205883231U (en) * | 2016-01-07 | 2017-01-11 | 中国航空无线电电子研究所 | General hardware platform towards large capacity broadband frequency hopping communication |
| CN106685445A (en) * | 2016-11-25 | 2017-05-17 | 天津津航计算技术研究所 | Detection and elimination device for reverse self-excitation interference in TDD system |
-
2018
- 2018-10-30 CN CN201811276711.6A patent/CN109167613A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101425816A (en) * | 2008-09-26 | 2009-05-06 | 中国科学院微电子研究所 | Transceiver for wireless ultra-wideband and method for transceiving signal by transceiver |
| CN205883231U (en) * | 2016-01-07 | 2017-01-11 | 中国航空无线电电子研究所 | General hardware platform towards large capacity broadband frequency hopping communication |
| CN106685445A (en) * | 2016-11-25 | 2017-05-17 | 天津津航计算技术研究所 | Detection and elimination device for reverse self-excitation interference in TDD system |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111865382A (en) * | 2019-04-26 | 2020-10-30 | 华为技术有限公司 | Signal transmission circuit, signal reception circuit, electronic device, and base station |
| CN111865382B (en) * | 2019-04-26 | 2022-09-02 | 华为技术有限公司 | Signal transmission circuit, signal reception circuit, electronic device, and base station |
| US12040823B2 (en) | 2019-04-26 | 2024-07-16 | Huawei Technologies Co., Ltd. | Signal sending circuit, signal receiving circuit, electronic apparatus, and base station |
| CN110245735A (en) * | 2019-07-05 | 2019-09-17 | 深圳市章誉物联技术有限公司 | A kind of demixing scan sense channel RFID controller |
| CN112994742A (en) * | 2019-12-16 | 2021-06-18 | 鹤壁天海电子信息系统有限公司 | Method for realizing frequency hopping synchronization, receiver and communication equipment |
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Application publication date: 20190108 |