CN109167583B - Transconductance amplifier - Google Patents
Transconductance amplifier Download PDFInfo
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- CN109167583B CN109167583B CN201811283011.XA CN201811283011A CN109167583B CN 109167583 B CN109167583 B CN 109167583B CN 201811283011 A CN201811283011 A CN 201811283011A CN 109167583 B CN109167583 B CN 109167583B
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- 238000005516 engineering process Methods 0.000 description 9
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- 230000003068 static effect Effects 0.000 description 6
- 238000001914 filtration Methods 0.000 description 5
- 238000013461 design Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
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- 230000033228 biological regulation Effects 0.000 description 1
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/45—Differential amplifiers
- H03F3/45071—Differential amplifiers with semiconductor devices only
- H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/26—Modifications of amplifiers to reduce influence of noise generated by amplifying elements
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/56—Modifications of input or output impedances, not otherwise provided for
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
- H03F2203/45—Indexing scheme relating to differential amplifiers
- H03F2203/45302—Indexing scheme relating to differential amplifiers the common gate stage of a cascode dif amp being controlled
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Abstract
The invention discloses a transconductance amplifier which comprises a first NMOS tube and a second NMOS tube which are in common source and common gate, wherein the grid electrode of the first NMOS tube is connected with a positive input end, the grid electrode of the second NMOS tube is connected with a negative input end, the source electrodes of the first NMOS tube and the second NMOS tube are connected with a current source, the drain electrode of the first NMOS tube is connected with one end of a first amplifier, the other end of the first amplifier is connected with the source electrode of the second PMOS tube, the drain electrode of the second NMOS tube is connected with one end of the second amplifier, the other end of the second amplifier is connected with the source electrode of the first PMOS tube, the drain electrode of the first PMOS tube is connected with one end of a third amplifier, the other end of the third amplifier is connected with an output end, and the drain electrode of the second PMOS tube is connected with the output end. The amplifier used in the invention adopts a current mirror amplifier architecture, the gain of the grid control end noise and the power supply noise is close to 0dB, and the output stage adopts a common-source common-grid architecture, so that good power supply inhibition performance is realized.
Description
Technical Field
The present invention relates to the field of integrated circuits, and in particular, to a transconductance amplifier.
Background
In order to increase the signal dynamic range of the transconductance amplifier as much as possible, various technologies have been developed in the conventional design to increase the signal output range, and various technologies have been developed to suppress the power supply noise, where the response of the power supply noise at the output end is generally measured by a power supply rejection ratio indicator, and the higher the power supply rejection ratio, the higher the dynamic range of the signal. The conventional techniques for improving the power supply rejection of the transconductance amplifier include the following:
(1) A power supply preconditioning technique;
I.e. a linear regulation technique is applied to the supply, and the regulated supply is used to supply the transconductance amplifier, e.g. LDO (Low drop out) or a Sub-regulator. The output of these sources is typically a 20dB boost relative to the original source PSRR (power supply rejection ratio). But this technique is not suitable for low voltage applications and the ancillary circuitry is complex.
(2) Cascode or cascoded technology;
The equivalent impedance of the output end can be improved by utilizing the technology, so that the noise transmission of the positive and negative power supplies to the output end is reduced. However, this technique reduces the output signal range, which has an impact on low voltage designs.
(3) Feedforward noise cancellation techniques;
The sampling power supply noise is loaded to the grid control end of the control device, so that equivalent small signals of the source end and the grid end of the control device are mutually offset, the conduction characteristic of the control device is not changed along with the power supply noise, and the output end can obtain high PSRR in a very wide frequency range. This technique requires complex circuit support.
(4) Outputting a filtering technology;
this technique requires a large area of capacitance and has a large impact on the output signal settling time.
Therefore, how to obtain a transconductance amplifier with simple structure and excellent effect is always a technical problem expected to be solved in the industry.
Disclosure of Invention
The invention aims to provide a transconductance amplifier, which optimizes the structure of a device and improves the positive power supply rejection ratio performance.
In order to solve the above technical problems, the present invention provides a transconductance amplifier, including:
The first NMOS tube and the second NMOS tube of the common source common gate, the grid electrode of the first NMOS tube is connected with the positive input end, the grid electrode of the second NMOS tube is connected with the negative input end, the source electrode of the first NMOS tube and the source electrode of the second NMOS tube are connected with a current source, the drain electrode of the first NMOS tube is connected with one end of a first amplifier, the other end of the first amplifier is connected with the source electrode of the second PMOS tube, the drain electrode of the second NMOS tube is connected with one end of a second amplifier, the other end of the second amplifier is connected with the source electrode of the first PMOS tube, the drain electrode of the first PMOS tube is connected with one end of a third amplifier, the other end of the third amplifier is connected with the output end, and the drain electrode of the second PMOS tube is connected with the output end.
Optionally, for the transconductance amplifier, substrate bias of the first PMOS transistor and substrate bias of the second PMOS transistor adopt filtered static voltage bias.
Optionally, for the transconductance amplifier, the substrates of the first PMOS transistor and the second PMOS transistor are connected to a low-pass filter.
Optionally, for the transconductance amplifier, the output end is further provided with a filter capacitor.
Optionally, for the transconductance amplifier, a capacitance of the capacitor is greater than or equal to 1pF.
Optionally, for the transconductance amplifier, the first amplifier includes a third PMOS transistor, a fourth PMOS transistor, and a fifth PMOS transistor, where a drain of the third PMOS transistor is connected to a drain of the first NMOS transistor, and is connected to a gate of the fourth PMOS transistor and a gate of the fifth PMOS transistor, a source of the third PMOS transistor is connected to a drain of the fourth PMOS transistor, a source of the fourth PMOS transistor and a source of the fifth PMOS transistor are connected to a supply voltage, and a drain of the fifth PMOS transistor is connected to a source of the second PMOS transistor.
Optionally, for the transconductance amplifier, the second amplifier includes a sixth PMOS transistor, a seventh PMOS transistor, and an eighth PMOS transistor, where a drain of the sixth PMOS transistor is connected to a drain of the second NMOS transistor, and is connected to a gate of the seventh PMOS transistor and a gate of the eighth PMOS transistor, a source of the sixth PMOS transistor is connected to a drain of the seventh PMOS transistor, a source of the seventh PMOS transistor and a source of the eighth PMOS transistor are connected to a supply voltage, and a drain of the eighth PMOS transistor is connected to a source of the first PMOS transistor.
Optionally, for the transconductance amplifier, substrate bias of the third PMOS transistor and substrate bias of the sixth PMOS transistor adopt filtered static voltage bias.
Optionally, for the transconductance amplifier, substrates of the third PMOS transistor and the sixth PMOS transistor are connected to the low-pass filter.
Optionally, for the transconductance amplifier, the third amplifier includes a third NMOS tube, a fourth NMOS tube, a fifth NMOS tube, and a sixth NMOS tube, where a drain electrode of the third NMOS tube is connected to a drain electrode of the first PMOS tube and to a gate electrode of the fourth NMOS tube and a gate electrode of the fifth NMOS tube, a source electrode of the third NMOS tube is connected to a drain electrode of the fourth NMOS tube, and source electrodes of the fourth NMOS tube and the fifth NMOS tube are grounded; the drain electrode of the fifth NMOS tube is connected with the source electrode of the sixth NMOS tube, the grid electrode of the sixth NMOS tube and the grid electrode of the third NMOS tube are connected with bias voltage, and the drain electrode of the sixth NMOS tube is connected with the drain electrode of the second PMOS tube.
The first, second and third amplifiers used in the invention adopt the architecture of a current mirror amplifier, the output node of the first-stage common source difference is the low-impedance input of the current mirror, the gain of the noise of the grid control end and the power supply noise is close to 0dB, thus the common source device of the output stage of the transconductance amplifier approximately adopts the feedforward noise cancellation technology, and the good power supply inhibition performance is realized at the drain end of the common source device; the output stage adopts a cascode architecture, and the impedance of the output stage is improved, so that the power supply rejection performance of the output end of the transconductance amplifier is further improved;
furthermore, the substrate bias of the P-type cascode device is subjected to static voltage bias after filtering, so that the power supply inhibition performance can be improved;
In addition, the output end adopts a certain filter capacitor, and the capacitor not only plays a role in frequency compensation and increases stability, but also can further improve the power supply inhibition performance.
Drawings
FIG. 1 is a schematic diagram of a transconductance amplifier according to an embodiment of the present invention;
fig. 2 is a schematic diagram of a transconductance amplifier according to an embodiment of the present invention.
Detailed Description
The transconductance amplifier of the present invention will be described in more detail below in conjunction with the schematic drawings, wherein preferred embodiments of the present invention are shown, it being understood that one skilled in the art could modify the invention described herein while still achieving the advantageous effects of the invention. Accordingly, the following description is to be construed as broadly known to those skilled in the art and not as limiting the invention.
The invention is more particularly described by way of example in the following paragraphs with reference to the drawings. Advantages and features of the invention will become more apparent from the following description and from the claims. It should be noted that the drawings are in a very simplified form and are all to a non-precise scale, merely for convenience and clarity in aiding in the description of embodiments of the invention.
As shown in fig. 1 and 2, the main idea of the present invention is to provide a transconductance amplifier, comprising:
The first NMOS tube MN0 of the common source stage, the second NMOS tube MN1, the first PMOS tube MP0 of the common source common gate stage (cascode), the second PMOS tube MP1, the grid of the first NMOS tube connects the positive input terminal VINP, the grid of the second NMOS tube connects the negative input terminal VINN, the source of the first NMOS tube MN0 and the second NMOS tube MN1 connects the current source, the drain of the first NMOS tube MN0 connects one end of the first amplifier CM0, the other end of the first amplifier CM0 connects the source of the second PMOS tube MP1, the drain of the second NMOS tube MN1 connects one end of the second amplifier CM1, the other end of the second amplifier CM1 connects the source of the first PMOS tube MP0, the drain of the first PMOS tube MP0 connects one end of the third amplifier CM2, the other end of the third amplifier CM2 connects the output terminal VOUT, the drain of the second PMOS tube MP1 connects the output terminal.
In this way, the transconductance amplifier adopts the architecture of the mirror amplifier, the output nodes VP0 and VN0 are low-impedance inputs of the current mirror, and the gain of the output noise and the power supply noise is close to 0dB at this time, so that the common source devices (the fifth PMOS tube MP4 and the eighth PMOS tube MP7, which will be described below) of the output stage of the transconductance amplifier approximately adopt the feedforward noise cancellation technology, and good power supply rejection performance is obtained at the drain terminals VP1 and VN1 of the common source devices.
In addition, the first PMOS tube MP0 and the second PMOS tube MP1 of the output stage adopt a common-source common-gate architecture, and the impedance of the output end is improved, so that the power supply inhibition performance of the output end of the transconductance amplifier is improved.
For example, a supply rejection performance of about 30dB can be obtained at the output VOUT of the transconductance amplifier in the frequency range of 100 MHz.
Further, the gates of the first PMOS transistor MP0 and the second PMOS transistor MP1 are connected to a bias voltage VCSP, and the substrate bias of the first PMOS transistor MP0 and the substrate bias of the second PMOS transistor MP1 are static voltage bias after filtering. For example, the substrates of the first PMOS transistor MP0 and the second PMOS transistor MP1 are connected to a low-pass filter.
Through the application of the substrate filtering technology, the power supply rejection performance improvement of about 10dB can be obtained for the output end VOUT of the transconductance amplifier in the frequency range of 100 MHz.
Further, the output terminal VOUT is further provided with a filter capacitor C0. The filter capacitor C0 can also improve the power supply rejection performance.
In one embodiment, the capacitance of the capacitor C0 is greater than or equal to 1pF.
Referring specifically to fig. 2, the first amplifier CM0 includes a third PMOS transistor MP2, a fourth PMOS transistor MP3, and a fifth PMOS transistor MP4, where a drain of the third PMOS transistor MP2 is connected to a drain of the first NMOS transistor MN0, and is connected to a gate of the fourth PMOS transistor MP3 and a gate of the fifth PMOS transistor MP4, a source of the third PMOS transistor MP2 is connected to a drain of the fourth PMOS transistor MP3, a source of the fourth PMOS transistor MP3 and a source of the fifth PMOS transistor MP4 are connected to a power supply voltage, and a drain of the fifth PMOS transistor MP4 is connected to a source of the second PMOS transistor MP 1.
The second amplifier CM1 includes a sixth PMOS transistor MP5, a seventh PMOS transistor MP6, and an eighth PMOS transistor MP7, where a drain of the sixth PMOS transistor MP5 is connected to a drain of the second NMOS transistor MN1, and is connected to a gate of the seventh PMOS transistor MP6 and a gate of the eighth PMOS transistor MP7, a source of the sixth PMOS transistor MP5 is connected to a drain of the seventh PMOS transistor MP6, a source of the seventh PMOS transistor MP6 and a source of the eighth PMOS transistor MP7 are connected to a power supply voltage, and a drain of the eighth PMOS transistor MP7 is connected to a source of the first PMOS transistor MP 0.
Further, the gates of the third PMOS transistor MP2 and the sixth PMOS transistor MP5 are connected to a bias voltage VCSP, and substrate bias of the third PMOS transistor MP2 and the sixth PMOS transistor MP5 is a filtered static voltage bias.
For example, the substrates of the third PMOS transistor MP2 and the sixth PMOS transistor MP5 are connected to the low-pass filter.
Specifically, the substrates of the third PMOS transistor MP2, the sixth PMOS transistor MP5, the first PMOS transistor MP0 and the second PMOS transistor MP1 are connected to the same low-pass filter.
The third PMOS transistor MP2 and the sixth PMOS transistor MP5 are cascode devices, the third PMOS transistor MP2 and the fourth PMOS transistor MP3 form a cascode structure, and the sixth PMOS transistor MP5 and the seventh PMOS transistor MP6 form a cascode structure.
The third amplifier CM2 includes a third NMOS transistor MN2, a fourth NMOS transistor MN3, a fifth NMOS transistor MN4, and a sixth NMOS transistor MN5, where a drain of the third NMOS transistor MN2 is connected to a drain of the first PMOS transistor MP0 and to a gate of the fourth NMOS transistor MN3 and a gate of the fifth NMOS transistor MN4, a source of the third NMOS transistor MN2 is connected to a drain of the fourth NMOS transistor MN3, and a source of the fourth NMOS transistor MN3 and a source of the fifth NMOS transistor MN4 are grounded; the drain electrode of the fifth NMOS transistor MN4 is connected to the source electrode of the sixth NMOS transistor MN5, the gate electrode of the sixth NMOS transistor MN5 and the gate electrode of the third NMOS transistor MN2 are connected to the bias voltage VCSN, and the drain electrode of the sixth NMOS transistor MN5 is connected to the drain electrode of the second PMOS transistor MP 1.
The third NMOS transistor MN2 and the sixth NMOS transistor MN5 are cascode devices.
According to practical requirements, the first amplifier CM0, the second amplifier CM1 and the third amplifier CM2 may have different amplification ratios, for example, the input/output ratio may be 1: k is greater than or equal to 1. For example, the second amplifier CM1 shown in fig. 1 is 1: 1.
As can be seen from the above description, the transconductance amplifier of the present invention is not complicated in structure, and therefore, power consumption is improved. And under the condition of maintaining the structure and the power consumption, the power supply rejection performance is greatly improved, for example, the output end VOUT of the transconductance amplifier can obtain about 40dB of power supply rejection performance improvement in the frequency range of 100 MHz.
Practical experiments show that the positive power supply rejection ratio of more than 40dB can be achieved for all frequencies.
In summary, in the transconductance amplifier provided by the invention, the transconductance amplifier adopts the architecture of the current mirror amplifier, the output node of the first stage is the low-impedance input of the current mirror, and the gain of the output noise of the first stage (namely the noise of the gate control end) and the power supply noise is close to 0dB at the moment, so that the common source device of the output stage of the transconductance amplifier approximately adopts the feedforward noise cancellation technology, and the good power supply inhibition performance is realized at the drain end of the common source device; the output stage adopts a cascode architecture, and the impedance of the output stage is improved, so that the power supply rejection performance of the output end of the transconductance amplifier is further improved;
furthermore, the substrate bias of the P-type cascode device is subjected to static voltage bias after filtering, so that the power supply inhibition performance can be improved;
In addition, the output end adopts a certain filter capacitor, and the capacitor not only plays a role in frequency compensation and increases stability, but also can further improve the power supply inhibition performance.
It will be apparent to those skilled in the art that various modifications and variations can be made to the present invention without departing from the spirit or scope of the invention. Thus, it is intended that the present invention also include such modifications and alterations insofar as they come within the scope of the appended claims or the equivalents thereof.
Claims (7)
1. A transconductance amplifier, comprising:
The first NMOS tube and the second NMOS tube of the common source common gate, the grid electrode of the first NMOS tube is connected with the positive input end, the grid electrode of the second NMOS tube is connected with the negative input end, the source electrodes of the first NMOS tube and the second NMOS tube are connected with a current source, the drain electrode of the first NMOS tube is connected with one end of a first amplifier, the other end of the first amplifier is connected with the source electrode of the second PMOS tube, the drain electrode of the second NMOS tube is connected with one end of a second amplifier, the other end of the second amplifier is connected with the source electrode of the first PMOS tube, the drain electrode of the first PMOS tube is connected with one end of a third amplifier, the other end of the third amplifier is connected with the output end, and the drain electrode of the second PMOS tube is connected with the output end;
The first amplifier comprises a third PMOS tube, a fourth PMOS tube and a fifth PMOS tube, wherein the drain electrode of the third PMOS tube is connected with the drain electrode of the first NMOS tube and connected with the grid electrode of the fourth PMOS tube and the grid electrode of the fifth PMOS tube, the source electrode of the third PMOS tube is connected with the drain electrode of the fourth PMOS tube, the source electrodes of the fourth PMOS tube and the fifth PMOS tube are connected with power supply voltages, and the drain electrode of the fifth PMOS tube is connected with the source electrode of the second PMOS tube;
The second amplifier comprises a sixth PMOS tube, a seventh PMOS tube and an eighth PMOS tube, wherein the drain electrode of the sixth PMOS tube is connected with the drain electrode of the second NMOS tube and connected with the grid electrode of the seventh PMOS tube and the grid electrode of the eighth PMOS tube, the source electrode of the sixth PMOS tube is connected with the drain electrode of the seventh PMOS tube, the source electrodes of the seventh PMOS tube and the eighth PMOS tube are connected with a power supply voltage, and the drain electrode of the eighth PMOS tube is connected with the source electrode of the first PMOS tube;
The third amplifier comprises a third NMOS tube, a fourth NMOS tube, a fifth NMOS tube and a sixth NMOS tube, wherein the drain electrode of the third NMOS tube is connected with the drain electrode of the first PMOS tube and is connected with the grid electrode of the fourth NMOS tube and the grid electrode of the fifth NMOS tube, the source electrode of the third NMOS tube is connected with the drain electrode of the fourth NMOS tube, and the source electrodes of the fourth NMOS tube and the fifth NMOS tube are grounded; the drain electrode of the fifth NMOS tube is connected with the source electrode of the sixth NMOS tube, the grid electrode of the sixth NMOS tube and the grid electrode of the third NMOS tube are connected with bias voltage, and the drain electrode of the sixth NMOS tube is connected with the drain electrode of the second PMOS tube.
2. The transconductance amplifier of claim 1, wherein the substrate bias of the first PMOS transistor and the second PMOS transistor is a filtered quiescent voltage bias.
3. The transconductance amplifier of claim 2, wherein the substrates of the first PMOS transistor and the second PMOS transistor are connected to a low pass filter.
4. The transconductance amplifier of claim 3, wherein the substrates of the third PMOS transistor and the sixth PMOS transistor are connected to the low pass filter.
5. The transconductance amplifier of claim 1, wherein the output is further provided with a filter capacitor.
6. The transconductance amplifier of claim 5, wherein the capacitance of the capacitor is greater than or equal to 1pF.
7. The transconductance amplifier of claim 1, wherein the substrate bias of the third PMOS transistor and the sixth PMOS transistor is a filtered quiescent voltage bias.
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| CN201811283011.XA CN109167583B (en) | 2018-10-31 | 2018-10-31 | Transconductance amplifier |
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| CN201811283011.XA CN109167583B (en) | 2018-10-31 | 2018-10-31 | Transconductance amplifier |
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| CN109167583B true CN109167583B (en) | 2024-07-16 |
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| CN112506259B (en) * | 2020-11-12 | 2022-07-01 | 苏州大学 | CMOS reference voltage buffer with low output resistance |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN208956003U (en) * | 2018-10-31 | 2019-06-07 | 上海海栎创微电子有限公司 | Trsanscondutance amplifier |
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| CN101917168B (en) * | 2010-06-30 | 2013-02-27 | 西安电子科技大学 | High switching rate transconductance amplifier for active power factor corrector |
| CN102541146B (en) * | 2010-12-07 | 2013-12-18 | 上海华虹Nec电子有限公司 | Circuit for band-gap reference source for preventing leakage current of high-voltage metal oxide semiconductor (MOS) from increasing |
| CN102331809A (en) * | 2011-07-14 | 2012-01-25 | 复旦大学 | Current mirror circuit with grid leakage compensating function |
| CN102916666B (en) * | 2011-08-02 | 2015-09-09 | 中国科学院微电子研究所 | Broadband programmable gain amplifier |
| CN102916667B (en) * | 2011-08-02 | 2015-09-09 | 中国科学院微电子研究所 | Broadband programmable gain amplifier with 2dB step length |
| CN102611400B (en) * | 2012-02-09 | 2015-02-04 | 东南大学 | High-gain single-stage operational transconductance amplifier |
| CN104218904B (en) * | 2013-05-29 | 2017-06-06 | 上海华虹宏力半导体制造有限公司 | The Full differential operational amplifier of rail-to-rail input AB class outputs |
| CN103825557B (en) * | 2014-02-28 | 2017-01-11 | 电子科技大学 | Transconductance amplifier with low power consumption and high linearity |
| CN105187017B (en) * | 2015-09-07 | 2017-11-03 | 电子科技大学 | A kind of wideband amplification circuit |
| CN105227142B (en) * | 2015-09-25 | 2017-10-17 | 中国电子科技集团公司第二十四研究所 | A kind of low pressure Foldable cascade trsanscondutance amplifier |
| CN105720936B (en) * | 2016-01-21 | 2018-01-09 | 中国电子科技集团公司第二十四研究所 | A kind of trsanscondutance amplifier based on automatic biasing cascode structure |
| CN105720927B (en) * | 2016-01-21 | 2018-03-27 | 中国电子科技集团公司第二十四研究所 | A kind of frequency compensated trsanscondutance amplifier |
| CN106208992A (en) * | 2016-07-25 | 2016-12-07 | 天津大学 | A kind of operation transconductance amplifier being applied to Infrared Detectors circuit |
| CN107301308B (en) * | 2017-08-15 | 2023-08-15 | 苏州锴威特半导体股份有限公司 | Constant transconductance full-swing operational amplifier |
| CN108599731B (en) * | 2018-08-15 | 2024-07-19 | 广东工业大学 | Low-power-consumption broadband transconductance error amplifier |
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| CN208956003U (en) * | 2018-10-31 | 2019-06-07 | 上海海栎创微电子有限公司 | Trsanscondutance amplifier |
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