CN108959117A - H2D write operation accelerated method, device, computer equipment and storage medium - Google Patents
H2D write operation accelerated method, device, computer equipment and storage medium Download PDFInfo
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
- G06F12/023—Free address space management
- G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
- G06F12/0246—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory in block erasable memory, e.g. flash memory
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Abstract
The present invention relates to H2D write operation accelerated method, device, computer equipment and storage medium, this method includes the fifo queue designed for the storage address Flash；Obtain the H2D write order of Host host；It parses and handles H2D write order；In moving data to the buffer space of memory；The preset address Flash to be written is obtained out of fifo queue；It writes data into the address Flash to be written；Recycle the buffer space of memory.The present invention is lined up by the way that first in first out is arranged, the address Flash to be written of FTL algorithm acquisition is stored in advance, when hardware needs that data are written using the address Flash to be written, directly transfer the address Flash to be written, the address Flash to be written is provided in real time without waiting for FTL algorithm, has been simplified software operating procedure, has been greatly reduced CPU overhead, sufficiently release hardware performance, improves SSD write performance.
Description
Technical field
The present invention relates to H2D write operation methods, more specifically refer to that H2D write operation accelerated method, device, computer are set
Standby and storage medium.
Background technique
The method of existing H2D write order is as shown in Figure 1, include: hardware obtains H2D write order；The Wait Orders such as firmware (packet
Include inquiry or interrupt mode)；Firmware resolve command；Firmware application buffer space；It is (i.e. non-easy that firmware generates NVME PRD order
The PRD order of the property lost memory host controller interface specification) and it is handed down to the execution of NVME circuit；Firmware FTL algorithm generates to be written
The address Flash entered；NVME circuit is read in data deposit buffer area according to PRD order from host；The transmission of the pending datas such as firmware
It finishes and after FTL algorithm generates the address Flash to be written, generates NFC order and be simultaneously handed down to NFC circuit and execute；NFC circuit from
Buffer area reads data storage to the specified space Flash；The pending datas such as the firmware write-in space Flash finishes；Firmware recycling storage
The buffer space of device.Total 13 steps complete a host write order.Wherein having 6 steps is pure software behavior, 5 steps
It suddenly is software and hardware interaction, only 2 steps are pure hardware behaviors, since there are more software actions, cause CPU overhead big；It is soft
Hardware interaction is relatively more, and there are time overhead, hardware will wait software triggering just to start to work often, leads to H2D write operation
Efficiency is lower, and SSD readwrite performance is lower.
Therefore, it is necessary to design a kind of new method, realizing reduces CPU overhead, improves SSD write performance.
Summary of the invention
It is an object of the invention to overcome the deficiencies of existing technologies, H2D write operation accelerated method, device, computer are provided
Equipment and storage medium.
To achieve the above object, the invention adopts the following technical scheme: H2D write operation accelerated method, comprising:
Designed for storing the fifo queue of the address Flash；
Obtain the H2D write order of Host host；
It parses and handles H2D write order；
In moving data to the buffer space of memory；
The preset address Flash to be written is obtained out of fifo queue；
It writes data into the address Flash to be written；
Recycle the buffer space of memory.
Its further technical solution are as follows: designed for store the address Flash fifo queue the step of after, also wrap
It includes:
The address Flash being written into is stored in fifo queue.
Its further technical solution are as follows: the address Flash being written into is stored in the step in fifo queue, including
Step in detail below:
Judge whether the space of fifo queue has expired；
If it is not, then running FTL firmware algorithm, an address Flash to be written is generated；
The address the Flash indentation fifo queue being written into；
If so, return judge fifo queue space whether full step.
Its further technical solution are as follows: the step of parsing and handling H2D write order, comprising the following specific steps
Parse H2D write order；
Apply for the buffer space of memory, generates NVME PRD order, and be issued to NVME circuit.
Its further technical solution are as follows: after the step of obtaining the address Flash to be written out of fifo queue, also
Include:
NFC writing commands are generated, NFC circuit is handed down to.
The present invention also provides H2D write operation accelerators, include:
Design cell, for the fifo queue designed for the storage address Flash；
Acquiring unit, for obtaining the H2D write order of Host host；
Resolution unit, for parsing and handling H2D write order；
Unit is moved, in the buffer space for moving data to memory；
Address acquisition unit, for obtaining the preset address Flash to be written out of fifo queue；
Writing unit, for writing data into the address Flash to be written；
Recovery unit, for recycling the buffer space of memory.
Its further technical solution are as follows: described device further includes having:
Storage unit, the address Flash for being written into are stored in fifo queue.
Its further technical solution are as follows: the storage unit includes:
Judgment module, for judging whether the space of fifo queue has expired；
Address acquisition module, for providing the address Flash to be written if it is not, then obtaining FTL algorithm and continuing operation；
Address is pressed into module, and the address Flash for being written into is pressed into fifo queue.
The present invention also provides a kind of computer equipment, including memory, processor and it is stored on the memory simultaneously
The computer program that can be run on the processor, the processor realize above-mentioned side when executing corresponding computer program
Method.
The present invention also provides a kind of storage medium, the storage medium is stored with computer program, the computer journey
Sequence includes program instruction, and described program instruction makes the processor execute above-mentioned method when being executed by a processor.
Compared with the prior art, the invention has the advantages that: the hardware-accelerated method of H2D write operation of the invention passes through
Setting first in first out is lined up, and the address Flash to be written of FTL algorithm acquisition is stored in advance, when hardware is needed using to be written
When data are written in the address Flash, the address Flash to be written can be directly transferred, is provided in real time without waiting for FTL algorithm to be written
The address Flash, is isolated with fifo queue, reduces the coupling between software and hardware, is reduced software and hardware interaction, is mentioned
High respective operational efficiency, has simplified software operating procedure, has greatly reduced CPU overhead, sufficiently release hardware performance, improved
SSD write performance.
The invention will be further described in the following with reference to the drawings and specific embodiments.
Detailed description of the invention
Fig. 1 is the H2D write order operational flowchart of the prior art；
Fig. 2 is the schematic flow chart one for the H2D write operation accelerated method that a specific embodiment of the invention provides；
Fig. 3 is the schematic flow chart two for the H2D write operation accelerated method that a specific embodiment of the invention provides；
Fig. 4 is the sub-process schematic diagram for the H2D write operation accelerated method that Fig. 2 specific embodiment provides；
Fig. 5 is the sub-process schematic diagram for the H2D write operation accelerated method that Fig. 2 specific embodiment provides；
Fig. 6 is the schematic block diagram for the H2D write operation accelerator that a specific embodiment of the invention provides；
Fig. 7 is the schematic block diagram for the storage unit that a specific embodiment of the invention provides；
Fig. 8 is the schematic block diagram for the resolution unit that a specific embodiment of the invention provides；
Fig. 9 is a kind of schematic block diagram for computer equipment that a specific embodiment of the invention provides.
Specific embodiment
In order to more fully understand technology contents of the invention, combined with specific embodiments below to technical solution of the present invention into
One step introduction and explanation, but not limited to this.
It should be appreciated that ought use in this specification and in the appended claims, term " includes " and "comprising" instruction
Described feature, entirety, step, operation, the presence of element and/or component, but one or more of the other feature, whole is not precluded
Body, step, operation, the presence or addition of element, component and/or its set.
It is also understood that mesh of the term used in this present specification merely for the sake of description specific embodiment
And be not intended to limit the application.As present specification and it is used in the attached claims, unless on
Other situations are hereafter clearly indicated, otherwise " one " of singular, "one" and "the" are intended to include plural form.
It will be further appreciated that the term "and/or" used in present specification and the appended claims is
Refer to any combination and all possible combinations of one or more of associated item listed, and including these combinations.
The specific embodiment as shown in Fig. 2~9, H2D write operation accelerated method provided in this embodiment, device, computer
Equipment and storage medium can be used in solid-state storage, mobile storage and SSD master control, and realizing reduces CPU overhead, improves
SSD readwrite performance.
Referring to Fig. 2, Fig. 2 is the schematic flow for the H2D write operation accelerated method that a specific embodiment of the invention provides
Figure one；As shown in Fig. 2, the method comprising the steps of S101~S109:
S101, the fifo queue designed for storing the address Flash.
Specifically, which can be used for storing the address Flash of writable data, after the address Flash is stored in advance, with
It is to be called.It is arranged FIFO (i.e. fifo queue), plays a kind of effect of isolation, reduce the coupling between software and hardware
It closes, so that each self-operating of software and hardware, does not depend on mutually, to improve respective operational efficiency, improves the write operation of H2D
Energy.
S102, the address Flash being written into are stored in fifo queue.
The address Flash to be written that FTL algorithm operation generates is stored in advance in during first in first out lines up, this process is held
It is continuous to carry out, regardless of whether hardware components at this time are in the task of execution, that is, no matter whether S103~S109 step is executing, the row
Not interrupt, lining up to have stored in addition to the first in first out has expired the address Flash to be written, if having stored completely to be written
Then first suspend FTL when the address Flash to be written in the full fifo queue fails called in time in the address Flash
The storage of operation and the address Flash to be written, until have the address Flash to be written being stored in fifo queue start by
It calls, when vacating the address Flash to be written of space storage newly, starts to press against the address Flash to be written.As long as first in first out
Line up enough depths, step S101, the coupling of S102 and step S103~S109 will be very small, to realize that software and hardware are logical
FIFO isolation is crossed, mutual independent operating is not interfere with each other, and improves respective efficiency.
In one embodiment, as shown in figure 4, the step S102 may include step S1021~S1023:
S1021, judge whether the space of fifo queue has expired；
S1022, the address Flash to be written is provided if it is not, then obtaining FTL algorithm and continuing operation；
S1023, the address Flash being written into are pressed into fifo queue；
If so, into return step S1021.
In actual operation, after having executed S1023 step, it can be also back to S1021 step, it is lasting to judge.
The FTL algorithm of software continues operation, constantly provides the address Flash to be written, as long as hardware FIFO is discontented, holds
Continuous that the calculated address Flash is pressed into hardware FIFO, this movement of software has been independent on whether host write order, even if
Host does not have a write order, and software can still get out the address Flash to be written in advance and be placed on inside FIFO, for hardware circuit with
When obtain, to avoid hardware circuit that software real-time operation is waited to go out the address Flash, improve hardware execution efficiency, above-mentioned FTL
What is referred to is a kind of software middle layer, for flash memory simulation to be become Virtual Block Device.
When judging that FIFO has expired, it can continue to judge, wait FIFO discontented, then continue to be pressed into the address Flash.
S103, the H2D write order for obtaining Host host.
The specifically H2D write order of the NVMe hardware circuit acquisition Host host of SSD chip.
S104, parsing simultaneously handle H2D write order；
Order is delivered H2D hardware accelerator by NVMe hardware circuit, by accelerating module resolve command, and applies for one automatically
Block buffer space generates NVMe PRD order, is handed down to the execution of NVMe circuit.
In one embodiment, above-mentioned step S104 may include step S1041~S1042.
S1041, parsing H2D write order；
S1042, the buffer space for applying for memory generate NVME PRD order, and are issued to NVME circuit.
Hardware receives the write order of Host host, automatically parses, and applies for buffer space automatically, automatically generates NVME PRD
It orders and executes, whole process does not need software participation, can reduce the operating procedure of software, reduces CPU overhead, wherein NVME
PRD order is a kind of command format of Nonvolatile memory host controller interface specification, i.e. a logical device interface specification
A kind of command format.
S105, moving data to memory buffer space in.
After NVMe hardware circuit receives PRD order, data are moved to specified storage from Host host according to order request
In device buffer area, transmission one finishes signal and gives H2D hardware accelerator after end of transmission.
S106, the preset address Flash to be written is obtained out of fifo queue.
The existing FTL algorithm in the address Flash to be written, which calculates, to be obtained, and is ready in advance.H2D hardware accelerator receives
After finishing signal, an address Flash to be written is taken out from FIFO at once, this process foundation is first written, the rule first transferred
Then transfer the address Flash to be written.And the position of a storage address Flash to be written is then vacated in fifo queue at this time
It sets, can continue to be pressed into the address Flash to be written.When storing the address Flash to be written at this time, still according to centainly be sequentially written in
The address Flash is written, for example the address Flash to be written that need to currently store is stored in the 10th vacancy in fifo queue,
The first in first out lines up to amount to 12 vacancy, then the new address Flash to be written need to successively be stored in the 11st vacancy, the 12nd vacancy
Afterwards, then by the new address Flash to be written it is stored in the first vacancy, and so on.Software and hardware interactive interface is simplified, and only
One software and hardware interactive interface is fifo interface, and software can be pressed into a large amount of address Flash to be written in advance, and hardware needs
It is taken automatically when the address Flash, hardware need not wait software to calculate in real time and provide the address Flash, and hardware can ceaselessly be run,
Hardware performance is sufficiently released, achievees the purpose that improve SSD readwrite performance.
S107, NFC writing commands are generated, is handed down to NFC circuit；
After taking out the address Flash to be written, a NFC write order is generated by H2D hardware accelerator, is handed down to
NFC circuit.
S108, it writes data into the address Flash to be written.
After NFC circuit receives writing commands, data are taken out from specified storage buffer space, i.e. step S105 is deposited
Data in the storage buffer of storage write the data to the specified address Flash, transmit completion signal after the completion of write-in
Give H2D hardware accelerator.
S109, the buffer space for recycling memory.
After H2D hardware accelerator receives the completion signal from NFC, buffer space is recycled automatically, to next time
It uses.
In addition, being also possible to SATA circuit perhaps EMMC circuit or UFS circuit for above-mentioned NVME hardware circuit.
Referring to Fig. 3, as can be known from Fig. 3, only FTL firmware algorithm calculates the address Flash to be written and is pressed into FIFO
When need software to execute, remaining be hardware execute, largely reduced the execution content of software, to refer in same SSD performance
The lower requirement reduced to CPU operational capability of mark；Or it can be obtained higher under same CPU operational capability conversely speaking,
SSD readwrite performance, the especially write performance dependent on the SSD randomizer of CPU operational capability.
In the process of running, the address Flash and processing and the H2D write order of realization Host host to be written will be generated,
Two parallel independent processes are split as, and processing is realized by hardware circuit completely with the H2D write order for realizing Host host,
Firmware only generates the address Flash to be written, is isolated with fifo queue.
Above-mentioned H2D write operation accelerated method, by be arranged first in first out line up, be stored in advance FTL algorithm acquisition to
The address Flash is written, when hardware needs that data are written using the address Flash to be written, can directly transfer the Flash to be written
Address is provided the address Flash to be written without waiting for FTL algorithm in real time, is isolated with fifo queue, reduces software
Coupling between hardware reduces software and hardware interaction, improves respective operational efficiency, simplified software operating procedure, significantly
CPU overhead is reduced, sufficiently release hardware performance, improves SSD write performance.
Referring to Fig. 6, Fig. 6 is the schematic block diagram for the H2D write operation accelerator that a specific embodiment provides；Such as Fig. 6
Shown, H2D write operation accelerator includes:
Design cell 1, for the fifo queue designed for the storage address Flash.
Acquiring unit 3, for obtaining the H2D write order of Host host.
Resolution unit 4, for parsing and handling H2D write order.
Unit 5 is moved, in the buffer space for moving data to memory.
Address acquisition unit 6, for obtaining the address Flash to be written out of fifo queue.
Writing unit 8, for writing data into the address Flash to be written.
Recovery unit 9, for recycling the buffer space of memory.
In addition, above-mentioned device further includes having:
Storage unit 2, the address Flash for being written into are stored in fifo queue.
In one embodiment, referring to Fig. 7, above-mentioned storage unit 2 includes:
Judgment module 21, for judging whether the space of fifo queue has expired；
Address acquisition module 22, for providing the address Flash to be written if it is not, then obtaining FTL algorithm and continuing operation；
Address is pressed into module 23, and the address Flash for being written into is pressed into fifo queue.
In one embodiment, as shown in figure 8, above-mentioned resolution unit 4 includes:
Command analysis module 41, for parsing H2D write order；
Module 42 is applied in space, for applying for the buffer space of memory, generates NVME PRD order, and be issued to
NVME circuit.
In addition, above-mentioned device further includes having:
Transmitting order to lower levels unit 7 is handed down to NFC circuit for generating NFC writing commands.
Specifically, it above-mentioned acquiring unit 3 and moves unit 5 and is integrated in NVME hardware circuit, above-mentioned parsing list
Member 4, address acquisition unit 6, transmitting order to lower levels unit 7 and recovery unit 9 are integrated in above-mentioned H2D hardware accelerator；On
The writing unit 8 stated is integrated in above-mentioned NFC circuit；It can be seen that only FTL firmware algorithm is with calculating Flash to be written
Location and while being pressed into FIFO needs software to execute, remaining is that hardware executes, and largely reduced the execution content of software, thus same
The requirement to CPU operational capability is reduced under equal SSD performance indicator；It, can be with or conversely speaking, under same CPU operational capability
Higher SSD readwrite performance is obtained, the SSD random write performance of CPU operational capability is especially depended on.On it should be noted that
The H2D stated is host to equipment, and H2D write operation then indicates that host data is written in SSD equipment.
It should be noted that it is apparent to those skilled in the art that, above-mentioned H2D write operation accelerator
It, can be for convenience of description and simple with reference to the corresponding description in preceding method embodiment with the specific implementation process of each unit
Clean, details are not described herein.
Above-mentioned H2D write operation accelerator, by be arranged first in first out line up, be stored in advance FTL algorithm acquisition to
The address Flash is written, when hardware needs that data are written using the address Flash to be written, can directly transfer the Flash to be written
Address is provided the address Flash to be written without waiting for FTL algorithm in real time, is isolated with fifo queue, reduces software
Coupling between hardware reduces software and hardware interaction, improves respective operational efficiency, simplified software operating procedure, significantly
CPU overhead is reduced, sufficiently release hardware performance, improves SSD write performance.
Above-mentioned H2D write operation accelerator can be implemented as a kind of form of computer program, and computer program can be
It is run in computer equipment as shown in Figure 9.
Referring to Fig. 9, Fig. 9 is a kind of schematic block diagram of computer equipment provided by the embodiments of the present application.The computer
Equipment 700 can be terminal, be also possible to server, wherein terminal can be smart phone, tablet computer, laptop,
Desktop computer, personal digital assistant and wearable device etc. have the electronic equipment of communication function.Server can be independent
Server is also possible to the server cluster of multiple server compositions.
Refering to Fig. 9, which includes processor 720, memory and the net connected by system bus 710
Network interface 750, wherein memory may include non-volatile memory medium 730 and built-in storage 740.
The non-volatile memory medium 730 can storage program area 731 and computer program 732.The computer program 732
Including program instruction, which is performed, and processor 720 may make to execute a kind of H2D write operation accelerated method.
The processor 720 is for providing calculating and control ability, to support the operation of entire computer equipment 700.
The built-in storage 740 provides environment for the operation of the computer program 732 in non-volatile memory medium 730, should
When computer program 732 is executed by processor 720, processor 720 may make to execute a kind of H2D write operation accelerated method.
The network interface 750 is used to carry out network communication with other equipment.It will be understood by those skilled in the art that in Fig. 9
The structure shown, only the block diagram of part-structure relevant to application scheme, does not constitute and is applied to application scheme
The restriction of computer equipment 700 thereon, specific computer equipment 700 may include more more or fewer than as shown in the figure
Component perhaps combines certain components or with different component layouts.
Wherein, the processor 720 is for running computer program 732 stored in memory, to realize following step
It is rapid:
Designed for storing the fifo queue of the address Flash；
Obtain the H2D write order of Host host；
It parses and handles H2D write order；
In moving data to the buffer space of memory；
The preset address Flash to be written is obtained out of fifo queue；
It writes data into the address Flash to be written；
Recycle the buffer space of memory.
In one embodiment, processor 720 is realizing the fifo queue designed for the storage address Flash
After step, following steps are also realized:
The address Flash being written into is stored in fifo queue.
In one embodiment, the address Flash that processor 720 is written into described in the realization is stored in fifo queue
In step when, be implemented as follows step:
Judge whether the space of fifo queue has expired；
If it is not, then running FTL firmware algorithm, an address Flash to be written is generated；
The address the Flash indentation fifo queue being written into；
And return judge fifo queue space whether full step；
If so, return judge fifo queue space whether full step.
In one embodiment, processor 720 is specific real when the step of realizing the parsing and handling H2D write order
Existing following steps:
Parse H2D write order；
Apply for the buffer space of memory, generates NVME PRD order, and be issued to NVME circuit.
In one embodiment, processor 720 described obtains the address Flash to be written realizing out of fifo queue
The step of after, also realization following steps:
NFC writing commands are generated, NFC circuit is handed down to.
It should be appreciated that in the embodiment of the present application, processor 720 can be central processing unit (Central
Processing Unit, CPU), which can also be other general processors, digital signal processor (Digital
Signal Processor, DSP), specific integrated circuit (Application Specific Integrated Circuit,
ASIC), ready-made programmable gate array (Field-Programmable Gate Array, FPGA) or other programmable logic
Device, discrete gate or transistor logic, discrete hardware components etc..Wherein, general processor can be microprocessor or
Person's processor is also possible to any conventional processor etc..
Those of ordinary skill in the art will appreciate that be realize above-described embodiment method in all or part of the process,
It is that relevant hardware can be instructed to complete by computer program.The computer program includes program instruction, computer journey
Sequence can be stored in a storage medium, which is computer readable storage medium.The program instruction is by the department of computer science
At least one processor in system executes, to realize the process step of the embodiment of the above method.
A kind of above-mentioned computer equipment is lined up by the way that first in first out is arranged, and the to be written of FTL algorithm acquisition is stored in advance
The address Flash, when hardware needs that data are written using the address Flash to be written, with can directly transferring the Flash to be written
Location is provided the address Flash to be written without waiting for FTL algorithm in real time, is isolated with fifo queue, reduce software and
Coupling between hardware reduces software and hardware interaction, improves respective operational efficiency, simplified software operating procedure, dropped significantly
Low CPU overhead, sufficiently release hardware performance, improve SSD write performance.
Therefore, the present invention also provides a kind of storage mediums.The storage medium can be computer readable storage medium.This is deposited
Storage media is stored with computer program, and wherein computer program includes program instruction.The program instruction makes when being executed by processor
Processor executes following steps:
Designed for storing the fifo queue of the address Flash；
Obtain the H2D write order of Host host；
It parses and handles H2D write order；
In moving data to the buffer space of memory；
The preset address Flash to be written is obtained out of fifo queue；
It writes data into the address Flash to be written；
Recycle the buffer space of memory.
In one embodiment, the processor realizes described be arranged for storing Flash executing described program instruction
After the step of fifo queue of address, following steps are also realized:
The address Flash being written into is stored in fifo queue.
In one embodiment, the address Flash that processor is written into described in the realization is stored in fifo queue
The step of when, be implemented as follows step:
Judge whether the space of fifo queue has expired；
If it is not, then running FTL firmware algorithm, an address Flash to be written is generated；
The address the Flash indentation fifo queue being written into；
And return judge fifo queue space whether full step；
If so, return judge fifo queue space whether full step.
In one embodiment, processor is when the step of realizing the parsing and handling H2D write order, and specific implementation is such as
Lower step:
Parse H2D write order；
Apply for the buffer space of memory, generates NVME PRD order, and be issued to NVME circuit.
In one embodiment, processor described obtains the address Flash to be written realizing out of fifo queue
After step, following steps are also realized:
NFC writing commands are generated, NFC circuit is handed down to.
The storage medium can be USB flash disk, mobile hard disk, read-only memory (Read-Only Memory, ROM), magnetic disk
Or the various computer readable storage mediums that can store program code such as CD.
Those of ordinary skill in the art may be aware that list described in conjunction with the examples disclosed in the embodiments of the present disclosure
Member and algorithm steps, can be realized with electronic hardware, computer software, or a combination of the two, in order to clearly demonstrate hardware
With the interchangeability of software, each exemplary composition and step are generally described according to function in the above description.This
A little functions are implemented in hardware or software actually, the specific application and design constraint depending on technical solution.Specially
Industry technical staff can use different methods to achieve the described function each specific application, but this realization is not
It is considered as beyond the scope of this invention.
In several embodiments provided by the present invention, it should be understood that disclosed device and method can pass through it
Its mode is realized.For example, the apparatus embodiments described above are merely exemplary.For example, the division of each unit, only
Only a kind of logical function partition, there may be another division manner in actual implementation.Such as multiple units or components can be tied
Another system is closed or is desirably integrated into, or some features can be ignored or not executed.
The steps in the embodiment of the present invention can be sequentially adjusted, merged and deleted according to actual needs.This hair
Unit in bright embodiment device can be combined, divided and deleted according to actual needs.In addition, in each implementation of the present invention
Each functional unit in example can integrate in one processing unit, is also possible to each unit and physically exists alone, can also be with
It is that two or more units are integrated in one unit.
If the integrated unit is realized in the form of SFU software functional unit and when sold or used as an independent product,
It can store in one storage medium.Based on this understanding, technical solution of the present invention is substantially in other words to existing skill
The all or part of part or the technical solution that art contributes can be embodied in the form of software products, the meter
Calculation machine software product is stored in a storage medium, including some instructions are used so that a computer equipment (can be a
People's computer, terminal or network equipment etc.) it performs all or part of the steps of the method described in the various embodiments of the present invention.
It is above-mentioned that technology contents of the invention are only further illustrated with embodiment, in order to which reader is easier to understand, but not
It represents embodiments of the present invention and is only limitted to this, any technology done according to the present invention extends or recreation, by of the invention
Protection.Protection scope of the present invention is subject to claims.
Claims (10)
1.H2D write operation accelerated method characterized by comprising
Designed for storing the fifo queue of the address Flash；
Obtain the H2D write order of Host host；
It parses and handles H2D write order；
In moving data to the buffer space of memory；
The preset address Flash to be written is obtained out of fifo queue；
It writes data into the address Flash to be written；
Recycle the buffer space of memory.
2. H2D write operation accelerated method according to claim 1, which is characterized in that be arranged for storing the address Flash
After the step of fifo queue, further includes:
The address Flash being written into is stored in fifo queue.
3. H2D write operation accelerated method according to claim 2, which is characterized in that the address the Flash storage being written into
Step in fifo queue, comprising the following specific steps
Judge whether the space of fifo queue has expired；
If it is not, then running FTL firmware algorithm, an address Flash to be written is generated；
The address the Flash indentation fifo queue being written into；
If so, return judge fifo queue space whether full step.
4. H2D write operation accelerated method according to any one of claims 1 to 3, which is characterized in that parse and handle H2D
The step of write order, comprising the following specific steps
Parse H2D write order；
Apply for the buffer space of memory, generates NVME PRD order, and be issued to NVME circuit.
5. H2D write operation accelerated method according to claim 1, which is characterized in that out of fifo queue obtain to
After the step of address Flash of write-in, further includes:
NFC writing commands are generated, NFC circuit is handed down to.
6.H2D write operation accelerator, which is characterized in that include:
Design cell, for the fifo queue designed for the storage address Flash；
Acquiring unit, for obtaining the H2D write order of Host host；
Resolution unit, for parsing and handling H2D write order；
Unit is moved, in the buffer space for moving data to memory；
Address acquisition unit, for obtaining the preset address Flash to be written out of fifo queue；
Writing unit, for writing data into the address Flash to be written；
Recovery unit, for recycling the buffer space of memory.
7. H2D write operation accelerator according to claim 6, which is characterized in that described device further includes having:
Storage unit, the address Flash for being written into are stored in fifo queue.
8. H2D write operation accelerator according to claim 7, which is characterized in that the storage unit includes:
Judgment module, for judging whether the space of fifo queue has expired；
Address acquisition module, for providing the address Flash to be written if it is not, then obtaining FTL algorithm and continuing operation；
Address is pressed into module, and the address Flash for being written into is pressed into fifo queue.
9. a kind of computer equipment, which is characterized in that including memory, processor and be stored on the memory and can be in institute
The computer program run on processor is stated, the processor realizes such as claim 1 to 5 when executing corresponding computer program
Any one of described in method.
10. a kind of storage medium, which is characterized in that the storage medium is stored with computer program, the computer program packet
Program instruction is included, described program instruction executes the processor such as any one of claim 1-5
The method.
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