CN108918552A - A kind of failure analysis localization method - Google Patents
A kind of failure analysis localization method Download PDFInfo
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- CN108918552A CN108918552A CN201810619924.8A CN201810619924A CN108918552A CN 108918552 A CN108918552 A CN 108918552A CN 201810619924 A CN201810619924 A CN 201810619924A CN 108918552 A CN108918552 A CN 108918552A
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- target area
- failure analysis
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- dot pattern
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
- G01N21/00—Investigating or analysing materials by the use of optical means, i.e. using sub-millimetre waves, infrared, visible or ultraviolet light
- G01N21/84—Systems specially adapted for particular applications
- G01N21/88—Investigating the presence of flaws or contamination
- G01N21/95—Investigating the presence of flaws or contamination characterised by the material or shape of the object to be examined
- G01N21/956—Inspecting patterns on the surface of objects
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Abstract
The invention discloses a kind of failure analysis localization methods, belong to the technology of semiconductor field, including：A target area is arranged in the repetitive structure region in advance in step S1；A dot pattern is arranged on the chip under test surface centered on the target area in step S2, and the area and the distance between the composition point and the target area of the composition point in the dot pattern are positively correlated；Step S3 carries out failure analysis to the target area to position the failpoint in the target area, positions the target area according to the dot pattern before carrying out the failure analysis.The beneficial effect of the technical solution is：The time that the present invention can reduce crawl failpoint improves the efficiency of failure analysis to be rapidly performed by failure analysis, realizes quick positioning and analysis to the failpoint in the repetitive structure region on chip.
Description
Technical field
The present invention relates to a kind of technology of semiconductor field, specifically a kind of failure analysis localization method.
Background technique
Failure analysis refers to after product failure through the system research to product and its structure, use and technological document,
To identify failure mode, the process that failure cause, mechanism and failure develop is determined.Integrated circuit in development, produce and make
It can all fail in, the defect in design production can be found by failure analysis.
The electric property failure analysis (EFA, Electrical Failure Analysis) of chip is in failure analysis
Important component.
At present the EFA location technology of mainstream include EMMI (Emission Microscope, low-light microscope) technology and
OBIRCH (Optical Beam Induce Resistance Change, the test of light beam inductive material resistance variations area) technology.
EMMI technology is using in the presence of leaking electricity, puncturing, in the semiconductor devices of hot carrier's effect, and failpoint hesitates
Electroluminescent process and generate luminescence phenomenon.These photon streams are by collecting and enhancing, using optical transition and image procossing,
Obtain a luminescent image, the Optical Reflected Image of luminescent image and device surface be superimposed, can to failpoint and defect into
Row positioning.
OBIRCH technology can be measured change in resistance of the different materials after crossing laser beam flying.With laser beam flying device
Surface, the component energy of laser beam are converted into heat and are absorbed by device such as metal interconnecting wires.If in interconnection line existing defects or
Person is empty, and the heat conduction near these failed areas is different from other intact regions, and the heat of failed areas cannot lead to rapidly
It crosses conducting wire conduction to scatter, which results in the raisings of failed areas local temperature.It, will be thermally-induced according to the temperature-coefficient of electrical resistance of material
Resistance variations and current/voltage variation it is associated, it is corresponding with the pixel intensity being imaged changing current/voltage, it is final to obtain
Failure positioning is carried out to OBIRCH picture.It can be with short circuit/electric leakage in effective position metal interconnecting wires, sky using OBIRCH technology
Hole and high resistance area.
But with being continuously increased for the raising of chip integration and metal layer, in imaging a hot spot contains up to a hundred
A even more transistor, by OBIRCH technology and EMMI technology come the process for accurately positioning failpoint it is complicated and
It is cumbersome, it requires a great deal of time.
Summary of the invention
The present invention In view of the above shortcomings of the prior art, proposes a kind of failure analysis localization method.The present invention is preparatory
One dot pattern is set around the target area of chip surface, can quickly be positioned according to the composition point in dot pattern
Target area improves failure analysis so as to reduce the time of crawl failpoint to be rapidly performed by failure analysis
Efficiency, realize to the failpoint in the repetitive structure region on chip it is quick positioning and analysis.
The present invention is achieved by the following technical solutions：
The present invention relates to a kind of failure analysis localization methods, wherein suitable for the repetitive structure region of chip under test, tool
Body includes the following steps：
A target area is arranged in the repetitive structure region in advance in step S1；
A dot pattern, the dot matrix is arranged on the chip under test surface centered on the target area in step S2
The area and the distance between the composition point and the target area of composition point in figure are positively correlated；
Step S3 carries out failure analysis to the target area to position the failpoint in the target area, is carrying out
The target area is positioned according to the dot pattern before the failure analysis.
Preferably, failure analysis localization method, wherein the composition point in the dot pattern constitutes several and is in
The belt-like zone of linear, each belt-like zone starting point are the target area.
Preferably, failure analysis localization method, wherein the dot pattern includes two orthogonal described band-like
Region.
Preferably, failure analysis localization method, wherein the area edge of the composition point in each belt-like zone
Be gradually increased away from the direction of the target area.
Preferably, failure analysis localization method, wherein between the adjacent composition point in each belt-like zone
Distance be gradually increased along away from the direction of the target area.
Preferably, the failure analysis localization method, wherein the quantity of the composition point in the dot pattern with it is described
The area of target area is negatively correlated.
Preferably, failure analysis localization method, wherein the composition point prints on the core to be measured by a laser
Piece surface.
Preferably, failure analysis localization method, wherein the shape of the composition point is rectangle or circle.
Preferably, failure analysis localization method, wherein in the step S3, by EMMI technology to the target
Region carries out the failure analysis.
Preferably, failure analysis localization method, wherein in the step S3, by OBIRCH technology to the mesh
It marks region and carries out the failure analysis.
The beneficial effect of above-mentioned technical proposal is：
A dot pattern is arranged in the present invention around the target area of chip surface in advance, according to the group in dot pattern
Target area can be quickly positioned at point, so as to reduce the time of crawl failpoint, to be rapidly performed by failure
Analysis, improves the efficiency of failure analysis, realizes the quick positioning to the failpoint in the repetitive structure region on chip
With analysis.
Detailed description of the invention
Fig. 1 is a kind of failure analysis localization method flow diagram in preferred embodiment of the invention；
Fig. 2 is the composition schematic diagram of dot pattern in preferred embodiment of the invention；
In figure：1 repetitive structure region, 2 target areas, 3 composition points.
Specific embodiment
Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention carries out clear, complete
Site preparation description, it is clear that described embodiments are only a part of the embodiments of the present invention, instead of all the embodiments.It is based on
Embodiment in the present invention, those of ordinary skill in the art without creative labor it is obtained it is all its
His embodiment, shall fall within the protection scope of the present invention.
It should be noted that in the absence of conflict, the feature in embodiment and embodiment in the present invention can phase
Mutually combination.
The present invention will be further explained below with reference to the attached drawings and specific examples, but not as the limitation of the invention.
As shown in Figure 1, the present embodiment is related to a kind of failure analysis localization method.
Failure analysis localization method of the invention is suitable for the repetitive structure region 1 of chip under test, specifically includes following
Step：
A target area 2 is arranged in the repetitive structure region 1 in advance in step S1.
There is the region of the structure of a large amount of same or similar shape to be known as repetitive structure region 1 on the surface of chip.?
When repetitive structure region 1 carries out failure analysis, it is difficult to be positioned to the region for having failpoint.
A target area 2, multiple target areas 2 are set in repetitive structure region 1 in advance.It is usual in target area 2
It include failpoint.
The shape of target area 2 can there are many shapes, and in the present embodiment, target area 2 is rectangle, can be convenient fast
Speed divides and target area 2 is arranged.
A dot pattern, the dot matrix is arranged on the chip under test surface centered on the target area 2 in step S2
The area and the distance between the composition point 3 and the target area 2 of composition point 3 in figure are positively correlated.
Composition point 3 in dot pattern can be rectangle or circle.In the present embodiment, composition point 3 is circle.
Dot pattern has various shapes, as the position difference in chip surface of each composition point 3 can be formed not
Similar shape.No matter there is any shape, it can be according to the arrangement rule of composition point 3 come the target area 2 at the centre of location.
As shown in Fig. 2, being set to dot pattern on chip under test surface centered on target area 2.
The top of target area 2 is arranged three composition points 3, three composition points 3 of top point-blank, with target area
Domain 2 forms a linear belt-like zone, starting point of the target area 2 as the belt-like zone.
The right side of target area 2 is arranged three composition points 3, three composition points 3 on right side point-blank, with target area
Domain 2 forms a linear belt-like zone, starting point of the target area 2 as the belt-like zone.
In preferred embodiment, the lower section and left side of target area 2 also are provided with composition point 3.
Dot pattern is collectively constituted positioned at the top of target area 2 and the composition point 3 on right side, for being target area 2
Positioning.The left side of target area 2 and the composition point 3 of top have separately constituted a ribbon region, two ribbon regions of composition
It is mutually perpendicular to.
The area of the composition point 3 in each belt-like zone along away from the target area 2 direction gradually
Increase.When composition point 3 is round, the area of composition point 3 is directly reacted diametrically, at three of the right side of target area 2
The diameter of composition point 3 is respectively D1、D2And D3, D1、D2And D3It is sequentially increased i.e. D1< D2< D3.Above target area 2
The diameter characteristic having the same of composition point 3.
The adjacent composition point the distance between 3 in each belt-like zone is along away from the target area 2
Direction is gradually increased.The distance between first composition point 3 of target area 2 and right side is L1, distance between adjacent composition point 3
It is followed successively by L2And L3, then the three composition points 3 in the survey of target area 2 right side meet L1< L2< L3。
The quantity of the composition point 3 and the area of the target area 2 in the dot pattern are negatively correlated.Work as target
When region 2 is larger, then dot pattern can be constituted with less biggish composition point 3.When target area 2 is smaller, then need
More smaller composition points 3 constitute dot pattern, so that the more easily positioning of target area 2.
All composition points 3 can quickly be printed by laser.
Step S3, to the target area 2 carry out failure analysis to position the failpoint in the target area 2, into
The target area 2 is positioned according to the dot pattern before the row failure analysis.
Failure analysis is carried out to target area 2, can be carried out using EMMI technology or OBIRCH technology.Pass through failure point
Analysis is to obtain the failpoint in target area 2.
The region for needing to carry out failure analysis can be accurately found under lower enlargement ratio by dot pattern,
Without gradually finding failpoint by gradually increasing enlargement ratio.To improve the efficiency of failure analysis.
Failure analysis localization method of the invention, compared with prior art：
A dot pattern is arranged in the present invention around the target area of chip surface in advance, according to the group in dot pattern
Target area can be quickly positioned at point, so as to reduce the time of crawl failpoint, to be rapidly performed by failure
Analysis, improves the efficiency of failure analysis, realizes the quick positioning to the failpoint in the repetitive structure region on chip
With analysis.
The foregoing is merely preferred embodiments of the present invention, are not intended to limit embodiments of the present invention and protection model
It encloses, to those skilled in the art, should can appreciate that all with made by description of the invention and diagramatic content
Equivalent replacement and obviously change obtained scheme, should all be included within the scope of the present invention.
Claims (10)
1. a kind of failure analysis localization method, which is characterized in that suitable for the repetitive structure region of chip under test, specifically include
Following steps：
A target area is arranged in the repetitive structure region in advance in step S1；
A dot pattern, the dot pattern is arranged on the chip under test surface centered on the target area in step S2
In composition point area and the distance between the composition point and the target area be positively correlated；
Step S3 carries out failure analysis to position the failpoint in the target area, described in progress to the target area
The target area is positioned according to the dot pattern before failure analysis.
2. failure analysis localization method according to claim 1, which is characterized in that
The composition point in the dot pattern constitutes several linear belt-like zones, and each belt-like zone rises
Point is the target area.
3. failure analysis localization method according to claim 2, which is characterized in that
The dot pattern includes two orthogonal belt-like zones.
4. failure analysis localization method according to claim 2, which is characterized in that
The area of the composition point in each belt-like zone is gradually increased along the direction away from the target area.
5. failure analysis localization method according to claim 2, which is characterized in that
In each belt-like zone it is adjacent it is described composition point the distance between along away from the target area direction by
It is cumulative big.
6. failure analysis localization method according to claim 1, which is characterized in that
The quantity of the composition point and the area of the target area in the dot pattern are negatively correlated.
7. failure analysis localization method according to claim 1, which is characterized in that
The composition point prints on the chip surface to be measured by a laser.
8. failure analysis localization method according to claim 1, which is characterized in that
The shape of the composition point is rectangle or circle.
9. failure analysis localization method according to claim 1, which is characterized in that
In the step S3, the failure analysis is carried out to the target area by EMMI technology.
10. failure analysis localization method according to claim 1, which is characterized in that
In the step S3, the failure analysis is carried out to the target area by OBIRCH technology.
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| CN201810619924.8A CN108918552A (en) | 2018-06-14 | 2018-06-14 | A kind of failure analysis localization method |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2022033158A1 (en) * | 2020-08-14 | 2022-02-17 | 长鑫存储技术有限公司 | Wafer level failure analysis sample production method |
| US11835492B2 (en) | 2020-08-14 | 2023-12-05 | Changxin Memory Technologies, Inc. | Method for preparing sample for wafer level failure analysis |
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| CN103267661A (en) * | 2013-04-28 | 2013-08-28 | 上海华力微电子有限公司 | Positioning method for SEM/TEM sample |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2022033158A1 (en) * | 2020-08-14 | 2022-02-17 | 长鑫存储技术有限公司 | Wafer level failure analysis sample production method |
| US11835492B2 (en) | 2020-08-14 | 2023-12-05 | Changxin Memory Technologies, Inc. | Method for preparing sample for wafer level failure analysis |
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Application publication date: 20181130 |