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CN108878419B - Semiconductor structure and forming method thereof - Google Patents

Semiconductor structure and forming method thereof Download PDF

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CN108878419B
CN108878419B CN201710321841.6A CN201710321841A CN108878419B CN 108878419 B CN108878419 B CN 108878419B CN 201710321841 A CN201710321841 A CN 201710321841A CN 108878419 B CN108878419 B CN 108878419B
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interlayer dielectric
substrate
forming
dummy gate
dielectric layer
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CN108878419A (en
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周飞
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
    • H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
    • H01L27/0629—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with diodes, or resistors, or capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823431—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823481—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure

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  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

A semiconductor structure and a forming method thereof are provided, wherein the forming method comprises the following steps: providing a substrate, wherein the substrate comprises a high-resistance device area, and the high-resistance device area consists of a device area and an edge area; forming discrete dummy gates on the substrate in the device region and the edge region; forming an interlayer dielectric film on the substrate exposed out of the dummy gate, wherein the interlayer dielectric film covers the top of the dummy gate; and flattening the interlayer dielectric film to expose the residual interlayer dielectric film at the top of the dummy gate, wherein the residual interlayer dielectric film is used as the interlayer dielectric layer. Compared with the scheme without forming the virtual dummy gate, the method can improve the top flatness of the interlayer dielectric layer and improve the top sinking (sinking) problem of the interlayer dielectric layer in the subsequent planarization process for forming the interlayer dielectric layer, thereby being beneficial to improving the performance of the semiconductor structure.

Description

Semiconductor structure and forming method thereof
Technical Field
The present invention relates to the field of semiconductor manufacturing, and more particularly, to a semiconductor structure and a method for forming the same.
Background
In semiconductor manufacturing, integrated circuit feature sizes continue to decrease with the trend toward very large scale integrated circuits. To accommodate the reduction in feature size, the channel length of MOSFET devices has also been correspondingly shortened. However, as the channel length of the device is shortened, the distance between the source and the drain of the device is also shortened, so that the control capability of the gate to the channel is deteriorated, the difficulty of the gate voltage to pinch off the channel is increased, and the sub-threshold leakage (SCE) phenomenon, so-called short-channel effect (SCE), is easier to occur.
Therefore, in order to better accommodate the reduction of feature sizes, semiconductor processing is gradually beginning to transition from planar MOSFET transistors to three-dimensional transistors with higher power efficiency, such as fin field effect transistors (finfets). In the FinFET, the gate can control the ultrathin body (fin part) at least from two sides, the control capability of the gate on a channel is much stronger than that of a planar MOSFET device, and the short channel effect can be well inhibited; and compared with other devices, the FinFET has better compatibility of the existing integrated circuit manufacturing technology.
In the FinFET, a resistance Device (Resistor Device) is used in large quantities. Currently, with the introduction of metal gate (MetalGate), in order to reduce the process difficulty and the process cost, a metal layer is generally formed on an interlayer dielectric layer above an isolation structure as a metal resistor device.
However, the process of forming the metal resistance device is liable to cause a degradation in the performance of the semiconductor structure.
Disclosure of Invention
The invention provides a semiconductor structure and a forming method thereof, which can optimize the performance of the semiconductor structure.
To solve the above problems, the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate, wherein the substrate comprises a high-resistance device area, and the high-resistance device area consists of a device area and an edge area; forming discrete dummy gates on the substrate in the device region and the edge region; forming an interlayer dielectric film on the substrate exposed out of the virtual dummy gate, wherein the interlayer dielectric film covers the top of the virtual dummy gate; and flattening the interlayer dielectric film to expose the residual interlayer dielectric film out of the top of the virtual pseudo gate, wherein the residual interlayer dielectric film is used as an interlayer dielectric layer.
Optionally, after the forming of the interlayer dielectric layer, the method further includes: removing the virtual pseudo gate at the edge region, and forming an opening in the interlayer dielectric layer; forming a dummy metal gate filling the opening; and forming a metal layer on the interlayer dielectric layer in the device region.
Optionally, an extending direction of the metal layer is perpendicular to an extending direction of the dummy gate.
Optionally, the metal layer is doped with N ions or C ions.
Optionally, the metal layer is made of one or more of TiN, TaN, TiCN, or TiC.
Optionally, the thickness of the metal layer is
Figure BDA0001290018300000021
To
Figure BDA0001290018300000022
Optionally, after the metal layer is formed, the method further includes: and forming a conductive plug electrically connected with the metal layer.
Optionally, the distance between the device region and the edge region is 5nm to 2000 nm.
Optionally, the base includes a substrate and a plurality of discrete fins on the substrate, and the substrate includes a high-resistance device region.
Accordingly, the present invention also provides a semiconductor structure comprising: the device comprises a substrate, a first electrode, a second electrode and a third electrode, wherein the substrate comprises a high-resistance device area which consists of a device area and an edge area; the dummy gate is positioned on the substrate of the device region and the edge region; and the interlayer dielectric layer is positioned on the substrate exposed out of the virtual dummy gate, and the top of the interlayer dielectric layer exposed out of the virtual dummy gate is flush.
Compared with the prior art, the technical scheme of the invention has the following advantages:
compared with the scheme that the virtual dummy gate is not formed, the method can improve the top flatness of the interlayer dielectric layer and improve the top sinking (sinking) problem of the interlayer dielectric layer in the subsequent planarization process of forming the interlayer dielectric layer, thereby being beneficial to improving the performance of the semiconductor structure.
In an alternative, after the forming of the interlayer dielectric layer, forming a metal layer on the interlayer dielectric layer in the device region, where an extending direction of the metal layer is perpendicular to an extending direction of the dummy gate, so as to avoid a crosstalk Effect (Cross Talk Effect) between the metal layer and the dummy gate.
In an alternative scheme, after the interlayer dielectric layer is formed, a virtual metal gate is adopted to replace a virtual dummy gate of the edge region; in the semiconductor manufacturing, a metal gate of a transistor is usually formed, and the dummy metal gate in the edge region is replaced by a dummy metal gate, so that the metal gate and the dummy metal gate can be formed in the same step, the planarization effect in the metal gate forming process is further improved, and the problem of top depression of the metal gate is solved.
In the alternative, the dummy gate of the device region is not replaced by a dummy metal gate, so that the electromagnetic interference (e.g., inductance effect) of the metal layer can be reduced.
Drawings
Fig. 1 to 12 are schematic structural diagrams corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention.
Detailed Description
As is known from the background art, the process of forming the metal resistor device is liable to cause the performance degradation of the semiconductor structure. The reason for analyzing the performance degradation of the semiconductor structure is:
currently, a discrete Metal layer is usually formed on an interlayer dielectric layer above the isolation structure as a Metal Resistor Device (Metal Resistor Device). When the interlayer dielectric layer is formed, because the region corresponding to the isolation structure is a sparse region (Iso Area), after the planarization treatment of the interlayer dielectric layer is formed, the flatness of the top of the interlayer dielectric layer is poor, and the top of the interlayer dielectric layer is prone to have a sinking problem, so that the performance of the semiconductor structure is reduced.
In order to solve the technical problem, the invention forms the discrete dummy gates on the substrate in the device region and the marginal region, and compared with the scheme of not forming the dummy gates, the invention can improve the top flatness of the interlayer dielectric layer after planarization treatment and improve the problem of top depression of the interlayer dielectric layer.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 1 to 12 are schematic structural diagrams corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention.
Referring to fig. 1 and 2 in combination, fig. 1 is a top view, and fig. 2 is a schematic cross-sectional view taken along line A1a2 of fig. 1, providing a substrate (not shown) including a high-resistance device region (not shown) composed of a device region i and an edge region ii.
In this embodiment, the base includes a substrate 100 and a plurality of discrete fins 110 on the substrate 100, and the substrate 100 includes a high-resistance device region.
The high Resistance Device region is used for forming a Metal Resistance Device (Metal Resistance Device). Specifically, the metal resistance device is formed on the device region I.
In this embodiment, the fin portion 110 is formed on the high resistance device region substrate 100, and the fin portion 110 of the high resistance device region is used to increase a Pattern Density (Pattern Density) of the high resistance device region, so that compared with a scheme in which the fin portion 110 is not formed on the high resistance device region substrate 100, when an interlayer dielectric layer is formed on the isolation structure 111 subsequently, a top recess problem of the interlayer dielectric layer after planarization processing can be improved, thereby increasing the top flatness of the interlayer dielectric layer.
It should be noted that the substrate 100 further includes a transistor region (not shown) for forming a fin field effect transistor, and the fin 110 of the transistor region is used for providing a channel of the formed fin field effect transistor.
In this embodiment, the substrate 100 is a silicon substrate. In other embodiments, the material of the substrate can also be germanium, silicon carbide, gallium arsenide, or indium gallium, and the substrate can also be a silicon-on-insulator substrate or a germanium-on-insulator substrate.
The material of the fin 110 is the same as the material of the substrate 100. In this embodiment, the fin 110 is made of silicon. In other embodiments, the material of the fin may also be germanium, silicon carbide, gallium arsenide, or indium gallium arsenide.
In this embodiment, in order to make the process environments at the two sides of the device region i the same or similar, so as to improve the planarization effect, the edge regions ii are located at the two sides of the device region i.
It should be noted that, as shown in fig. 1, in this embodiment, the number of the fins 110 on the device region i and the edge region ii is illustrated as 4 (for convenience of illustration, 3 fins 110 are illustrated in the device region i and the edge region ii in fig. 2). However, the number of fins 110 in the device region i and the edge region ii is not limited by the present invention.
The distance between the device region I and the edge region II is not too small or too large. If the distance is too small, the top of the interlayer dielectric layer at the side of the edge region II, which is far away from the device region I, is easy to be sunken; and if the distance is too large, the top of the interlayer dielectric layer between the edge region II and the device region I is easy to have a sinking problem. For this purpose, in the present embodiment, the distance between the device region i and the edge region ii is 5nm to 2000 nm.
Referring to fig. 2 in combination, after providing the substrate, the method further includes the steps of: an isolation structure 111 is formed on the substrate 100, the isolation structure 111 covers a portion of the sidewall of the fin 110, and the top of the isolation structure 111 is lower than the top of the fin 110.
The isolation structure 111 serves as an isolation structure of a semiconductor device, and is used for isolating adjacent devices and also used for isolating adjacent fins 110.
In this embodiment, the isolation structure 111 is made of silicon oxide. In other embodiments, the material of the isolation structure may also be silicon nitride or silicon oxynitride.
Referring to fig. 3 to 6 in combination, fig. 3 is a top view based on fig. 1, fig. 4 is a schematic cross-sectional structure of fig. 3 along a B1B2 cut line (3 fins are illustrated in each of the device region and the edge region), fig. 5 is a schematic cross-sectional structure of fig. 3 along a C1C2 cut line (only 2 dummy gates are illustrated), fig. 6 is a schematic cross-sectional structure of fig. 3 along a D1D2 cut line (only 2 dummy gates are illustrated), and a discrete dummy gate 120 is formed on a substrate (not labeled) of the device region i and the edge region ii.
The dummy gate 120 is used to increase the pattern density (pattern density) of the high-resistance device region (not labeled), and compared with a scheme in which the dummy gate 120 is not formed, when an interlayer dielectric layer is formed on the isolation structure 111 in the following step, the problem of top recess of the interlayer dielectric layer after planarization processing can be improved, so that the top flatness of the interlayer dielectric layer is improved.
In this embodiment, the metal resistor device is formed on the interlayer dielectric layer in the device region i, and in order to reduce electromagnetic interference (for example, an inductance effect) of the metal resistor device, the dummy gate 120 is made of polysilicon.
The process compatibility of the polysilicon material is high, so that the introduction of the dummy gate 120 can be prevented from generating adverse effects on the performance of the formed semiconductor structure.
Specifically, the dummy gate 120 crosses over the fin 110 and covers a portion of the top surface and the sidewall surface of the fin 110. The virtual dummy gates 120 of the device region i and the edge region ii are separated from each other, so that the subsequent process treatment can be conveniently performed on the virtual dummy gates 120 of the device region i and the edge region ii respectively.
It should be noted that the substrate 100 further includes a fin field effect transistor region (not shown), so that the dummy gate 120 also crosses the fin 110 of the transistor region in the step of forming the dummy gate 120.
The dummy gate 120 of the transistor region occupies a space for a metal gate (MetalGate) of a fin field effect transistor to be formed later.
Referring to fig. 7 and 8 in combination, fig. 7 is a schematic cross-sectional structure based on fig. 5, fig. 8 is a schematic cross-sectional structure based on fig. 6, an interlayer dielectric film is formed on the substrate (not labeled) exposed by the dummy gate 120, and the interlayer dielectric film covers the top of the dummy gate 120; and flattening the interlayer dielectric film to expose the residual interlayer dielectric film out of the top of the dummy gate 120, wherein the residual interlayer dielectric film is used as an interlayer dielectric layer 130.
The interlayer dielectric layer 130 provides a process platform for the subsequent formation of a metal gate of the fin field effect transistor, provides a process platform for the formation process of the metal resistor device, and is also used for isolating adjacent devices.
In this embodiment, the top of the interlayer dielectric layer 130 is flush with the top of the dummy gate 120.
The interlayer dielectric layer 130 is made of an insulating material. The interlayer dielectric layer 130 may be made of silicon oxide, silicon nitride, silicon oxynitride or silicon oxycarbonitride. In this embodiment, the interlayer dielectric layer 130 is made of silicon oxide.
In this embodiment, the planarization process employs a Chemical Mechanical Polishing (CMP) process.
It should be noted that the fin portion 110 and the dummy gate 120 crossing the fin portion 110 are formed on the substrate 100 in the high resistance device region (not shown), so that the pattern density of the high resistance device region is high, the top recess problem of the interlayer dielectric layer 130 in the high resistance device region after the planarization process can be improved, and the top flatness of the interlayer dielectric layer 130 can be improved.
With reference to fig. 9 to 11, fig. 9 is a schematic cross-sectional structure based on fig. 8, fig. 10 is a schematic cross-sectional structure based on fig. 9, and fig. 11 is a schematic cross-sectional structure based on fig. 7, and after forming the interlayer dielectric layer 130, the method further includes: removing the dummy gate 120 (shown in fig. 8) in the edge region ii (shown in fig. 9), and forming an opening 121 (shown in fig. 9) in the interlayer dielectric layer 130; forming a dummy metal gate 122 (shown in fig. 10) filling the opening 121; a metal layer 140 (shown in fig. 11) is formed on the interlayer dielectric layer 130 in the device region i (shown in fig. 11).
In this embodiment, in the step of removing the dummy gate 120 in the edge region ii, the dummy gate 120 in the transistor region is also removed, and the opening 121 is also formed in the interlayer dielectric layer 130 in the transistor region; that is, in the same step, the dummy gates 120 in the transistor region and the edge region ii are removed.
Specifically, the process for removing the dummy gate 120 in the transistor area and the edge area ii is a wet etching process.
In other embodiments, a dry etching process or a combination of a dry etching process and a wet etching process may be further employed to remove the dummy gates in the transistor region and the edge region.
Accordingly, in the step of forming the dummy metal gate 122, a metal gate is also formed in the opening 121 of the transistor region.
The metal gate is used for controlling the opening and the truncation of the channel of the formed fin field effect transistor.
Specifically, the step of forming the metal gate and the dummy metal gate 122 includes: forming a metal material layer filling the opening 121, wherein the metal material layer covers the top of the interlayer dielectric layer 130; and performing planarization treatment on the metal material layer, removing the metal material layer higher than the top of the interlayer dielectric layer 130, wherein the remaining metal material layer in the transistor area opening 121 serves as a metal gate, and the remaining metal material layer in the edge area ii opening 121 serves as a dummy metal gate 122.
Wherein, the material of the metal material layer can be W, Al, Cu, Ag, Au, Pt, Ni or Ti.
In this embodiment, the planarization process employs a chemical mechanical polishing process.
By adopting the virtual metal gate 122 to replace the dummy gate 120 in the edge region ii, the metal material layer in the edge region ii is also subjected to planarization processing in the process of forming the metal gate, so that the planarization processing effect in the process of forming the metal gate is improved.
In addition, the dummy gate 120 of the device region i is not replaced by the dummy metal gate 122, so that electromagnetic interference (e.g., inductance effect) of the subsequently formed metal layer 140 can be reduced.
In this embodiment, the metal layer 140 is used as a metal resistor device.
The resistivity target value of the metal resistance device is determined according to actual process requirements. In this embodiment, the resistivity target value of the metal resistor device is 600 ohm/square to 700 ohm/square.
In order to reduce the resistivity of the metal resistor device, the metal layer 140 has doping ions therein, wherein the doping ions are N ions or C ions, and the higher the doping concentration of the doping ions is, the smaller the resistivity is. Specifically, the doping concentration of the doping ions is reasonably controlled according to the target value of the resistivity of the metal resistance device.
In this embodiment, the material of the metal layer 140 is one or more of TiN, TaN, TiCN, and TiC.
The thickness of the metal layer 140 is determined according to actual process requirements, so that the resistivity of the metal resistor device reaches a target value. In this embodiment, the thickness of the metal layer 140 is
Figure BDA0001290018300000081
To
Figure BDA0001290018300000082
It should be noted that the metal layer 140 is formed on the interlayer dielectric layer 130 in the device region i, and in order to avoid a crosstalk Effect (Cross Talk Effect) between the metal layer 140 and the dummy gate 120 in the device region i, an extending direction of the metal layer 140 is perpendicular to an extending direction of the dummy gate 120.
Referring to fig. 12 in combination, fig. 12 is a schematic cross-sectional structure diagram based on fig. 11, and after the metal layer 140 is formed, the method further includes the steps of: a conductive plug 150 electrically connected to the metal layer 140 is formed.
The conductive plugs 150 are used to electrically connect the high resistance device regions and also to electrically connect the devices to external circuits. In this embodiment, the contact plug 150 is made of a metal material such as W, Al, Cu, Ag, or Au.
Correspondingly, the invention also provides a semiconductor structure.
Referring collectively to fig. 3, 4, 7, and 8, the semiconductor structure includes:
a substrate (not labeled), wherein the substrate comprises a high-resistance device region (not labeled), and the high-resistance device region consists of a device region I and a marginal region II; the dummy gate 120 is positioned on the substrate of the device region I and the edge region II; and the interlayer dielectric layer 130 is positioned on the substrate exposed out of the virtual dummy gate 120, and the interlayer dielectric layer 130 is exposed out of the top of the virtual dummy gate 120.
In this embodiment, the base includes a substrate 100 and a plurality of discrete fins 110 on the substrate 100, and the substrate 100 includes a high-resistance device region.
The high Resistance Device region is used for forming a Metal Resistance Device (Metal Resistance Device). Specifically, the metal resistance device is formed on the device region I.
It should be noted that the substrate 100 further includes a transistor region (not shown) for forming a fin field effect transistor, and the fin 110 of the transistor region is used for providing a channel of the formed fin field effect transistor.
It should be noted that, as shown in fig. 1, in this embodiment, the number of the fins 110 on the device region i and the edge region ii is taken as an example to be described (for convenience of illustration, 3 fins 110 are illustrated in the device region i and the edge region ii in fig. 4, respectively). However, the number of fins 110 in the device region i and the edge region ii is not limited by the present invention.
In this embodiment, the high resistance device region substrate 100 has the fin portion 110 and the dummy gate 120, and the fin portion 110 and the dummy gate 120 in the high resistance device region are used to improve the pattern density (pattern density) of the high resistance device region; compared with the scheme that the fin portion 110 and the dummy gate 120 are not arranged on the substrate 100 in the high-resistance device region, the method for forming the interlayer dielectric layer 130 can improve the top depression problem of the interlayer dielectric layer 130 after the planarization treatment, so that the top flatness of the interlayer dielectric layer 130 is improved.
In this embodiment, in order to make the process environments at the two sides of the device region i the same or similar, so as to improve the planarization effect, the edge regions ii are located at the two sides of the device region i.
The distance between the device region I and the edge region II is not too small or too large. If the distance is too small, the top of the interlayer dielectric layer 130 at the side of the edge region II, which is far away from the device region I, is easy to have a sinking problem; if the distance is too large, the top of the interlayer dielectric layer 130 between the edge region II and the device region I is prone to have a recess problem. For this purpose, in the present embodiment, the distance between the device region i and the edge region ii is 5nm to 2000 nm.
In this embodiment, a metal resistor is formed on the interlayer dielectric layer 130 in the device region i, and in order to reduce electromagnetic interference (e.g., inductance effect) of the metal resistor, the dummy gate 120 is made of polysilicon.
The process compatibility of the polysilicon material is high, so that the introduction of the dummy gate 120 can be prevented from generating adverse effects on the performance of the formed semiconductor structure.
The interlayer dielectric layer 130 provides a process platform for forming a metal gate of the fin field effect transistor, provides a process platform for forming a metal resistor device, and is used for isolating adjacent devices.
In this embodiment, the top of the interlayer dielectric layer 130 is flush with the top of the dummy gate 120.
In this embodiment, the semiconductor structure further includes: and an isolation structure 111 located on the substrate 100, wherein the isolation structure 111 covers a part of the sidewall of the fin 110, and the top of the isolation structure 111 is lower than the top of the fin 110.
The isolation structure 111 serves as an isolation structure of the semiconductor device, and is used for isolating adjacent devices and also used for isolating adjacent fins 110.
For the specific description of the semiconductor structure, please refer to the corresponding description in the foregoing forming method, and details are not repeated herein.
According to the invention, the discrete dummy gates 120 are formed on the substrate of the device region I and the edge region II, so that the top flatness of the interlayer dielectric layer 130 after planarization treatment is improved, and the problem of top depression of the interlayer dielectric layer 130 is solved.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims (8)

1. A method of forming a semiconductor structure, comprising:
providing a substrate, wherein the substrate comprises a substrate and a plurality of discrete fin parts positioned on the substrate, the substrate comprises a high-resistance device area, and the high-resistance device area consists of a device area and an edge area;
forming a plurality of discrete dummy gates on the substrate in the device region and the edge region respectively; a dummy gate formed on the substrate of the device region and crossing each fin part on the device region and covering part of the top surface and the side wall surface of the fin part; the dummy gate is formed on the substrate of the edge region, spans each fin part on the edge region, and covers part of the top surface and the side wall surface of the fin part;
forming an interlayer dielectric film on the substrate exposed out of the virtual dummy gate, wherein the interlayer dielectric film covers the top of the virtual dummy gate;
carrying out planarization treatment on the interlayer dielectric film to enable the residual interlayer dielectric film to be exposed out of the top of the virtual pseudo gate, wherein the residual interlayer dielectric film is used as an interlayer dielectric layer;
after the interlayer dielectric layer is formed, removing the virtual dummy gate at the edge region, and forming an opening in the interlayer dielectric layer;
forming a dummy metal gate filling the opening;
and forming a metal layer on the interlayer dielectric layer in the device region.
2. The method of forming a semiconductor structure of claim 1, wherein an extending direction of the metal layer is perpendicular to an extending direction of the dummy gate.
3. The method of claim 1, wherein the metal layer is doped with N ions or C ions.
4. The method of claim 1, wherein a material of the metal layer is one or more of TiN, TaN, TiCN, and TiC.
5. The method of forming a semiconductor structure of claim 1, wherein the metal layer has a thickness of
Figure FDA0002571091480000011
To
Figure FDA0002571091480000012
6. The method of forming a semiconductor structure of claim 1, further comprising, after forming the metal layer, the steps of: and forming a conductive plug electrically connected with the metal layer.
7. The method of forming a semiconductor structure of claim 1, wherein a spacing between the device region and the edge region is 5nm to 2000 nm.
8. A semiconductor structure, comprising:
the substrate comprises a substrate and a plurality of discrete fin parts positioned on the substrate, wherein the substrate comprises a high-resistance device area, and the high-resistance device area consists of a device area and an edge area;
a plurality of discrete dummy gates respectively located on the substrate in the device region and the edge region; a dummy gate formed on the substrate of the device region and crossing each fin part on the device region and covering part of the top surface and the side wall surface of the fin part; the dummy gate is formed on the substrate of the edge region, spans each fin part on the edge region, and covers part of the top surface and the side wall surface of the fin part;
the interlayer dielectric layer is positioned on the substrate exposed out of the virtual dummy gate, and the interlayer dielectric layer is exposed out of the top of the virtual dummy gate;
and forming a metal layer on the interlayer dielectric layer in the device region.
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CN102208349A (en) * 2010-03-29 2011-10-05 格罗方德半导体公司 Method of manufacturing finned semiconductor device structure
CN104681557A (en) * 2013-11-28 2015-06-03 中国科学院微电子研究所 Semiconductor device and method for manufacturing the same
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