CN108831881B - Vertically stacked multi-chip packaging structure with cavity and manufacturing method thereof - Google Patents

Abstract

The invention discloses a vertically stacked multi-chip packaging structure with a cavity and a manufacturing method thereof, wherein the packaging structure comprises: a package substrate having a chamber; the functional chip is arranged in the cavity, the first upper surface of the functional chip and the upper surface of the substrate are positioned on the same side, and the first upper surface is provided with a plurality of first electrodes; the filter chip is arranged above the packaging substrate, the second lower surface of the filter chip is arranged face to face with the upper surface of the substrate, and the second lower surface is provided with a plurality of second electrodes; and the interconnection structures are used for conducting the first electrodes and the second electrodes. According to the invention, two different chips are packaged on the same packaging substrate by using a packaging technology, so that high integration of multiple chips can be realized; the filter chips and the functional chips are distributed up and down, and the filter chips above the packaging substrate do not occupy the space of the packaging substrate, so that the utilization rate of the packaging substrate can be further improved, and the interconnection structure is simplified; the functional chip is embedded in the cavity, so that the packaging structure is lighter and thinner.

Description

Up and down stacked multi-chip packaging structure with chamber and manufacturing method thereof

Technical Field

The present invention relates to the field of semiconductor packaging, and in particular to an up-and-down stacked multi-chip packaging structure with a cavity and a manufacturing method thereof.

Background technique

To cater to the development trend of increasingly thin and light electronic products, filters, RF transmitting components and receiving components need to be highly integrated in a packaging structure with limited area to form a system-in-package (SIP) structure to reduce the size of the hardware system.

Regarding the packaging integration technology of filters and RF front-end modules in the system-level packaging structure, there are still many technical problems in the industry that need to be solved urgently, such as the protection structure of the filter, the connection structure between multiple chips, the layout of multiple chips, etc.

Summary of the invention

The object of the present invention is to provide a top-and-bottom stacked multi-chip packaging structure with a cavity and a manufacturing method thereof.

To achieve one of the above-mentioned purposes of the invention, an embodiment of the present invention provides a top-to-bottom stacked multi-chip packaging structure with a cavity, comprising:

A packaging substrate, comprising an upper substrate surface and a lower substrate surface which are arranged opposite to each other, wherein the packaging substrate has a cavity;

A functional chip is disposed in the chamber, wherein the functional chip has a first upper surface and a first lower surface that are disposed opposite to each other, the first upper surface and the upper surface of the substrate are located on the same side, and the first upper surface has a plurality of first electrodes;

A filter chip is disposed above the packaging substrate, the filter chip has a second upper surface and a second lower surface that are disposed opposite to each other, the second lower surface is disposed face to face with the upper surface of the substrate, and the second lower surface has a plurality of second electrodes;

A plurality of interconnection structures are used to conduct a plurality of first electrodes and a plurality of second electrodes.

As a further improvement of an embodiment of the present invention, the filter chip is located above the chamber, and a plurality of first electrodes and a plurality of second electrodes are arranged face to face.

As a further improvement of an embodiment of the present invention, one side of the lower surface of the substrate has a plurality of external pins, the packaging substrate has a plurality of through holes, and the interconnection structure conducts the first electrode, the second electrode and the external pins through the through holes.

As a further improvement of an embodiment of the present invention, the through hole and the second electrode are spaced apart from each other.

As a further improvement of one embodiment of the present invention, the interconnection structure includes a metal column, solder and an electroplating layer structure, the metal column is connected to the bottom of the second electrode, the electroplating layer structure conducts the first electrode, and the electroplating layer structure extends through the through hole to the bottom of the packaging substrate to conduct the external pin, and the solder is used to conduct the metal column and the electroplating layer structure.

As a further improvement of one embodiment of the present invention, the electroplating layer structure includes an upper redistribution layer, an intermediate wiring layer and a lower redistribution layer that are interconnected, the upper redistribution layer is located above the packaging substrate and is conductive to the first electrode, the lower redistribution layer is located below the packaging substrate and is conductive to the external pin, the intermediate wiring layer includes a first electroplating layer located on the upper surface of the substrate, a second electroplating layer located on the inner wall of the through hole, and a third electroplating layer located on the lower surface of the substrate, the first electroplating layer is connected to the upper redistribution layer, and the third electroplating layer is connected to the lower redistribution layer.

As a further improvement of one embodiment of the present invention, a first insulating layer is arranged between the upper redistribution layer and the upper surface of the substrate and the first upper surface, and the multi-chip packaging structure also includes a cofferdam, which cooperates with the second lower surface and the upper surface of the first insulating layer to form a cavity.

As a further improvement of one embodiment of the present invention, the cofferdam includes a first cofferdam located on the inner side of the plurality of second electrodes and a second cofferdam located on the outer side of the plurality of second electrodes, the first cofferdam cooperates with the second lower surface and the upper surface of the first insulating layer to form a cavity, and the second cofferdam extends away from the first cofferdam until the outer edge of the second cofferdam is flush with the outer edge of the packaging substrate, and the second cofferdam exposes the through hole.

As a further improvement of one embodiment of the present invention, the multi-chip packaging structure also includes a first plastic packaging layer located on the side of the packaging substrate away from the lower surface of the substrate, the first plastic packaging layer simultaneously covers the exposed upper surface area of the second cofferdam and the filter chip, and the first plastic packaging layer fills the through hole.

As a further improvement of one embodiment of the present invention, the multi-chip packaging structure includes a first lower redistribution layer connected to the third electroplating layer, a second insulating layer located between the first lower redistribution layer and the lower surface of the substrate, a third insulating layer covering the second insulating layer and the first lower redistribution layer, a second lower redistribution layer that conducts through holes in the third insulating layer and extends toward the lower surface of the third insulating layer, and a fourth insulating layer covering the third insulating layer and the second lower redistribution layer, the external pins are connected to the second lower redistribution layer, and the fourth insulating layer exposes the external pins.

As a further improvement of an embodiment of the present invention, a second plastic packaging layer is provided on the gap between the functional chip and the chamber, the lower surface of the substrate and the first lower surface, and the first upper surface is flush with the upper surface of the substrate.

To achieve one of the above-mentioned purposes of the invention, an embodiment of the present invention provides a method for manufacturing a top-to-bottom stacked multi-chip package structure with a cavity, characterized in that it comprises the steps of:

S1: providing a packaging substrate, which has a substrate upper surface and a substrate lower surface arranged opposite to each other;

S2: forming a cavity on the packaging substrate;

S3: providing a functional chip, wherein the functional chip has a first upper surface and a first lower surface arranged opposite to each other, and the first upper surface has a plurality of first electrodes;

S4: loading the functional chip into the chamber, wherein the first upper surface and the upper surface of the substrate are located on the same side;

S5: forming a first interconnection structure on the packaging substrate, wherein the first interconnection structure is connected to the first electrode;

S6: providing a filter chip, wherein the filter chip has a second upper surface and a second lower surface that are oppositely arranged, and the second lower surface has a plurality of second electrodes;

S7: Mounting the filter chip on the packaging substrate, disposing the second lower surface face to face with the upper surface of the substrate, and forming a second interconnection structure that conducts the second electrode and the first interconnection structure;

S8: forming external pins on the second interconnect structure.

As a further improvement of an embodiment of the present invention, step S4 specifically includes:

Providing a temporary bonding plate;

Laminating the upper surface of the package substrate to a temporary laminating plate;

Loading the functional chip into the chamber, wherein the first upper surface and the upper surface of the substrate are located on the same side;

forming a second plastic sealing layer covering the gap between the functional chip and the chamber, the lower surface of the substrate and the first lower surface;

removing the temporary bonding plate;

Forming a plurality of through holes on the packaging substrate, wherein the through holes penetrate the second plastic packaging layer;

inverting the packaging substrate;

Step S5 specifically includes:

Forming a first electroplating layer on the upper surface of the substrate, forming a second electroplating layer on the inner wall of the through hole, and forming a third electroplating layer on the second plastic sealing layer;

forming a first insulating layer on the upper surface of the substrate, the first upper surface, and above the first electroplating layer;

Forming an upper rewiring layer above the first insulating layer, which is connected to the first electrode and the first electroplating layer through holes in the first insulating layer;

Arranging a light-sensitive insulating film above the first insulating layer and the upper redistribution layer;

Exposure and development form a cofferdam, wherein the cofferdam includes a first cofferdam and a second cofferdam, the outer edge of the second cofferdam is flush with the outer edge of the packaging substrate, the second cofferdam exposes the through hole, and a groove is formed between the first cofferdam and the second cofferdam;

Steps S7 and S8 specifically include:

forming a metal column on the lower surface of the second electrode;

Setting solder in the slot;

The filter chip is mounted on the packaging substrate, the second lower surface is arranged face to face with the upper surface of the substrate, the first cofferdam cooperates with the second lower surface and the upper surface of the first insulating layer to enclose and form a cavity, the metal column is aligned with the slot, and the solder is connected to the metal column;

Forming a first plastic encapsulation layer on a side of the packaging substrate away from the lower surface of the substrate, the first plastic encapsulation layer simultaneously covering the upper surface area of the second cofferdam exposed to the outside and the filter chip, and the first plastic encapsulation layer fills the through hole;

forming a second insulating layer below the third electroplating layer and the second plastic sealing layer;

Forming a first lower redistribution layer below the second insulating layer, which is connected to the third electroplating layer through holes in the second insulating layer;

forming a third insulating layer below the first lower redistribution layer and the second insulating layer;

Forming a second lower redistribution layer below the third insulating layer and connecting to the first lower redistribution layer through holes on the third insulating layer;

forming a fourth insulating layer covering the third insulating layer and the second lower redistribution layer, wherein the fourth insulating layer exposes the second lower redistribution layer;

A ball grid array is formed on the second lower redistribution layer exposed to the outside.

Compared with the prior art, the beneficial effects of the present invention are as follows: an embodiment of the present invention utilizes packaging technology to package two different chips in the same packaging substrate, which can achieve high integration of multiple chips, improve the utilization rate of the packaging substrate, and further achieve miniaturization of the multi-chip packaging structure; in addition, the filter chip and the functional chip are distributed up and down, and the filter chip located above the packaging substrate does not occupy the space of the packaging substrate, which can further improve the utilization rate of the packaging substrate, and the spacing between the filter chip and the functional chip becomes smaller, which facilitates the interconnection between the filter chip and the functional chip and simplifies the interconnection structure; moreover, the functional chip is embedded in the cavity, making the multi-chip packaging structure lighter and thinner.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG1 is a radio frequency front-end module according to an example of the present invention;

FIG2 is a radio frequency front-end module according to another example of the present invention;

3 is a cross-sectional view of a multi-chip package structure according to an embodiment of the present invention;

4 is a schematic diagram of a cofferdam, a through hole and a second electrode according to an embodiment of the present invention;

5 is a step diagram of a method for manufacturing a multi-chip package structure according to an embodiment of the present invention;

6a to 6z-19 are flow charts of a method for manufacturing a multi-chip packaging structure according to an embodiment of the present invention.

Detailed ways

The present invention will be described in detail below in conjunction with the specific embodiments shown in the accompanying drawings. However, these embodiments do not limit the present invention, and any structural, methodological, or functional changes made by a person skilled in the art based on these embodiments are all within the scope of protection of the present invention.

In various drawings of the present application, for the convenience of illustration, some sizes of structures or parts are exaggerated relative to other structures or parts, and thus, are only used to illustrate the basic structure of the subject matter of the present application.

In addition, terms such as "upper", "above", "lower", "below", etc. used herein to indicate spatial relative positions are used for the purpose of convenience to describe the relationship of one unit or feature relative to another unit or feature as shown in the accompanying drawings. Terms of spatial relative position may be intended to include different orientations of the device in use or operation other than the orientation shown in the drawings. For example, if the device in the figure is turned over, the unit described as being "below" or "beneath" other units or features will be located "above" the other units or features. Therefore, the exemplary term "below" can encompass both the above and below orientations. The device may be oriented in other ways (rotated 90 degrees or other orientations), and the spatially related descriptors used herein interpreted accordingly.

1 and 2 , an embodiment of the present invention provides a universal radio frequency front-end module, which can be used in mobile devices such as mobile phones and computers or other electronic devices.

In conjunction with Figure 1, in one example, the RF front-end module includes a power amplifier module 200 (Power Amplifier Module, PAM), and the power amplifier module 200 includes a first amplifier unit 201, a first RF switch unit 202 and a first RF filter unit 203 electrically connected in sequence, and the first amplifier unit 201 is a multi-mode-wide bandwidth power amplifier unit.

In actual operation, the first amplifier unit 201 is used to receive the modulated signal output by other components, and after being modulated, amplified and filtered by the power amplifier module 200 , the modulated signal is output by the filter unit 203 .

In combination with Figure 2, in another example, the RF front-end module includes a receive diversity module 300 (Receive Diversity Module, RDM), and the receive diversity module 300 includes a low noise amplifier multiplexer 301 (LNA Multiplexer Module, LMM), a second RF filter unit 302 and an RF antenna switch unit 303 electrically connected in sequence, wherein the low noise amplifier multiplexer 301 includes an electrically connected second amplifier unit 3011 and a second RF switch unit 3012, the second amplifier unit 3011 is a multi-mode-wide bandwidth low noise amplifier unit, and the two ends of the second RF switch unit 3012 are respectively connected to the second amplifier unit 3011 and the second RF filter unit 302.

In actual operation, the signal is divided into a high-frequency signal and a low-frequency signal through the antenna duplexer 304. Here, taking the high-frequency signal as an example, the high-frequency signal enters the RF antenna switch unit 303, and then passes through the filtering, modulation, and amplification operations of the second RF filter unit 302 and the low-noise amplifier multiplexer 301 in sequence, and is output by the second amplifier unit 3011.

It can be understood that the electrical connection between the above-mentioned RF switch unit, filter unit, amplifier unit and other units can be achieved through a packaging process, that is, the RF switch chip, amplifier chip, filter chip and the like are packaged together to achieve various functions.

This embodiment uses the packaging structure and process of an RF switch chip, an amplifier chip, and a filter chip as examples for explanation.

3 is a cross-sectional view of a top-and-bottom stacked multi-chip package structure 100 with a cavity according to an embodiment of the present invention.

The multi-chip package structure 100 includes a package substrate 10 , a functional chip 20 , a filter chip 30 and a plurality of interconnect structures 50 .

The packaging substrate 10 has a substrate upper surface 11 and a substrate lower surface 12 which are oppositely disposed, and the packaging substrate 10 has a cavity 101 .

Here, the packaging substrate 10 is a carrier board for carrying the chip. The packaging substrate 10 may be a printed circuit board made of organic resin, or a glass substrate, a ceramic substrate, or the like.

The chamber 101 may be a through hole penetrating the packaging substrate 10 , but is not limited thereto.

The function chip 20 is disposed in the chamber 101 . The function chip 20 has a first upper surface 21 and a first lower surface 22 that are oppositely disposed. The first upper surface 21 and the substrate upper surface 11 are located on the same side, and the first upper surface 21 has a plurality of first electrodes 211 .

The first electrode 211 protrudes out of the first upper surface 21 in a direction away from the first lower surface 22 , but the present invention is not limited thereto.

The function chip 20 is an amplifier chip or an RF switch chip, but is not limited thereto.

The filter chip 30 is disposed above the packaging substrate 10 . The filter chip 30 has a second upper surface 31 and a second lower surface 32 that are opposite to each other. The second lower surface 32 is disposed face to face with the substrate upper surface 11 , and has a plurality of second electrodes 321 .

The second electrode 321 protrudes out of the second lower surface 32 in a direction away from the second upper surface 31 , but the present invention is not limited thereto.

The filter chip 30 can be a surface acoustic wave filter chip (SAW) or a bulk acoustic wave filter chip (BAW), but is not limited to this. The active area (Active Zone) on the surface of the filter chip 30 needs to be free from contact or coverage by foreign objects in order to work normally. In other words, a cavity needs to be formed under the filter chip 30 to protect the active area.

The interconnection structures 50 are used to conduct the first electrodes 211 and the second electrodes 321 .

Here, “a plurality of interconnection structures 50 for conducting a plurality of first electrodes 211 and a plurality of second electrodes 321 ” refers to electrical connection between the first electrodes 211 and the second electrodes 321 , that is, interconnection between the filter chip 30 and the functional chip 20 is realized.

This embodiment utilizes packaging technology to package two different chips (filter chip 30 and functional chip 20) into the same packaging substrate 10, which can achieve high integration of multiple chips, improve the utilization rate of the packaging substrate 10, and further realize the miniaturization of the multi-chip packaging structure 100.

In addition, the filter chip 30 and the functional chip 20 are distributed up and down. The filter chip 30 located above the packaging substrate 10 does not occupy the space of the packaging substrate 10, which can further improve the utilization rate of the packaging substrate 10. The spacing between the filter chip 30 and the functional chip 20 becomes smaller, which facilitates the interconnection between the filter chip 30 and the functional chip 20 and simplifies the interconnection structure.

Furthermore, the functional chip 20 is embedded in the cavity 101 , making the multi-chip package structure 100 thinner and lighter.

It should be noted that, in the multi-chip packaging structure 100 of the present embodiment, a filter chip 30 and a functional chip 20 are loaded on the packaging substrate 10 as an example. It can be understood that in actual application, referring to Figures 1 and 2, it can include multiple filter chips 30 and multiple functional chips 20. For example, multiple functional chips 20 can be electrically connected around the filter chip 30 (including the three-dimensional directions of up, down, front, back, left and right).

In this embodiment, the filter chip 30 is located above the chamber 101 , and a plurality of first electrodes 211 and a plurality of second electrodes 321 are disposed face to face.

That is to say, the filter chip 30 and the functional chip 20 are arranged correspondingly in the upper and lower directions, the first electrode 211 and the second electrode 321 are also arranged face to face, and the size of the filter chip 30 can be smaller than the size of the functional chip 20. In this way, in the horizontal direction, the setting of the filter chip 30 will not further occupy the horizontal space of the packaging substrate 10, and the size of the packaging substrate 10 can be further reduced.

In this embodiment, one side of the package substrate 10 has a plurality of external pins 121 , and the interconnection structure 50 is used to conduct the first electrode 211 , the second electrode 321 and the external pins 121 .

The external pins 121 may be a ball grid array (BGA), a pad, etc. The multi-chip packaging structure 100 may be electrically connected to other chips or substrates through the external pins 121. Here, the external pins 121 take the ball grid array 121 as an example, and the external pins 121 protrude from the bottom surface of the multi-chip packaging structure 100.

In addition, here, it is taken as an example that a plurality of external pins 121 are located on one side of the lower surface 12 of the substrate, but the present invention is not limited thereto, and the external pins 121 may also be located in other areas.

The package substrate 10 has a plurality of through holes 13 , and the interconnection structure 50 conducts the first electrode 211 , the second electrode 321 and the external pin 121 through the through holes 13 .

In this embodiment, the through holes 13 and the second electrodes 321 are spaced apart from each other.

Here, the through hole 13 is located on the outside of the second electrode 321, and the through hole 13 is located on the outside of the chamber 101. At this time, the external pins 121 located on one side of the lower surface 12 of the substrate can be moved outward on both sides of the filter chip 30, which is convenient for arranging the space for burying other chips in advance, thereby facilitating the realization of high-performance and small-size multi-chip 2.5D or 3D stacked integrated packaging and modules.

In this embodiment, the interconnection structure 50 includes a metal pillar 51 , a solder 52 and an electroplating layer structure 53 .

The metal column 51 is connected to the bottom of the second electrode 321 , the electroplating layer structure 53 is connected to the first electrode 211 , and the electroplating layer structure 53 extends to the bottom of the package substrate 10 through the through hole 13 to connect to the external pin 121 , and the solder 52 is used to connect the metal column 51 and the electroplating layer structure 53 .

Specifically, the electroplating layer structure 53 includes an upper redistribution layer 531 , an intermediate wiring layer 532 , and a lower redistribution layer 533 that are interconnected.

The upper redistribution layer 531 is located above the package substrate 10 and is connected to the first electrode 211 . A first insulating layer 70 is disposed between the upper redistribution layer 531 and the substrate upper surface 11 and the first upper surface 21 .

That is, the upper redistribution layer 531 is connected to the first electrode 211 through the hole in the first insulating layer 70 .

The middle wiring layer 532 includes a first electroplating layer 5321 located on the upper surface 11 of the substrate, a second electroplating layer 5322 located on the inner wall of the through hole 13 , and a third electroplating layer 5323 located on the lower surface 12 of the substrate.

The first electroplating layer 5321 is connected to the upper redistribution layer 531 , that is, the first insulating layer 70 covers the first electroplating layer 5321 , and the upper redistribution layer 531 is connected to the first electroplating layer 5321 through the holes on the first insulating layer 70 .

The width of the first electroplating layer 5321 connected to the upper redistribution layer 531 extending to the upper surface 11 of the substrate is substantially equal to the width of the corresponding third electroplating layer 5323 extending to the lower surface 12 of the substrate.

Here, on the one hand, both the upper surface 11 and the lower surface 12 of the substrate are provided with electroplating layers, which can improve the reliability of the combination of the electroplating layer and the packaging substrate 10; on the other hand, the first electroplating layer 5321 extends toward the first electrode 211, which is convenient for the upper rewiring layer 531 to connect to the first electroplating layer 5321, and because the solder 52 does not enter the through hole 13 at this time, the through hole 13 can move outward on both sides, thereby allowing the external pin 121 of the lower surface 12 of the substrate to move outward.

The lower redistribution layer 533 is located below the package substrate 10 and is connected to the external pins 121 , and the lower redistribution layer 533 is connected to the third electroplating layer 5323 .

Here, the multi-chip packaging structure 100 includes a first lower redistribution layer 5331 connected to the third electroplating layer 5323, a second insulating layer 71 located between the first lower redistribution layer 5331 and the lower surface 12 of the substrate, a third insulating layer 72 covering the second insulating layer 71 and the first lower redistribution layer 5331, a second lower redistribution layer 5332 that conducts the first lower redistribution layer 5331 through holes on the third insulating layer 72 and extends toward the lower surface of the third insulating layer 72, and a fourth insulating layer 73 covering the third insulating layer 72 and the second lower redistribution layer 5332, the external pin 121 is connected to the second lower redistribution layer 5332, and the fourth insulating layer 73 exposes the external pin 121.

The lower redistribution layer 533 includes a first lower redistribution layer 5331 and a second lower redistribution layer 5332 , which can not only expand the redistribution range and improve the freedom of subsequent external pin 121 layout, but also further assist the external pin 121 to move outward.

The metal pillar 51 is a copper pillar, and the upper redistribution layer 531 , the middle redistribution layer 532 and the lower redistribution layer 533 are all copper layers.

This embodiment adopts a simple redistribution layout (RDL) solution to achieve electrical connection between the first electrode 211, the second electrode 321 and the external pin 121, and the process is stable and the reliability is high.

The metal wire material for the rewiring is copper (i.e., the upper rewiring layer 531, the middle wiring layer 532 and the lower rewiring layer 533 are all copper layers). A metal or alloy film that enhances the mutual adhesion between the rewiring copper and the chip electrodes (including the first electrode 211 and the second electrode 321) can be arranged between the rewiring copper and the chip electrodes. The metal or alloy material can be nickel, titanium, nickel-chromium, titanium tungsten, etc.

A first insulating layer 70 , a second insulating layer 71 and a third insulating layer 72 are sandwiched between the package substrate 10 , the upper redistribution layer 531 and the lower redistribution layer 533 , so as to achieve electrical isolation between the various components.

It can be understood that the upper rewiring layer 531 in the rewiring scheme is not limited to the above-mentioned one layer, and the lower rewiring layer 533 is not limited to the above-mentioned two layers (i.e., the first lower rewiring layer 5331 and the first lower rewiring layer 5332), which can be determined according to actual conditions.

In addition, the advantages of setting the copper pillar 51 and the solder 52 in this embodiment are: (1) the solder 52 is in a molten state during the reflow soldering process, which is convenient for combining with the copper pillar 51, and the combining effect is better; (2) the contact area between the solder 52 and the upper rewiring layer 531 is large, which can improve the electrical transmission performance and also improve the reliability of the combination of the solder 52 and the upper rewiring layer 531; (3) the copper pillar 51 has already occupied a part of the space. At this time, when the solder 52 is set, the amount of raw materials used in the solder 52 can be reduced, the difficulty of the solder 52 welding process is reduced, the welding time is shortened, and the welding capacity is improved; (4) the copper pillar 51 has a significant appearance and can be used as an identification part to improve the recognition efficiency, thereby facilitating automated appearance inspection and possible defect identification.

In this embodiment, the multi-chip packaging structure 100 further includes a dam 40 , which cooperates with the second lower surface 32 and the upper surface of the first insulating layer 70 to enclose a cavity S corresponding to the active area on the surface of the filter chip 30 .

In this embodiment, the cofferdam 40 is provided to form the cavity S, which can effectively prevent foreign matter from entering the cavity S during the manufacturing process of the packaging structure or during the use of the packaging structure and affecting the normal use of the filter chip 30, thereby improving the overall performance of the multi-chip packaging structure 100.

It should be noted that the cofferdam 40 extends toward the cavity S and completely covers the upper redistribution layer 531 , and at this time the cofferdam 40 is also combined with the upper surface of the upper surface of the first insulating layer 70 , but this is not limited thereto.

The cofferdam 40 includes a first cofferdam 41 located inside the second electrodes 321 and a second cofferdam 42 located outside the second electrodes 321 . The first cofferdam 41 cooperates with the second lower surface 32 and the upper surface of the first insulating layer 70 to enclose a cavity S.

Here, the first cofferdam 41 is located inside the through hole 13 , and the second cofferdam 42 is partially located inside the through hole 13 and partially located outside the through hole 13 .

Since the cofferdam 40 has a certain height, when the lower surface area of the cofferdam 40 is too small, it may be unable to support the cofferdam 40 of this height, thereby causing the cofferdam 40 to collapse. The cofferdam 40 of this embodiment includes a first cofferdam 41 and a second cofferdam 42. The cofferdam 40 has a sufficiently large lower surface, which improves the stability of the entire cofferdam 40; in addition, the upper surface of the cofferdam 40 can be combined with the entire area of the lower surface of the filter chip 30 outside the cavity S area of the lower surface of the filter chip 30, further improving the molding stability of the cavity S.

4 , a plurality of through holes 13 are distributed in an array on the upper surface 11 of the substrate, and there is a gap between adjacent through holes 13, there is a space between two rows of through holes 13, the chamber 101 is located in the space, and there is a gap between the chamber 101 and the through hole 13, the first cofferdam 41 corresponds to the internal area of the chamber 101, and the first cofferdam 41 is actually located on the inner side of the second electrode 321, the second cofferdam 42 extends from the internal area corresponding to the chamber 101 toward the through hole 13, and a groove 43 for accommodating solder 52 is formed between the first cofferdam 41 and the second cofferdam 42, and the groove 43 is arranged corresponding to the second electrode 321.

In addition, the second cofferdam 42 extends in a direction away from the first cofferdam 41 until the outer edge of the second cofferdam 42 is flush with the outer edge of the package substrate 10 , and the second cofferdam 42 exposes the through hole 13 .

Of course, since the packaging substrate 10 is a quadrilateral structure, the outer edge also includes the front side edge and the rear side edge of the packaging substrate 10, and the second cofferdam 42 will also extend to the front side edge and the rear side edge, but it is not limited to this, and the packaging substrate 10 can also be a structure of other shapes.

It should be noted that the first cofferdam 41 and the second cofferdam 42 can be independent of each other. For example, the first cofferdam 41 is a first annular structure located on the inner side of the second electrodes 321 , and the second cofferdam 42 is a second annular structure located on the outer side of the second electrodes 321 .

Of course, the first cofferdam 41 and the second cofferdam 42 may also be interconnected. In this case, the first cofferdam 41 and the second cofferdam 42 are interconnected through the third cofferdam 43. The third cofferdam 43 is located between adjacent through holes 13 and adjacent second electrodes 321 or in other areas. That is to say, the cofferdam 40 at this time covers all areas above the upper rewiring layer 531 and the first insulating layer 70 except for the cavity S, the through hole 13 and the groove 43.

In this embodiment, the second lower surface 32 of the filter chip 30 covers the upper surface of the first cofferdam 41 , and the second lower surface 32 partially overlaps with the upper surface of the second cofferdam 42 , and the substrate upper surface 11 covers the lower surface of the first cofferdam 41 and the lower surface of the second cofferdam 42 .

The cofferdam 40 is made of a light-sensitive insulating material, but is not limited thereto.

In this embodiment, the multi-chip packaging structure 100 further includes a first plastic packaging layer 60 that covers both the exposed upper surface area of the second cofferdam 42 and the filter chip 30 , and the first plastic packaging layer 60 fills the through hole 13 .

The first plastic encapsulation layer 60 is located on a side of the packaging substrate 10 away from the substrate lower surface 12 .

That is to say, at this time, the first plastic packaging layer 60 is located above the second cofferdam 42 and inside the through hole 13 , and the first plastic packaging layer 60 covers all open areas around the filter chip 30 and the inner area of the through hole 13 .

The first plastic encapsulation layer 60 can be an EMC (Epoxy Molding Compound) plastic encapsulation layer. Since the present embodiment utilizes the cofferdam 40 to prevent foreign substances from entering the cavity S, there is no need to consider whether the first plastic encapsulation layer 60 will affect the protection area in the cavity S due to material problems. Therefore, the selection range of the first plastic encapsulation layer 60 material is greatly expanded, thereby avoiding the selection of specific plastic encapsulation materials, greatly widening the plastic encapsulation process window, and effectively reducing costs.

In this embodiment, the first upper surface 21 of the functional chip 20 is flush with the substrate upper surface 11 , and the second plastic packaging layer 61 is disposed in the gap between the functional chip 20 and the chamber 101 , the substrate lower surface 12 and the first lower surface 22 .

That is to say, the third electroplating layer 5323 is substantially located below the second plastic layer 61, and the second insulating layer 71 is also substantially located below the second plastic layer 61. Other descriptions of the second plastic layer 61 can refer to the description of the first plastic layer 60 and will not be repeated here.

Here, by setting the second plastic encapsulation layer 61, on the one hand, the thickness difference between the functional chip 20 and the packaging substrate 10 can be compensated, so that the first upper surface 21 is flush with the substrate upper surface 11, so as to facilitate the subsequent molding of the first insulating layer 70, the second insulating layer 71 and other structures; on the other hand, the second plastic encapsulation layer 61 can protect the functional chip 20 and fix the relative position of the functional chip 20 and the chamber 101.

An embodiment of the present invention further provides a method for manufacturing a multi-chip package structure 100. In combination with the description of the multi-chip package structure 100 and FIGS. 5 and 6a to 6z-19, the method comprises the following steps:

S1: Referring to FIG. 6a , a packaging substrate 10 is provided, which has a substrate upper surface 11 and a substrate lower surface 12 disposed opposite to each other;

S2: Referring to FIG. 6 b , a cavity 101 is formed on the packaging substrate 10 ;

S3: Referring to FIG. 6 c , a functional chip 20 is provided. The functional chip 20 has a first upper surface 21 and a first lower surface 22 that are oppositely disposed. The first upper surface 21 has a plurality of first electrodes 211 ;

S4: Referring to FIG. 6 d to FIG. 6 j , the functional chip 20 is loaded into the chamber 101 , and the first upper surface 21 and the upper surface 11 of the substrate are located on the same side;

Step S4 is specifically as follows:

Referring to Fig. 6d, a temporary bonding plate 90 is provided;

Referring to FIG. 6 e , the upper surface 11 of the packaging substrate 10 is bonded to the temporary bonding plate 90 ;

Referring to FIG. 6 f , the functional chip 20 is loaded into the chamber 101 , and the first upper surface 21 and the upper surface 11 of the substrate are located on the same side;

Here, the first upper surface 21 is also attached to the temporary attaching plate 90 , so that the first upper surface 21 can be flush with the substrate upper surface 11 .

Referring to FIG. 6g , a second plastic encapsulation layer 61 is formed to cover the gap between the functional chip 20 and the chamber 101 , the lower surface 12 of the substrate and the first lower surface 22 ;

Referring to FIG. 6h , the temporary bonding plate 90 is removed;

Referring to FIG. 6i , a plurality of through holes 13 are formed on the packaging substrate 10 , and the through holes 13 penetrate the second plastic packaging layer 61 ;

Referring to FIG. 6 j , the packaging substrate 10 is turned over.

S5: Referring to FIG. 6 k to FIG. 6 v , a first interconnection structure is formed on the package substrate 10 , and the first interconnection structure is connected to the first electrode 211 ;

Step S5 is specifically as follows:

6k to 6n , a first electroplating layer 5321 is formed on the upper surface 11 of the substrate, a second electroplating layer 5322 is formed on the inner wall of the through hole 13 , and a third electroplating layer 5323 is formed on the second plastic sealing layer 61 ;

details as follows:

Referring to FIG. 6 k , a first photoresist layer 81 and a second photoresist layer 82 are formed above the upper surface 11 of the substrate and below the second plastic encapsulation layer 61 , respectively;

61 , the first photoresist layer 81 is exposed and developed to form a first opening 811, the first opening 811 exposes the through hole 13 and the upper surface 11 of the substrate, and the second photoresist layer 82 is exposed and developed to form a second opening 821, the second opening 821 exposes the through hole 13 and the second plastic encapsulation layer 61;

Referring to FIG. 6m , a first electroplating layer 5321 is formed on the exposed upper surface 11 of the substrate, a second electroplating layer 5322 is formed on the exposed inner wall of the through hole 13, and a third electroplating layer 5323 is formed on the exposed second plastic sealing layer 61;

6 n , the first photoresist layer 81 and the second photoresist layer 82 are removed.

Referring to FIG. 6 o , a first insulating layer 70 is formed on the substrate upper surface 11 , the first upper surface 21 , and the first electroplating layer 5321 ;

6p to 6t, an upper redistribution layer 531 is formed on the first insulating layer 70 to conduct the first electrode 211 and the first electroplating layer 5321 through the holes on the first insulating layer 70;

details as follows:

Referring to FIG. 6 p , the first insulating layer 70 is exposed and developed to form a first hole 701 , and the first hole 701 exposes the first electrode 211 , the through hole 13 and the first electroplating layer 5321 ;

Referring to FIG. 6q , a third photoresist layer 83 is formed on the first insulating layer 70 ;

6 r , the third photoresist layer 83 is exposed and developed to form a third opening 831 , and the third opening 831 exposes the first electrode 211 , the first electroplating layer 5321 and the first insulating layer 70 ;

Referring to FIG. 6s , an upper redistribution layer 531 is formed in the third opening 831 ;

Referring to FIG. 6 t , the third photoresist layer 83 is removed.

Referring to FIG. 6 u , a photosensitive insulating film 80 is disposed above the first insulating layer 70 and the upper redistribution layer 531 ;

Referring to FIG. 6v, exposure and development form a cofferdam 40, the cofferdam 40 includes a first cofferdam 41 and a second cofferdam 42, the outer edge of the second cofferdam 42 is flush with the outer edge of the package substrate 10, the second cofferdam 42 exposes the through hole 13, and there is a groove 43 between the first cofferdam 41 and the second cofferdam 42;

It should be noted that the cofferdam 40 may include a third cofferdam 43 connecting the first cofferdam 41 and the second cofferdam 42. That is to say, at this time, the cofferdam 40 is formed on the surface area of the substrate 11 except the corresponding cavity S, through hole 13 and groove 43 area.

In addition, since the independent packaging substrate 10 can be formed by dividing a large wafer-level substrate, when forming the cofferdam 40, multiple cofferdams 40 can be directly formed on the large substrate, and then the large substrate is divided to obtain a single packaging substrate 10 with a single cofferdam 40. In this way, the packaging efficiency can be greatly improved. Of course, the cofferdam 40 can also be formed on the filter chip 30.

S6: Referring to FIG. 6 w , a filter chip 30 is provided. The filter chip 30 has a second upper surface 31 and a second lower surface 32 that are oppositely disposed, and the second lower surface 32 has a plurality of second electrodes 321 ;

S7: Referring to FIGS. 6x to 6z-16 , the filter chip 30 is mounted on the packaging substrate 10 , the second lower surface 32 is disposed face to face with the substrate upper surface 11 , and a second interconnection structure connecting the second electrode 321 and the first interconnection structure is formed;

S8: Referring to FIG. 6z - 17 to FIG. 6z - 19 , external pins 121 are formed on the second interconnect structure.

Steps S7 and S8 are specifically as follows:

6x to 6z-1, a metal column 51 is formed on the lower surface of the second electrode 321;

details as follows:

Referring to FIG. 6x , a fourth photoresist layer 84 is formed on the second lower surface 32 ;

Referring to FIG. 6 y , the fourth photoresist layer 84 is exposed and developed to form a fourth opening 841 , and the fourth opening 841 exposes the second electrode 321 ;

Referring to FIG. 6 z , a metal pillar 51 is formed in the fourth opening 841 ;

Referring to FIG. 6z-1 , the fourth photoresist layer 84 is removed.

Referring to FIG. 6z-2 , solder 52 is disposed in the slot 43 ;

Referring to Figure 6z-3, the filter chip 30 is loaded on top of the packaging substrate 10, the second lower surface 32 is arranged face to face with the upper surface 11 of the substrate, the first cofferdam 41 and the second lower surface 32 and the upper surface of the first insulating layer 70 cooperate with each other to form a cavity S, and the metal column 51 is aligned with the groove 43, and the solder 52 and the metal column 51 are connected to each other.

Referring to FIG. 6z-4 , a first plastic encapsulation layer 60 is formed on a side of the package substrate 10 away from the lower surface 12 of the substrate. The first plastic encapsulation layer 60 simultaneously covers the upper surface area of the second cofferdam 42 exposed to the outside and the filter chip 30 , and the first plastic encapsulation layer 60 fills the through hole 13 ;

Referring to FIG. 6z-5 , a second insulating layer 71 is formed below the third electroplating layer 5323 and the second plastic encapsulation layer 61 ;

6z-6 to 6z-10, a first lower redistribution layer 5331 is formed below the second insulating layer 71 to conduct the third electroplating layer 5323 through the holes on the second insulating layer 71;

details as follows:

Referring to FIG. 6z-6 , the second insulating layer 71 is exposed and developed to form a second hole 711 , and the second hole 711 exposes the third electroplating layer 5323 ;

6z-7, a fifth photoresist layer 85 is formed below the second insulating layer 71;

6z-8, the fifth photoresist layer 85 is exposed and developed to form a fifth opening 851, and the fifth opening 851 exposes the second hole 711 and the second insulating layer 71;

Referring to FIG. 6z-9 , a first lower redistribution layer 5331 is formed in the fifth opening 851 ;

Referring to FIG. 6z-10 , the fifth photoresist layer 85 is removed.

6z-11 , a third insulating layer 72 is formed below the first lower redistribution layer 5331 and the second insulating layer 71 ;

6z-12 to 6z-16 , a second lower redistribution layer 5332 is formed below the third insulating layer 72 to conduct the first lower redistribution layer 5331 through the holes on the third insulating layer 72 ;

details as follows:

6z-12, the third insulating layer 72 is exposed and developed to form a third hole 721, and the third hole 721 exposes the first lower redistribution layer 5331;

6z-13, a sixth photoresist layer 86 is formed below the third insulating layer 72;

6z-14 , a sixth opening 861 is formed by exposing and developing the sixth photoresist layer 86 , and the sixth opening 861 exposes the third hole 721 and the third insulating layer 72 ;

Referring to FIG. 6z-15 , a second lower redistribution layer 5332 is formed in the sixth opening 861 ;

Referring to FIG. 6z-16 , the sixth photoresist layer 86 is removed.

Referring to FIGS. 6z-17 and 6z-18 , a fourth insulating layer 73 covering the third insulating layer 72 and the second lower redistribution layer 5332 is formed, and the fourth insulating layer 73 exposes the second lower redistribution layer 5332 ;

details as follows:

6z-17 , a fourth insulating layer 73 is formed below the second lower redistribution layer 5332 and the third insulating layer 72 ;

6z-18 , a fourth hole 731 is formed in the fourth insulating layer 73 by exposure and development, and the fourth hole 731 exposes the second lower redistribution layer 5332 .

6z-19 , a ball grid array 121 is formed on the exposed second lower redistribution layer 5332 , that is, a ball grid array 121 is formed in the fourth hole 731 .

For other descriptions of the method for manufacturing the multi-chip package structure 100 of this embodiment, reference may be made to the description of the multi-chip package structure 100 described above, which will not be repeated here.

The cofferdam 40 of the present invention is located on the inner side and the outer side of the second electrode 321, and the outer edge of the second cofferdam 42 is flush with the outer edge of the packaging substrate 10. In other embodiments, the cofferdam 40 may also be located on the inner side of the second electrode 321, or the outer edge of the second cofferdam 42 is flush with the outer edge of the filter chip 30, or the outer edge of the second cofferdam 42 is located between the outer edge of the filter chip 30 and the outer edge of the packaging substrate 10, and so on.

In summary, this embodiment forms a cavity S by setting a cofferdam 40, which can effectively prevent foreign matter from entering the cavity S during the packaging structure manufacturing process or during the use of the packaging structure and affecting the normal use of the filter chip 30, thereby improving the overall performance of the multi-chip packaging structure 100.

In addition, this embodiment utilizes packaging technology to package two different chips (filter chip 30 and functional chip 20) into the same packaging substrate 10, which can achieve high integration of multiple chips, improve the utilization rate of the packaging substrate 10, and further realize the miniaturization of the multi-chip packaging structure 100.

It should be understood that although this specification is described according to implementation modes, not every implementation mode contains only one independent technical solution. This description of the specification is only for the sake of clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each implementation mode may also be appropriately combined to form other implementation modes that can be understood by those skilled in the art.

The series of detailed descriptions listed above are only specific descriptions of feasible implementation methods of the present invention. They are not intended to limit the scope of protection of the present invention. Any equivalent implementation methods or changes that do not deviate from the technical spirit of the present invention should be included in the scope of protection of the present invention.

Claims (7)

1. A stacked multichip package structure with cavities, comprising:

the packaging substrate is provided with a substrate upper surface and a substrate lower surface which are oppositely arranged, and the packaging substrate is provided with a cavity;

The functional chip is arranged in the cavity and is provided with a first upper surface and a first lower surface which are oppositely arranged, the first upper surface and the upper surface of the substrate are positioned on the same side, and the first upper surface is provided with a plurality of first electrodes;

The filter chip is arranged above the packaging substrate and is provided with a second upper surface and a second lower surface which are oppositely arranged, the second lower surface and the upper surface of the substrate are arranged face to face, and the second lower surface is provided with a plurality of second electrodes;

a plurality of interconnection structures for conducting a plurality of first electrodes and a plurality of second electrodes;

One side of the lower surface of the substrate is provided with a plurality of external pins, the packaging substrate is provided with a plurality of through holes, and the interconnection structure conducts the first electrode, the second electrode and the external pins through the through holes; the through holes and the second electrode are distributed at intervals; the interconnection structure comprises a metal column, soldering tin and a plating layer structure, wherein the metal column is connected below the second electrode, the plating layer structure conducts the first electrode, the plating layer structure extends to the lower side of the packaging substrate through the through hole to conduct the external pin, and the soldering tin is used for conducting the metal column and the plating layer structure; the electroplating layer structure comprises an upper rewiring layer, a middle wiring layer and a lower rewiring layer which are communicated with each other, the upper rewiring layer is positioned above the packaging substrate and is used for conducting the first electrode, the lower rewiring layer is positioned below the packaging substrate and is used for conducting the external pin, the middle wiring layer comprises a first electroplating layer, a second electroplating layer and a third electroplating layer, the first electroplating layer is positioned on the upper surface of the substrate, the second electroplating layer is positioned on the inner wall of the through hole, the third electroplating layer is positioned on the lower surface of the substrate, the first electroplating layer is connected with the upper rewiring layer, and the third electroplating layer is connected with the lower rewiring layer; the multi-chip packaging structure comprises a first lower rewiring layer connected with the third electroplated layer, a second insulating layer positioned between the first lower rewiring layer and the lower surface of the substrate, a third insulating layer coating the second insulating layer and the first lower rewiring layer, a second lower rewiring layer which is conducted through holes of the third insulating layer and extends towards the lower surface direction of the third insulating layer, and a fourth insulating layer coating the third insulating layer and the second lower rewiring layer, wherein the external pins are connected with the second lower rewiring layer, and the fourth insulating layer exposes the external pins.

2. The multi-chip package structure of claim 1, wherein the filter chip is located above the cavity, and the plurality of first electrodes are disposed face-to-face with the plurality of second electrodes.

3. The multi-chip package structure of claim 1, wherein a first insulating layer is disposed between the upper redistribution layer and the upper surface of the substrate and between the upper redistribution layer and the first upper surface, and the multi-chip package structure further comprises a dam, wherein the dam cooperates with the second lower surface and the upper surface of the first insulating layer to form a cavity.

4. The multi-chip package structure of claim 3, wherein the dam comprises a first dam located inside the plurality of second electrodes and a second dam located outside the plurality of second electrodes, the first dam and the second lower surface and the upper surface of the first insulating layer are mutually matched to enclose a cavity, the second dam extends in a direction away from the first dam until an outer edge of the second dam is flush with an outer edge of the package substrate, and the second dam exposes the through hole.

5. The multi-chip package structure of claim 4, further comprising a first molding layer on a side of the package substrate remote from the substrate lower surface, the first molding layer simultaneously encapsulating the filter chip and an exposed upper surface area of the second dam, and the first molding layer filling the through hole.

6. The multi-chip package structure of claim 1, wherein a gap between the functional chip and the cavity, the lower surface of the substrate, and the first lower surface are provided with a second molding layer, and the first upper surface is flush with the upper surface of the substrate.

7. The manufacturing method of the vertically stacked multi-chip packaging structure with the cavity is characterized by comprising the following steps:

S1: providing a packaging substrate, wherein the packaging substrate is provided with a substrate upper surface and a substrate lower surface which are oppositely arranged;

s2: forming a cavity on the packaging substrate;

S3: providing a functional chip, wherein the functional chip is provided with a first upper surface and a first lower surface which are oppositely arranged, and the first upper surface is provided with a plurality of first electrodes;

s4: loading the functional chip into the chamber, wherein the first upper surface and the upper surface of the substrate are positioned on the same side;

s5: forming a first interconnection structure on the packaging substrate, wherein the first interconnection structure conducts the first electrode;

S6: providing a filter chip, wherein the filter chip is provided with a second upper surface and a second lower surface which are oppositely arranged, and the second lower surface is provided with a plurality of second electrodes;

s7: the filter chip is loaded above the packaging substrate, the second lower surface and the upper surface of the substrate are arranged face to face, and a second interconnection structure for conducting the second electrode and the first interconnection structure is formed;

S8: forming an external pin on the second interconnection structure; the step S4 specifically comprises the following steps:

Providing a temporary bonding plate;

bonding the upper surface of the substrate of the packaging substrate to the temporary bonding plate;

loading the functional chip into the chamber, wherein the first upper surface and the upper surface of the substrate are positioned on the same side;

forming a second plastic layer which covers the gap between the functional chip and the cavity, the lower surface of the substrate and the first lower surface;

Removing the temporary bonding plate;

forming a plurality of through holes on the packaging substrate, wherein the through holes penetrate through the second plastic sealing layer;

Inverting the package substrate;

The step S5 specifically comprises the following steps:

Forming a first electroplated layer on the upper surface of the substrate, forming a second electroplated layer on the inner wall of the through hole, and forming a third electroplated layer on the second plastic sealing layer;

forming an insulating layer on the upper surface of the substrate, the first upper surface and the first electroplated layer;

Forming an upper rewiring layer above the first insulating layer, wherein the upper rewiring layer is used for conducting the first electrode and the first electroplated layer through holes in the first insulating layer;

A Fang Bushe light-sensitive insulating film on the first insulating layer and the upper rewiring layer;

exposing and developing to form a cofferdam, wherein the cofferdam comprises a first cofferdam and a second cofferdam, the outer side edge of the second cofferdam is flush with the outer side edge of the packaging substrate, the second cofferdam exposes the through hole, and a slot is formed between the first cofferdam and the second cofferdam;

the steps S7 and S8 specifically include:

Forming a metal column on the lower surface of the second electrode;

Arranging soldering tin in the slot;

The filter chip is loaded above the packaging substrate, the second lower surface and the upper surface of the substrate are arranged face to face, the first cofferdam, the second lower surface and the upper surface of the first insulating layer are mutually matched to enclose to form a cavity, the metal column is aligned to the slot, and the soldering tin and the metal column are mutually communicated;

forming a first plastic sealing layer on one side of the packaging substrate, which is far away from the lower surface of the substrate, wherein the first plastic sealing layer simultaneously covers the upper surface area of the second cofferdam, which is exposed outside, and the filter chip, and the first plastic sealing layer fills the through hole;

forming a second insulating layer below the third electroplated layer and the second plastic sealing layer;

forming a first lower rewiring layer below the second insulating layer, wherein the first lower rewiring layer is communicated with the third electroplated layer through a hole in the second insulating layer;

forming a third insulating layer under the first lower rewiring layer and the second insulating layer;

Forming a second lower rewiring layer below the third insulating layer, wherein the second lower rewiring layer is communicated with the first lower rewiring layer through a hole in the third insulating layer;

Forming a fourth insulating layer covering the third insulating layer and the second lower rewiring layer, wherein the second lower rewiring layer is exposed by the fourth insulating layer;

The exposed second lower redistribution layer forms a ball grid array.