CN108809280A - comparator - Google Patents
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- CN108809280A CN108809280A CN201710310183.0A CN201710310183A CN108809280A CN 108809280 A CN108809280 A CN 108809280A CN 201710310183 A CN201710310183 A CN 201710310183A CN 108809280 A CN108809280 A CN 108809280A
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- 239000003990 capacitor Substances 0.000 claims description 18
- 230000008030 elimination Effects 0.000 abstract description 8
- 238000003379 elimination reaction Methods 0.000 abstract description 8
- 238000010586 diagram Methods 0.000 description 7
- 238000000034 method Methods 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 3
- 230000005669 field effect Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/22—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral
- H03K5/24—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude
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- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Manipulation Of Pulses (AREA)
- Amplifiers (AREA)
Abstract
A kind of imbalance elimination realization circuit of comparator, is included in concatenated feedback switch (S3) between the output end of the comparator and an input terminal of the comparator；And voltage hold circuit (101), when the comparator enters comparison phase, the voltage hold circuit (101) keeps the voltage at feedback switch (S3) both ends equal.
Description
Technical Field
The present invention relates to circuit technologies, and in particular, to a comparator.
Background
With the widespread use of circuit technology, circuit technology utilizes advanced design and manufacturing capabilities. Comparator circuits are widely used in analog integrated circuits as a common circuit module. A new generation of comparators with high accuracy and low power consumption has emerged. New generation comparators can greatly improve the energy efficiency and operating speed of various devices, including gas sensors, medical devices, safety systems, and industrial controls.
A comparator circuit is a common circuit in circuit design, and an offset cancel (offset cancel) technique is also a technique used in the comparator circuit. In general, comparator offset cancellation techniques all require clock and sample-and-hold circuits to hold the offset voltage (offset). The holding circuit is usually implemented by a capacitor, for example. The higher the frequency of the clock the greater the system power consumption. However, if the clock frequency is reduced, the leakage of the capacitor through the switch in the hold circuit will cause a comparison error.
The invention provides a comparator circuit offset elimination implementation circuit which can avoid electric leakage and prevent errors caused by electric leakage.
Disclosure of Invention
The technical problem to be solved by the present invention is to overcome the problems in the prior art, and to provide an offset cancellation implementation circuit of a comparator, which can reduce the leakage current of the offset cancellation implementation circuit, thereby reducing the clock frequency of the offset cancellation implementation circuit and reducing the power consumption.
In order to solve the above problems, the technical solution of the present invention is as follows:
an offset cancellation implementation circuit of a comparator, comprising:
a feedback switch (S3) connected in series between an output of the comparator and an input of the comparator; and
a voltage holding circuit (101), said voltage holding circuit (101) holding the voltage across said feedback switch (S3) equal when said comparator enters a comparison phase.
Further, a feedback loop is formed between the output end of the comparator and one input end of the comparator, and the feedback loop is conducted in the offset elimination stage.
Further, the voltage holding circuit (101) comprises a leakage switch (S4) and a capacitor (C1), the leakage switch (S4) is connected in series between the output terminal of the comparator and the voltage holding circuit (101), one end of the capacitor (C1) is connected with the leakage switch (S4) and the feedback switch (S3), and the other end of the capacitor (C1) is grounded.
Further, the phases of the leakage switch (S4) and the feedback switch (S3) are the same; or/and the phase of the leakage switch (S4) has a phase difference with the phase of the feedback switch.
Further, the voltage holding circuit (201) includes a leakage switch (S4) and a voltage holding switch (S5), the leakage switch (S4) is connected in series between the output terminal of the comparator and the voltage holding circuit (101), one end of the voltage holding switch (S5) is connected to the leakage switch (S4) and the feedback switch (S3), the other end of the voltage holding switch (S5) is connected to a voltage equal to the reference voltage of the comparator, and the phase of the voltage holding switch (S5) is opposite to the phase of the feedback switch (S3).
Further, the phases of the leakage switch (S4) and the feedback switch (S3) are the same; or/and the phase of the leakage switch (S4) has a phase difference with the phase of the feedback switch.
Further, the offset cancellation implementation circuit further comprises a sample-and-hold circuit (102) for holding an offset voltage, wherein the sample-and-hold circuit (102) is connected to an input terminal of the comparator.
Further, the offset canceling circuit further includes a first switch (S1) and a second switch (S2), one end of the first switch (S1) is connected to the reference voltage of the comparator, the other end of the first switch (S1) is connected to the other input end of the comparator, one end of the second switch (S2) is connected to the input voltage of the comparator, and the other end of the second switch (S2) is connected to the other input end of the comparator.
Further, the first switch S1, the second switch S2 and the feedback switch (S3) are all MOS switches.
Further, the first switch (S1) and the feedback switch (S3) are in phase, and the phase of the second switch (S2) is opposite to the phase of the feedback switch (S3).
The invention provides a circuit for eliminating offset of a comparator, which comprises: a feedback switch (S3) connected in series between an output of the comparator and an input of the comparator; and the voltage holding circuit (101), when the said comparator enters the comparison stage, the said voltage holding circuit (101) keeps the voltage of both ends of the said feedback switch (S3) equal, has reduced the electric leakage of the feedback switch, thus can reduce the clock frequency of the offset elimination realization circuit, in order to achieve the goal of reducing the power consumption. And can reduce errors that may be caused.
Drawings
The invention is described in detail below with reference to the drawings and the detailed description;
fig. 1 is a circuit diagram showing an offset canceling circuit of a comparator according to an embodiment of the present invention.
Fig. 2 is a schematic diagram showing the operation principle of one phase of the offset canceling implementation circuit of the comparator according to one embodiment of the present invention.
Fig. 3 is a schematic diagram showing the operation principle of another phase of the offset canceling implementation circuit of the comparator according to one embodiment of the present invention.
Fig. 4 is a circuit diagram showing an offset canceling circuit of a comparator according to another embodiment of the present invention.
Detailed Description
In order to make the technical means, the creation characteristics, the achievement purposes and the effects of the invention easy to understand, the invention is further explained below by combining the specific drawings.
Comparator offset cancellation techniques require clock and sample and hold circuits to hold the offset voltage (offset). The sample-and-hold circuit is implemented, for example, with a capacitor. On the other hand, the higher the frequency of the clock, the greater the system power consumption. But if the frequency of the clock is reduced, then the leakage of the capacitance through the switch in the sample-and-hold circuit will cause a comparison error.
The invention discloses a circuit for eliminating offset of a comparator, which comprises: a feedback switch (S3) connected in series between an output of the comparator and an input of the comparator; and a voltage holding circuit (101), the voltage holding circuit (101) holding the voltages across the feedback switch (S3) equal when the comparator enters a comparison phase.
The offset cancellation implementation circuit of the comparator can reduce the electric leakage of the offset cancellation implementation circuit, thereby reducing the clock frequency of the offset cancellation implementation circuit and reducing the power consumption. The offset is reduced, the electric leakage of the circuit is eliminated, and the error caused by the electric leakage can be prevented.
Fig. 1 is a circuit diagram showing an offset canceling circuit of a comparator according to an embodiment of the present invention.
According to an embodiment of the present invention, the offset cancellation circuit of the comparator includes a sample-and-hold circuit connected to the comparator for holding the offset voltage Voffset. The sample-and-hold circuit uses, for example, a capacitor.
As shown in fig. 1, the comparator a0And said comparator a0An input terminal (in this embodiment the comparator)A0Is a negative terminal, in other embodiments the comparator a0May be + terminal), wherein the comparator a forms a feedback loop0And said comparator a0And a voltage holding circuit (101) and a feedback switch (S3) connected in series in sequence between one input end of the voltage holding circuit. During an offset cancel (offset cancel) phase, the feedback loop is turned on. At the comparator A0When entering the comparison phase, the voltage holding circuit (101) keeps the voltages at the two ends of the feedback switch (S3) equal (namely Vh and Vx are equal).
The offset cancellation implementation circuit further comprises a first switch (S1) and a second switch (S2), wherein one end of the first switch (S1) is connected with the comparator A0The other end of the first switch (S1) is connected to the other input terminal of the comparator a0, one end of the second switch (S2) is connected to the input voltage Vin of the comparator, and the other end of the second switch (S2) is connected to the other input terminal of the comparator a 0. In this embodiment the comparator A0The other input terminal of (b) is a + terminal, in other embodiments the comparator A0May be-terminal.
In this embodiment, the first switch S1, the second switch S2 and the feedback switch S3 are MOS switches, and in other embodiments, the first switch S1, the second switch S2 and the feedback switch S3 may be other switches such as field effect transistors. The first switch S1 and the feedback switch S3 are in phaseThe second switch S2 has opposite phase to the first switch S1 and the feedback switch S3Wherein,andis a two phase non-overlapping clock.
In order to hold the offset voltage, preferably, the offset cancellation implementation circuit further comprises a sample-and-hold circuit (102), and the sample-and-hold circuit (102) is connected with the comparator A0An input terminal of (1). For example, in this embodiment, the sample-and-hold circuit (102) is a capacitor, and one end of the capacitor is connected to the comparator A0The other end of the capacitor is grounded. The sample-and-hold circuit (102) is not limited to a capacitor, and it is within the scope of the idea of the present invention as long as the offset voltage can be held.
According to one embodiment of the invention, the Voltage holding circuit (Voltage holder) (101) comprises a leakage switch (S4) and a capacitor (C1), the leakage switch (S4) is connected in series between the output end of the comparator and the Voltage holding circuit (101), one end of the capacitor (C1) is connected with the leakage switch (S4) and the feedback switch (S3), and the other end of the capacitor (C1) is grounded. Wherein, the leakage switchWherein,andbelong to the same phase, andandhaving a phase difference of leakage current when entering the comparison stageFirst turned off and then fed back to the switchSwitch off. The leakage switch S4, the first switch S1, and the feedback switch S3 may be in phaseIn this embodiment, the leakage switch S4 is a MOS switch, and in other embodiments, the leakage switch S4 may also be another switch such as a field effect transistor.
In fig. 1, Voffset is the offset voltage of the comparator, the offset voltage Voffset appears in the circuit as a voltage source 103, but on the physical connection, the voltage source 103 does not really exist in the circuit, the first switch S1, the second switch S2 and the comparator a0Is directly connected to the other input terminal of the comparator A, but only at the first switch S1, the second switch S2 and the comparator A0A voltage difference exists at the other input terminal of the first transistor.
The working principle of the comparator offset cancellation realization circuit is described as follows:
fig. 2 is a schematic diagram illustrating the operation of one phase of the comparator offset cancellation implementation circuit according to one embodiment of the present invention. Fig. 3 is a schematic diagram showing the operation of another phase of the comparator offset cancellation implementation circuit according to an embodiment of the present invention.
Referring to FIG. 2, whenThe first switch S1, the feedback switch S3 and the leakage switch S4 are closed, the second switch S2 is opened, and the comparator A0And said comparator a0The feedback loop between one input terminals of the first and second switches is turned on. The circuit enters an offset cancellation offset cancel stage, Vh ═ Vref + Voffset, Voffset is the offset (offset) voltage of the comparator, Vh is the comparator a0Voltage of an input terminal of the voltage converter.
Referring to FIG. 3, whenFirst switch S1, feedback switchOff S3 and leakage switch S4 are open and the second switch S2 is closed. The circuit enters a normal comparison stage, when Vin-Vh is greater than 0, namely Vin + Voffset-Vref-Voffset is greater than 0, and Vin-Vref is greater than 0, Vout is equal to '1', and the offset voltage is eliminated.
If there is no leakage switchAnd a voltage holding circuit 101 connected to the leakage switch S4, the comparator A entering a comparison phase0The voltage Vh of one input end of the comparator A is a high-impedance point0And the output terminal voltage Vout and the comparator a0The voltage Vh at one input end of the comparator a has a large voltage difference, and although the feedback switch S3 is turned off, when the frequency of the offset cancellation circuit is low, the leakage of the feedback switch S3 will cause the comparator a to operate0The voltage Vh at one input of (a) is reduced, thereby introducing an error.
According to one embodiment of the invention, the leakage switchAnd the voltage holding circuit (Voltageholder)101 are the same in phase as the first switch S1, the feedback switch S3, but have a phase difference. At the time of the entry into the comparison phase,first is turned off, thenAnd (6) turning off. It can be obtained that the voltages Vx and Vh across the feedback switch S3 are equal. Since the voltages Vx and Vh across the feedback switch S3 are equal, the leakage of the feedback switch S3 will be small. Although the voltage drop of the leakage switch S4 is large, the leakage is large, but the feedback switch S3 is ensured to have small leakage.
The preferred embodiments of the present invention are described above, but the present invention is not limited to the above embodiments, for example:
the voltage holding circuit (101) is not limited to a capacitor, and as shown in fig. 4, the voltage holding circuit (201) includes a leakage switch (S4) and a voltage holding switch (S5), the leakage switch (S4) is connected in series between the output terminal of the comparator and the voltage holding circuit (101), one end of the voltage holding switch (S5) is connected to the leakage switch (S4) and the feedback switch (S3), the other end of the voltage holding switch (S5) is connected to a voltage equal to the reference voltage of the comparator, and the phase of the voltage holding switch (S5) is opposite to the phase of the feedback switch (S3). It is also within the scope of the present invention to ensure that the voltage holding circuit (101) keeps the voltages at the two ends of the feedback switch (S3) equal when the comparator enters the comparison stage, and to ensure that the leakage current of the feedback switch S3 is small. The leakage switch S4 and the voltage holding switch (S5) are MOS switches, and in other embodiments, the leakage switch S4 and the voltage holding switch (S5) may also be other switches such as field effect transistors.
Further, the voltage holding circuit is not limited to the above disclosed range as long as the voltage holding circuit electrically holds the voltages across the feedback switch (S3) equal when the comparator enters the comparison phase.
The offset cancellation implementing circuit of the invention comprises: a feedback switch (S3) connected in series between an output of the comparator and an input of the comparator; and the voltage holding circuit (101), when the said comparator enters the comparison stage, the said voltage holding circuit (101) keeps the voltage of both ends of the said feedback switch (S3) equal, has reduced the electric leakage of the feedback switch, thus can reduce the clock frequency of the offset elimination realization circuit, in order to achieve the goal of reducing the power consumption. And can reduce errors that may be caused.
The offset elimination implementation circuit of the comparator can reduce the electric leakage of the offset elimination implementation circuit, thereby reducing the clock frequency of the offset elimination implementation circuit and reducing the power consumption. The offset is reduced, the electric leakage of the circuit is eliminated, and the error caused by the electric leakage can be prevented.
The foregoing shows and describes the general principles, essential features, and advantages of the invention. It will be understood by those skilled in the art that the present invention is not limited by the foregoing examples, which are provided to illustrate the principles of the invention, and that various changes and modifications may be made without departing from the spirit and scope of the invention, which is also intended to be covered by the appended claims. The scope of the invention is defined by the appended claims and equivalents thereof.
Claims (10)
1. An offset cancellation implementation circuit of a comparator, comprising:
a feedback switch (S3) connected in series between an output of the comparator and an input of the comparator; and
a voltage holding circuit (101), said voltage holding circuit (101) holding the voltage across said feedback switch (S3) equal when said comparator enters a comparison phase.
2. The offset cancellation implementation circuit of claim 1, wherein a feedback loop is formed between the output of the comparator and an input of the comparator, the feedback loop being turned on during an offset cancellation phase.
3. Offset cancellation realization circuit of a comparator according to claim 1 or 2, characterized in that the voltage holding circuit (101) comprises a leakage switch (S4) and a capacitor (C1), the leakage switch (S4) is connected in series between the output of the comparator and the voltage holding circuit (101), one end of the capacitor (C1) is connected to the leakage switch (S4) and the feedback switch (S3), and the other end of the capacitor (C1) is connected to ground.
4. The offset cancellation realization circuit of comparator as claimed in claim 3, characterized in that the phases of the leakage switch (S4) and the feedback switch (S3) are the same; or/and the phase of the leakage switch (S4) has a phase difference with the phase of the feedback switch.
5. The offset cancellation realization circuit of comparator according to claim 1 or 2, characterized in that the voltage holding circuit (201) comprises a leakage switch (S4) and a voltage holding switch (S5), the leakage switch (S4) is connected in series between the output of the comparator and the voltage holding circuit (201), one end of the voltage holding switch (S5) is connected to the leakage switch (S4) and the feedback switch (S3), the other end of the voltage holding switch (S5) is connected to a voltage equal to the reference voltage of the comparator, and the phase of the voltage holding switch (S5) is opposite to the phase of the feedback switch (S3).
6. The offset cancellation realization circuit of comparator as claimed in claim 5, characterized in that the phase of the leakage switch (S4) and the feedback switch (S3) are the same; or/and the phase of the leakage switch (S4) has a phase difference with the phase of the feedback switch.
7. The offset cancellation circuit of claim 1, further comprising a sample-and-hold circuit (102) for holding an offset voltage, wherein the sample-and-hold circuit (102) is connected to an input of the comparator.
8. The offset cancellation circuit of claim 1, further comprising a first switch (S1) and a second switch (S2), wherein one end of the first switch (S1) is connected to the reference voltage of the comparator, the other end of the first switch (S1) is connected to the other input terminal of the comparator, one end of the second switch (S2) is connected to the input voltage of the comparator, and the other end of the second switch (S2) is connected to the other input terminal of the comparator.
9. The offset canceling realization circuit of comparator according to claim 8, characterized in that the first switch S1, the second switch S2 and the feedback switch (S3) are MOS switches.
10. The offset canceling implementation circuit of a comparator according to claim 8, characterized in that the first switch (S1) and the feedback switch (S3) are in phase, and the second switch (S2) is in phase with the feedback switch (S3).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710310183.0A CN108809280B (en) | 2017-05-04 | 2017-05-04 | Comparator with a comparator circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710310183.0A CN108809280B (en) | 2017-05-04 | 2017-05-04 | Comparator with a comparator circuit |
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| Publication Number | Publication Date |
|---|---|
| CN108809280A true CN108809280A (en) | 2018-11-13 |
| CN108809280B CN108809280B (en) | 2022-02-11 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710310183.0A Active CN108809280B (en) | 2017-05-04 | 2017-05-04 | Comparator with a comparator circuit |
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| CN (1) | CN108809280B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114268301A (en) * | 2022-02-28 | 2022-04-01 | 成都明夷电子科技有限公司 | LOS detection circuit with self-calibration offset function and detection method |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0432379A (en) * | 1990-05-29 | 1992-02-04 | Olympus Optical Co Ltd | Solid-state image pickup device |
| US20090273392A1 (en) * | 2008-05-01 | 2009-11-05 | Custom One Design, Inc. | Methods and apparatus for reducing non-ideal effects in correlated double sampling compensated circuits |
| CN103698054A (en) * | 2013-12-20 | 2014-04-02 | 深圳国微技术有限公司 | Temperature testing and calibration circuit and method |
-
2017
- 2017-05-04 CN CN201710310183.0A patent/CN108809280B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0432379A (en) * | 1990-05-29 | 1992-02-04 | Olympus Optical Co Ltd | Solid-state image pickup device |
| US20090273392A1 (en) * | 2008-05-01 | 2009-11-05 | Custom One Design, Inc. | Methods and apparatus for reducing non-ideal effects in correlated double sampling compensated circuits |
| CN103698054A (en) * | 2013-12-20 | 2014-04-02 | 深圳国微技术有限公司 | Temperature testing and calibration circuit and method |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114268301A (en) * | 2022-02-28 | 2022-04-01 | 成都明夷电子科技有限公司 | LOS detection circuit with self-calibration offset function and detection method |
| CN114268301B (en) * | 2022-02-28 | 2022-06-14 | 成都明夷电子科技有限公司 | LOS detection circuit with self-calibration offset function and detection method |
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| Publication number | Publication date |
|---|---|
| CN108809280B (en) | 2022-02-11 |
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Effective date of registration: 20220628 Address after: 201210 floor 10, block a, building 1, No. 1867, Zhongke Road, pilot Free Trade Zone, Pudong New Area, Shanghai Patentee after: Xiaohua Semiconductor Co.,Ltd. Address before: Room 303-304, block a, 112 liangxiu Road, pilot Free Trade Zone, Pudong New Area, Shanghai Patentee before: HUADA SEMICONDUCTOR Co.,Ltd. |
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