CN108780421A - For the technology in memory device mirroring command/address or interpretation command/address logic - Google Patents
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
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- G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
- G06F13/4234—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus
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- G11C5/063—Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
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- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
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- G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
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Abstract
Example includes the technology for mirroring command/address at memory device or interpretation command/address logic.Positioned at dual inline memory modules（DIMM）On memory device may include the circuit for having logic, the logic can receive command/address signal, and one or more short circuit pins based on memory device are come the command/address logic that is indicated in mirroring command/address or interpretation command/address signal.
Description
CROSS REFERENCE
The United States Patent (USP) No.15/266991 submitted for 15th this application claims September in 2016, it is entitled " in memory device
Mirroring command/address or the technology for interpreting command/address logic " is in 35 U.S.C § 365（c）Under priority, and then want
Seek the U.S. Provisional Application No.62/304212 submitted on March 5th, 2016, it is entitled " for memory device mirroring command/
The equity of the priority of address or the technology for interpreting command/address logic ".The entirety of these documents is open to lead to for all purposes
It crosses reference and is incorporated herein.
Technical field
Example described herein is usually directed to dual inline memory modules（DIMM）On memory device.
Background technology
With computing platform or system（Such as it is configured to those of server computing platform or system）The memory mould of coupling
Block may include dual inline memory modules（DIMM）.DIMM may include various types of memories, including volatibility
Or the memory of nonvolatile type.As memory technology has advanced to including with increasingly high density of memory list
The memory capacity of member, DIMM has also considerably increased.Moreover, to be written to memory included in DIMM for access
Or the progress of the data rate for the data being read from enables mass data to be wrapped in needing the requesting party and DIMM that access
It is flowed between the memory device included.Higher data rate may cause to be transmitted to the memory included by DIMM/from its
The increased frequency of the signal of transmission.
Description of the drawings
Fig. 1 shows example system.
Fig. 2 shows dual inline memory modules（DIMM）Example first part.
Fig. 3 shows the example second part of DIMM.
Fig. 4 shows example pin figure.
Fig. 5 shows example memory devices logic.
Fig. 6 shows example apparatus.
Fig. 7 shows the first logic flow of example.
Fig. 8 shows the first logic flow of example.
Fig. 9 shows exemplary storage medium.
Figure 10 shows example calculations platform.
Specific implementation mode
As contemplated by the disclosure, for access to be written to DIMM memory or memory device or from its
The higher data rate of the data of reading can cause to be transmitted to DIMM memory device/from the increased of its signal transmitted
Frequency.It may be implemented for improving signal integrity and saving power to include command/address signal mirror image or reversion
（inversion）Technology.
In some instances, when the interconnection branch line between the memory device on the opposite side of DIMM（stub）It is minimum
Change or be made as far as possible in short-term, can execute best to transmit the memory bus of data via increased frequency.Some are existing
There is DIMM that can use special " mirror image " encapsulation or bear long branch line and associated suboptimum signal routing.Other DIMM can
To dispose this by the encapsulation without using different mirror images.But these other DIMM can be directed to the pin of memory device
The mirror image of command/address is executed, the pin can be exchanged in the case of not varying functionality.For example, can be pure
Pin for address bit.For example, the pin for command bit can not be exchanged.For the reversion for command/address signal
Such exchange may there is a situation where identical.This can considerably limit the quantity for the pin that can be used for mirror image.
Moreover, in current computing system how in some examples by the memory device in DIMM to realize reversion,
Memory Controller can use multiple command cycles during initialization.The period 1 can be normally issued, and second round
The copy of same commands can be issued in the case of logic inversion.This may apply host memory controller extremely complex
Requirement overturn or invert position.
Fig. 1 shows system 100.As shown in Figure 1, in some instances, system 100 includes being coupled to DIMM
The host 110 of 120-1 to 120-n, wherein " n " is any positive integer with the value more than 2.For these examples, DIMM
120-1 to 120-n can be coupled to host 110 via one or more channel 140-1 to 140-n.As shown in fig. 1
, host 110 may include operating system（OS）114, one or more application（（It is one or more）App）116 and circuit
112.Circuit 112 may include the one or more processing elements 111 coupled with Memory Controller 113（For example, processor or
Processor core）.Host 110 can include but is not limited to personal computer, desktop PC, laptop computer, tablet meter
It is calculation machine, server, server array or server farm, web server, network server, Internet server, work station, small
Type computer, mainframe computer, supercomputer, network equipment, web equipments, distributed computing system, multicomputer system,
Processor-based system, or combinations thereof.
In some instances, as shown in Figure 1, DIMM 120-1 to 120-n may include corresponding memory dice
Or device 120-1 to 120-n.Memory device 120-1 to 120-n may include various types of volatibility and/or non-volatile
Property memory.Volatile memory can include but is not limited to random access memory（RAM）, dynamic ram（D-RAM）, it is double
Data rate synchronous dynamic ram（DDR SDRAM）, static RAM（SRAM）, thyristor RAM（T-RAM）Or zero
Capacitor RAM（Z-RAM）.Nonvolatile memory can include but is not limited to the memory of nonvolatile type（Such as byte
Or 3 dimensions of block addressable（3-D）Cross point memory）.These block addressables of memory device 120-1 to 120-n can word
The memory of section addressing nonvolatile type may include but be not limited to use chalcogenide phase change material（For example, chalkogenide glass
Glass）Memory, multi-threshold grade NAND flash, NOR flash memory, single-stage or multi-level phase change memory（PCM）, electricity
Hinder memory, nanometer linear memory, ferroelectric transistor random access memory（FeTRAM）, in conjunction with memristor technology magnetic resistance with
Machine accesses memory（MRAM）Memory or spin-transfer torque MRAM（STT-MRAM）Or the combination or other of any of the above
Types of non-volatile.
According to some examples, including the memory of volatibility and/or nonvolatile type memory device 122-1 extremely
122-n can be according to multiple memorizers technology（Such as just developing with the associated new technologies of DIMM comprising but be not limited to DDR5
（DDR versions 5, are currently discussed by JEDEC）,LPDDR5（LPDDR versions 5, are currently discussed by JEDEC）,HBM2（HBM version 2s,
Currently discussed by JEDEC）, and/or derivative or extension based on such specification other new technologies）And it operates.Memory device
Setting 122-1 to 122-n can also be according to other memory technology（Such as, but not limited to DDR4（Double Data Rate（DDR）Version
4, by JEDEC initial specifications are announced in September, 2012）,LPDDR4（Low power double data rate（LPDDR）Edition 4,
JESD209-4 is initially published by JEDEC in August, 2014）,WIO2（Wide I/O 2（WideIO2）, JESD229-2, by JEDEC
It is initially published in August, 2014）,HBM（High bandwidth memory DRAM, JESD235, it is initially public in October, 2013 by JEDEC
Cloth）, and/or derivative or extension based on these specifications other technologies）And it operates.
According to some examples, DIMM 120-1 to 120-n can be designed as the DIMM of registration（RDIMM）, load
The DIMM of reduction（LRDIMM）, low-power DIMM（LPDIMM）, full buffer DIMM（FB-DIMM）, the DIMM that does not buffer
（UDIMM）Or small shape（small outline）（SODIMM）.Example is not limited to only these DIMM designs.
In some instances, may include volatile in the memory device 122-1 to 122-n of DIMM 120-1 to 120-n
The whole or combination of property or the type of nonvolatile memory.For example, the memory device 122-1 in DIMM 120-1 can be wrapped
Include the volatile memory on front side or the first side（For example, DRAM）, and may include non-volatile in back side or the second side
Property memory（For example, 3D cross point memories）.In other examples, mixing DIMM may include appointing for DIMM 120-1
The combination of the memory of the non-volatile and volatile type of memory device 122-1 on side.In other examples, own
Memory device 122-1 can be volatile like the memory of type or the memory of nonvolatile type.In some instances, more
A channel can be coupled with the memory device maintained on DIMM, and in some instances, and the channel of separation can be by cloth
Line is to different non-volatile/volatile types and/or the memory device of group.For example, to including nonvolatile memory
Memory device first passage and second channel to the memory device including volatile memory.In other examples
In, first passage can be routed to the memory device on the first side of DIMM, and second channel is routed to DIMM's
Memory device in the second side.Example be not limited to can how by multiple channel routings to being included in depositing on single DIMM
The above example of reservoir device.
Fig. 2 shows example DIMM portions 200.In some instances, DIMM portion 200 shows double sided memory modules
How sub-assembly is can be in printed circuit board（PCB）Have on 203 opposite side memory device or tube core 201 and 202 and
The shared public address bus for command/address bus A and B.For these examples, the pin 212 on memory device 201
Become the mirror image of the pin 222 and 224 on the memory device 202 for common command/address bus A and B with 214.
In some instances, the mirror image on the either side of PCT 203 or connection between identical pin caused by point
Branch line（By in Fig. 2 alphabetical A and B described）, PCB layout resource may be consumed and bus frequency scaling may be influenced.Such as
It more describes below, the length of this branch line can be reduced for realizing the technology of mirror image.However, DIMM portion 200 is shown
Example when mirror image is not implemented.
Fig. 3 shows example DIMM portion 300.In some instances, command/address signal can be filled in target memory
The place of setting is exchanged so that command/address signal can be consistent between the memory device on the opposite side of PCB 303.
Therefore, the public through-hole by PCB 303 can be shared, as shown in Figure 3.Now, order/ground of such as command/address A
Location signal can be connected to the pin 322 of memory device 320, and can also be connected to the pin of memory device 310
312, to form shortest path or branch line between these memory devices（It is routed through PCB 303）.As it is following more
It describes more, short circuit pin can be utilized on given memory device（strap pin）To indicate given command/address pin
It has been mirrored.For example, what is indicated in the command/address signal received via command/address A at pin 322 arrives memory
First command/address of device 320 can be the mirror image of the second command/address to memory device 310 at pin 312,
Or vice versa.
According to some examples, DIMM can be used in register buffer（It is not shown）Circuit or logic come generate life
The additional copies of order/address bus are to reduce bus load.For these examples, in the logic and/or electricity of register buffer
Road can make the multiple total segments for the memory device being routed to from register buffer on DIMM propagate command/address signal.
The command/address signal propagated can indicate the corresponding command/address logic with the logical level inverted relative to each other.
The reversion of the logical level indicated in the command/address signal of these propagation can improve power efficiency and signal integrity.
However, referring in memory device and/or in the circuit and/or logic of register buffer need to know command/address signal
The command/address logic shown has been inverted.In some instances, another short circuit pin or position can be utilized so that in register
The memory device and/or logic of buffer can cancel reversion（un-invert）The order indicated in command/address signal/
Address logic interprets for correct command/address logic.
Fig. 4 shows example pin Figure 40 0.In some instances, pinouts 400, which can be used for having, is included in DIMM
On DRAM memory device.For these examples, frame F2（Mirror image）And G2（CAI）In pinouts 400 in indicate it is short
It connects pin and may indicate that whether memory device is answered the command/address that is indicated in mirroring command/address signal and/or will be received
The command/address logic indicated in command/address signal is interpreted as being inverted.
According to some examples, according to the MIRROR pins for the target memory device that pinouts 400 designs（F2）It can be connected
It is connected to power pin, such as output storage drain electrode power voltage（VDDQ）Pin（Such as H1）.For these examples, target storage
Device device can the internal command/address by even-numbered（CA）It is swapped to the CA of next higher corresponding odd-numbered,
So that given CA is mirrored to target memory device.Example exchange pair for giving CA come mirror image according to pinouts 400 can
To include by CA2 and CA3（It is not CA1）It swaps, by CA4 and CA5（It is not CA3）It swaps, by CA6 and CA7（It is not
CA5）It swaps.In some instances, MIRROR pins can be bound or be connected to grounding pin, such as VSSQ pins
（For example, G1）（If not requiring or not needing CA and exchange）.
In some instances, in CAI（Command address inverts）Pin is connected to VDDQ（For example, H1）In the case of, quilt
Being designed for use with the memory device of such as pinouts of pinouts 400 internal can be reversed in the command/address signal of reception（Example
Such as, it is route from register buffer）The command/address logical level of middle instruction.According to some examples, if order/ground
Location logic however be interpreted as being inverted, then CAI pins can be connected or be tied to such as VSSQ pins（For example, H1）Ground connection
Pin.
Two independent short circuit pins of MIRROR and CAI can allow four kinds of different combinations, may include [no mirror
Picture, no reversion], [no mirror image, reversion], [mirror image, no reversion] or [mirror image inverts].
Fig. 5 shows example memory devices logic 500.In some instances, as shown in Figure 5, it can be based on
Whether one or two of the short circuit pin 501 of MIRROR or the short circuit pin 502 of CAI, which have been connected to power/VDDQ, is drawn
Foot（Generate 1）Or it is connected to ground connection/VSSQ pins（Generate 0）To activate the circuit of memory device logic 500.Such as institute in Fig. 5
Show, if logic 1 were generated from short circuit pin 501, including the memory device of memory device logic 500 could be via would making
Passed through to overturn with multiplexer 530（Command/address CA0 is to CA13's）The command/address signal that CMD/ADD pins 510 receive.
Moreover, if generate logic 1 from short circuit pin 502, including the memory device of memory device logic 500 can be via making
Passed through to invert with XOR gate 520（Command/address CA0 is to CA13's）In the command/address signal that CMD/ADD pins 510 receive
The command/address logic of instruction.
Fig. 6 shows the example block diagram of equipment 600.Although equipment 600 shown in Fig. 6 has limited in some topology
The element of quantity, it will be appreciated that, equipment 600 such as can realize that desired in alternate topologies includes more for given
Or less element.
Equipment 600 can be supported that circuit 620 is maintained at or positioned at via one or more channels and master by circuit 620
At memory device on the DIMM of machine coupling.Circuit 620, which can be arranged to, executes one or more softwares or firmware realizes
Component or logic 622-a.It is worth noting that, " a " is intended that with " b " with " c " and similar indicator as used herein
Indicate the variable of any positive integer.Thus, for example, if realizing the value of setting a=3, the software of component or logic 622-a or
The full set of firmware may include component or logic 622-1 or 622-2.The example context without being limited thereto that is presented and lead to
The different variables that a piece uses can indicate identical or different integer value.Moreover, these ' components ' or " logic " can be storages
Software/firmware in computer-readable medium, and although component is shown as discrete frame in figure 6, this is not by these
Component is limited to different computer-readable medium components（For example, individual memory etc.）In storage device.
According to some examples, circuit 620 may include processor or processor circuit.Processor or processor circuit can be with
It is any one of various commercially available processors, including but not limited to AMD Athlon, Duron and Opteron
Processor；ARM is applied, embedded and safe processor；IBM and Motorola DragonBall and PowerPC
Processor；IBM and Sony Cell processors；Intel® Atom®,Celeron®,Core（2）Duo®,Core
I3, Core i5, Core i7, Itanium, Pentium, Xeon, Xeon Phi and XScale processors；And
Similar processor.According to some examples, circuit 620 can also be application-specific integrated circuit（ASIC）, and at least some components
Or logic 622-a can be implemented as the hardware element of ASIC.
According to some examples, equipment 600 may include mirror logic 622-1.Mirror logic 622-1 can be by circuit 620
To execute to receive instruction to the first order/ground of the first command/address of the target memory device that may include equipment 600
Location signal.Target memory device can be on the first side of DIMM.Command/address signal can be included in and want mirror image
In CMD/ADD 605.Mirror logic 622-1 then can be with the first command/address of mirror image so that is indicated in command/address signal
The first command/address be mirror image to the second command/address of the memory device in the second side of DIMM.Mirroring command/
Address can be included in the CMD/ADD 630 of mirror image.
In some instances, equipment 600 can also include reverse logic 622-2.Reverse logic 622-2 can be by circuit
620 come execute at the memory device including equipment 600 receive command/address signal.Reverse logic 622-2 can be based on
Whether the short circuit pin of memory device has been inverted and so come the command/address logic for determining by command/address signal designation
Interpret the command/address logic by command/address signal designation based on the determination afterwards.The command/address logic of reversion can
The command/address logic for being included in CMD/ADD signals 610, and interpreting can be included in the CMD/ADD logics of interpretation
In 635.
Fig. 7 shows example logic flow 700.As shown in Figure 7, the first logic flow includes logic flow 700.It patrols
Collecting flow 700 can indicate by one or more logics, feature or device described herein（Such as, equipment 700）Performed
Some or all operations.More specifically, logic flow 700 can be realized by mirror logic 622-1.
According to some examples, in frame 702, logic flow 700 can receive instruction and be deposited to the target on the first side of DIMM
The command/address signal of first command/address of reservoir device.For these examples, mirror logic 622-1 can receive life
Order/address signal.
In some instances, in frame 704, logic flow 700 can the short circuit pin based on target memory device come really
Surely the first command/address being mirrored, being indicated in command/address signal.For these examples, mirror logic 622-2
It can carry out this determination.
According to some examples, in frame 706, the first command/address can be mirrored to target memory dress by logic flow 700
It sets so that the first command/address indicated in command/address signal is the non-targeted memory device onto the second side of DIMM
The second command/address mirror image.For these examples, the first command/address can be mirrored to target by mirror logic 622-1
Memory device.
Fig. 8 shows example logic flow 800.As shown in Figure 8, the first logic flow includes logic flow 800.It patrols
Collecting flow 800 can indicate by one or more logics, feature or device described herein（Such as, equipment 800）Performed
Some or all operations.More specifically, logic flow 800 can be realized by reverse logic 622-1.
According to some examples, in frame 802, logic flow 800 can receive command/address in the memory device on DIMM
Signal.For these examples, reverse logic 622-1 can receive command/address signal.
In some instances, in frame 804, logic flow 800 can based on the short circuit pin of memory device come determine by
Whether the command/address logic of command/address signal designation has been inverted.For these examples, reverse logic 822-2 can be true
Determine whether command/address logic has been inverted.
According to some examples, in frame 806, logic flow 800 can be based on the order/ground indicated in command/address signal
The determination that location logic has been inverted interprets the command/address logic by command/address signal designation.For these examples, instead
Command/address logic can be interpreted based on the determination by turning logic 822-2.
Fig. 9 shows exemplary storage medium 900.As shown in Figure 9, the first storage medium includes storage medium 900.It deposits
Storage media 900 may include product.In some instances, storage medium 900 may include readable Jie of any non-transient computer
Matter or machine readable media, such as light, magnetic or semiconductor storage.Storage medium 900 can store various types of calculating
Machine executable instruction, such as instruction for realizing logic flow 700 or 800.Computer-readable or machine readable storage medium
Example may include that can store any tangible medium of electronic data, including volatile memory or non-volatile memories
Device, removable or non-removable memory, erasable or nonerasable memory, writeable or recordable memory etc..It calculates
The example of machine executable instruction may include the code of any suitable type, such as source code, compiled code, interpreted code, can
Execute code, static code, dynamic code, object-oriented code, visual code etc..Example context without being limited thereto.
Figure 10 shows example calculations platform 1000.In some instances, as shown in Figure 10, computing platform 1000 can
To include storage system 1030, processing component 1040, other platform assemblies 1050 or communication interface 1060.Shown according to some
Example, computing platform 1000 can be implemented in computing device.
According to some examples, storage system 1030 may include controller 1032 and one or more memory devices
1034.For these examples, resides in or the logic at controller 1032 and/or feature can execute equipment 600 extremely
Lack some processing operations or logic and may include storage medium（It includes storage medium 1000）.In addition, one or more
Memory device 1034 may include the volatibility or nonvolatile memory of similar type（It is not shown）, above for figure
Memory device 122,210,220,310 or 320 shown in 1-3 describes.In some instances, controller 1032 can be with
A part for 1034 identical tube core of one or more memory devices.In other examples, controller 1032 and one or more
A memory device 1034 can be located on tube core identical with processor or integrated circuit（E.g., including in processing component
In 1040）.In other examples, controller 1032 can couple or on it with one or more memory devices 1034 again
Single tube core or integrated circuit in.
According to some examples, processing component 1040 may include the combination of various hardware elements, software element or both.Firmly
The example of part element may include device, logic device, component, processor, microprocessor, circuit, processor circuit, circuit elements
Part（For example, transistor, resistor, capacitor, inductor etc.）, integrated circuit, ASIC, programmable logic device（PLD）, number
Word signal processor（DSP）, FPGA/programmable logic, memory cell, logic gate, register, semiconductor device, chip,
Microchip, chipset etc..The example of software element may include component software, program, application, computer program, using journey
Sequence, system program, software development procedures, machine program, operating system software, middleware, firmware, software module, routine, sub- example
Journey, function, method, process, software interface, API, instruction set, calculation code, computer code, code segment, computer code
Section, word, value, symbol, or any combination thereof.It is such as desired for given example, it is determined whether to use hardware element and/or soft
Part element implementation example can change according to any amount of factor, and the factor is all computation rates as desired, power
Rank, heat resistance, process cycle budget, input data rate, output data rate, memory resource, data bus speed and
Other designs or performance constraints.
In some instances, other platform assemblies 1050 may include common computing element, such as one or more processing
Device, coprocessor, memory cell, chipset, controller, peripheral hardware, interface, oscillator, timing means, regards multi-core processor
Frequency card, audio card, multimedia I/O components（For example, digital display）, power supply etc..With other platform assemblies 1050 or
The example of 1030 associated memory cell of storage system can include but is not limited to, with one or more higher speed memory lists
The various types of computer-readable and machine readable storage medium of the form of member, such as read-only memory（ROM）,RAM,
DRAM, DDR DRAM, synchronous dram（SDRAM）, DDR SDRAM, SRAM, programming ROM（PROM）, EPROM, EEPROM, sudden strain of a muscle
Fast memory, ferroelectric memory, SONOS memories, polymer memory（Such as ferroelectric polymer memory）, nano wire,
FeTRAM or FeRAM, ovonic memory, phase transition storage, memristor, STT-MRAM, magnetic or optical card and suitable for depositing
Store up the storage medium of any other type of information.
In some instances, communication interface 1060 may include the logic and/or feature for supporting communication interface.For
These examples, communication interface 1060 may include one or more communication interfaces, be carried out according to various communication protocols or standard
Operation by direct or network communication link to be communicated.Direct communication can be via using one or more professional standards
（Including offspring and variant）Described in communication protocol or standard（Such as with SMBus specifications, PCIe specification, NVMe specifications, SATA
Specification, SAS specification or the associated standard of USB specification）Occurred by direct interface.Network communication can be via using communication protocols
View or standard（Standard those of described in one or more ethernet standards such as by IEEE announcements）Pass through network interface
And occur.For example, a kind of such ethernet standard may include IEEE 802.3-2012 of in December, 2012 publication, " with punching
The Carrier Sense Multiple Access of prominent detection（CSMA/CD）Access method and physical layer specification "（"Carrier sense
Multiple access with Collision Detection （CSMA/CD） Access Method and Physical
Layer Specifications"）（Hereinafter referred to as " IEEE 802.3 "）.
Computing platform 1000 can be a part for computing device, and the computing device can be such as user equipment, meter
Calculation machine, personal computer（PC）, desktop PC, laptop computer, notebook computer, netbook computer, tablet
Computer, smart mobile phone, embedded electronic device, game console, server, server array or server farm, web clothes
Business device, network server, Internet server, work station, minicomputer, mainframe computers, supercomputer, network dress
Standby, web equipments, distributed computing system, multicomputer system, processor-based system, or combinations thereof.Correspondingly, as suitable
It closes desired, computing platform 1000 described herein can be included or omitted in the various embodiments of computing platform 1000
Function and/or specific configuration.
Computing platform can be realized using any combinations of discrete circuit, ASIC, logic gate and/or single-chip framework
1000 component and feature.In addition, the feature of computing platform 1000 can in the case that be suitble to it is appropriate using microcontroller, can
Programmed logic array (PLA) and/or microprocessor or any combinations above-mentioned are realized.Notice hardware, firmware and/or software element
It can collectively referred to herein as or independently be known as " logic ", " circuit（Circuit or circuitry）".
At least one exemplary one or more aspects can be by the expression that is stored at least one machine readable media
Property instruction realize that the representative instruciton indicates the various logic in processor, the logic when by machine, computing device or
When system is read, machine, computing device or system is made to manufacture logic to execute technique described herein.Such expression can be stored in
On tangible machine readable media and it is supplied to various clients or makes facility to be loaded into actual manufacture logic or processing
In the manufacture machine of device.
Various examples can be realized using the combination of hardware element, software element or both.In some instances, hardware
Element may include device, component, processor, microprocessor, circuit, circuit element（For example, transistor, resistor, capacitance
Device, inductor etc.）, integrated circuit, ASIC, PLD, DSP, FPGA, memory cell, logic gate, register, semiconductor dress
It sets, chip, microchip, chipset etc..In some instances, software element may include component software, program, application, meter
Calculation machine program, application program, system program, machine program, operating system software, middleware, firmware, software module, routine, son
Routine, function, method, process, software interface, API, instruction set, calculation code, computer code, code segment, computer code
Section, word, value, symbol, or any combination thereof.It is such as desired for given example, it is determined whether to use hardware element and/or soft
Part element implementation example can change according to any amount of factor, such as desired computation rate, power level, heat-resisting
Property, process cycle budget, input data rate, output data rate, memory resource, data bus speed and it is other design or
Performance constraints.
Some examples may include product or at least one computer-readable medium.Computer-readable medium may include using
In the non-transient storage media of storage logic.In some instances, non-transient storage media may include that can store electron number
According to one or more types computer readable storage medium, including it is volatile memory or nonvolatile memory, removable
It removes or non-removable memory, erasable or nonerasable memory, writeable or rewritable memory, etc..Show at some
In example, logic may include various software elements, such as component software, program, application, computer program, application program, system
It is program, machine program, operating system software, middleware, firmware, software module, routine, subroutine, function, method, process, soft
Part interface, API, instruction set, calculation code, computer code, code segment, computer code segments, word, value, symbol or its is any
Combination.
According to some examples, computer-readable medium may include for store or the non-transient storage of maintenance instruction be situated between
Matter, described instruction make machine, computing device or system according to described example when being executed by machine, computing device or system
Execution method and/or operation.Instruction may include the code of any suitable type（Such as source code, compiled code, interpretation generation
Code, executable code, static code, dynamic code etc.）.Can according to predefined computer language, mode or grammer come
It realizes instruction, some function is executed for instruction machine, computing device or system.It can use any suitable advanced, low
Grade, object-oriented, visual, compiling and/or the programming language of interpretation instruct to realize.
Some examples can be described together with its derivative words using expression " in one example " or " example ".These terms
Mean to contact the specific features of the example description, structure or characteristic is included at least one example.In the description
The appearance of phrase " in one example " in various positions is not necessarily all referring to identical example.
Some examples can be described together with its derivative words using expression " coupling " and " connection ".These terms are not necessarily anticipated
Figure is used as mutual synonym.For example, the description using term " connection " and/or " coupling " can indicate two or more yuan
Part physically or electrically contacts directly with one another.However, term " coupling " can also mean that two or more elements are not direct each other
Contact, but also still cooperate or interact with.
Following example is related to the additional example of presently disclosed technology.
A kind of 1. example apparatus of example may include：The circuit of memory device on the first side of DIMM.The electricity
Road may include logic, and at least part of the logic is hardware, and the logic can receive instruction and be stored to the target
The command/address signal of first command/address of device device.The short circuit that the logic is also based on the memory device draws
Foot determines first command/address for wanting to indicate in command/address signal described in mirror image.The logic can also will be described
First command/address is mirrored to the memory device so that and first order indicated in the command/address signal/
Address is the mirror image to the second command/address of the memory device in the second side of the DIMM.
The equipment of example 2. as described in example 1, for first command/address to be mirrored to the target memory
The logic of device may include for will arrive the command/address of the corresponding even-numbered of the target memory device and arrive
The logic that the command/address of corresponding next higher odd-numbered of the target memory device swaps.
The equipment of example 3. as described in example 1, for determining the command/address signal based on the short circuit pin
First command/address of middle instruction is that the logic of the mirror image of second command/address includes for determining
The short circuit pin is connected to the logic of the power pin of the target memory device.
Equipment of the example 4. as described in example 3, the power pin include VDDQ pins.
The equipment of example 5. as described in example 1, the DIMM can be RDIMM, LPDIMM, LRDIMM, FB-DIMM,
UDIMM or SODIMM.
The equipment of example 6. as described in example 1, the memory device may include nonvolatile memory or volatibility
Memory.
Equipment of the example 7. as described in example 6, the volatile memory can be DRAM.
Equipment of the example 8. as described in example 6, the nonvolatile memory can be three dimensional intersection point memory, make
With the memory of chalcogenide phase change material, multi-threshold grade NAND flash, NOR flash memory, single-stage or multistage
PCM, Memister, formula memory difficult to understand, nanometer linear memory, FeTRAM, in conjunction with memristor technology mram memory or
STT-MRAM。
A kind of 9. exemplary method of example may include：By the circuit of the target memory device on the first side of DIMM
To receive the command/address signal that the first command/address of the target memory device is arrived in instruction.The method can also wrap
The short circuit pin based on the target memory device is included to determine want to indicate in command/address signal described in mirror image described
One command/address.The method can also include that first command/address is mirrored to the target memory device, make
First command/address that indicates in the command/address signal is that non-targeted onto the second side of the DIMM is deposited
The mirror image of second command/address of reservoir device.
First command/address is mirrored to the target memory device by method of the example 10. as described in example 9
May include the corresponding even-numbered that will arrive the target memory device command/address with arrive the target memory device
The command/address of corresponding next higher odd-numbered swap.
Method of the example 11. as described in example 9 determines the command/address signal middle finger based on the short circuit pin
First command/address shown is that the mirror image of second command/address may include that the short circuit pin is connected
To the power pin of the target memory device.
Method of the example 12. as described in example 11, the power pin can be VDDQ pins.
Method of the example 13. as described in example 9, the DIMM can be RDIMM, LPDIMM, LRDIMM, FB-DIMM,
UDIMM or SODIMM.
Method of the example 14. as described in example 9, the memory device may include nonvolatile memory or volatile
Property memory.
Method of the example 15. as described in example 14, the volatile memory can be DRAM.
Method of the example 16. as described in example 14, the nonvolatile memory can be three dimensional intersection point memory,
Use the memory of chalcogenide phase change material, multi-threshold grade NAND flash, NOR flash memory, single-stage or multistage
PCM, Memister, formula memory difficult to understand, nanometer linear memory, FeTRAM, in conjunction with memristor technology mram memory or
STT-MRAM。
17. example at least one machine readable media of example, may include multiple instruction, described instruction is in response to by being
System executes the method that the system can be made to carry out according to any one of example 9 to 16.
A kind of 18. example apparatus of example may include the portion of the method for executing any one of example 9 to 16
Part.
A kind of 19. example apparatus of example may include the circuit of the memory device on the first side of DIMM, the electricity
Road includes logic, and at least part of the logic can be hardware, and the logic can receive command/address signal.It is described
Logic is also based on the short circuit pin of the memory device to determine by order/ground of the command/address signal designation
Whether location logic has been inverted.The logic is also based on the determination to interpret by the command/address signal designation
The command/address logic.
Equipment of the example 20. as described in example 19, the logic can be connected to the mesh based on the short circuit pin
The power pin for marking memory device, determines that command/address logic described in the command/address signal designation has been inverted.
Equipment of the example 21. as described in example 20, the power pin can be VDDQ pins.
Equipment of the example 22. as described in example 19, by the command/address logic of the command/address signal designation
It can be inverted by the circuit of the register buffer of the DIMM.
Equipment of the example 23. as described in example 19, the DIMM can be RDIMM, LPDIMM, LRDIMM, FB-DIMM,
UDIMM or SODIMM.
Equipment of the example 24. as described in example 19, the memory device may include nonvolatile memory or volatile
Property memory.
Equipment of the example 25. as described in example 24, the volatile memory can be DRAM.
Equipment of the example 26. as described in example 24, the nonvolatile memory can be three dimensional intersection point memory,
Use the memory of chalcogenide phase change material, multi-threshold grade NAND flash, NOR flash memory, single-stage or multistage
PCM, Memister, formula memory difficult to understand, nanometer linear memory, FeTRAM, in conjunction with memristor technology mram memory or
STT-MRAM。
A kind of 27. exemplary method of example, including may include by the target memory device on DIMM come receive order/
Address signal.The method can also include being determined by the command/address based on the short circuit pin of the memory device
Whether the command/address logic of signal designation has been inverted.The method can also include being interpreted based on the determination by institute
State the command/address logic of command/address signal designation.
Method of the example 28. as described in example 27 can also include being connected to the target based on the short circuit pin
The power pin of memory device determines that command/address logic described in the command/address signal designation has been inverted.
Method of the example 29. as described in example 28, the power pin can be VDDQ pins.
Method of the example 30. as described in example 27, by the command/address logic of the command/address signal designation
It can be inverted by the circuit of the register buffer of the DIMM.
Method of the example 31. as described in example 27, the DIMM can be RDIMM, LPDIMM, LRDIMM, FB-DIMM,
UDIMM or SODIMM.
Method of the example 32. as described in example 27, the memory device may include nonvolatile memory or volatile
Property memory.
Method of the example 33. as described in example 32, the volatile memory can be DRAM.
Method of the example 34. as described in example 32, the nonvolatile memory can be three dimensional intersection point memory,
Use the memory of chalcogenide phase change material, multi-threshold grade NAND flash, NOR flash memory, single-stage or multistage
PCM, Memister, formula memory difficult to understand, nanometer linear memory, FeTRAM, in conjunction with memristor technology mram memory or
STT-MRAM。
35. example at least one machine readable media of example, may include multiple instruction, described instruction is in response to by being
System executes the method that the system can be made to carry out according to any one of example 27 to 34.
A kind of 36. example apparatus of example may include the portion of the method for executing any one of example 27 to 34
Part.
A kind of 37. example system of example, may include DIMM, and the DIMM includes one or more the on the first side
One or more second memory devices on one memory device and the second side.The system can also include coming from described one
Memory device among a or multiple first memory devices, the memory device have the first short circuit pin and include
At least part of logic, the logic can be hardware.For these examples, the logic can receive the first order/ground
Location signal, the signal designation are set to the first command/address of target with the memory device.The logic can also determine institute
State whether the first short circuit pin is connected to power pin.The logic is also based on the determination and carrys out mirror image with the storage
Device device is first command/address of target so that first life indicated in the first command/address signal
Order/address is to the storage among one or more of second memory devices in the second side of the DIMM
The mirror image of second command/address of device device.
System of the example 38. as described in example 37, for being mirrored to first command/address from the one one
Or the logic of the memory device among multiple memory devices may include that will arrive from first one or more storages
The command/address of the corresponding even-numbered of the memory device among device device is stored with to from the first one or more
The logic that the command/address of corresponding next higher odd-numbered of the memory device among device device swaps.
System of the example 39. as described in example 37, the power pin can be VDDQ pins.
System of the example 40. as described in example 37, among one or more of first memory devices described in
Memory device can have the second short circuit pin.For these examples, the memory device can also include logic, described
Logic can receive the second command/address signal, and be connected to based on the second short circuit pin and drawn with first short circuit
Power pin that foot is connected to identical or different power pin is interpreted by the life of the second command/address signal designation
Order/address logic so that be interpreted as being inverted by the command/address logic of the second command/address signal designation.
System of the example 41. as described in example 40, it is identical as the power pin that the first short circuit pin is connected to or
Different power pins can be identical or different VDDQ pins.
System of the example 42. as described in example 40, by the command/address of the second command/address signal designation
Logic can be inverted by the circuit of the register buffer of the DIMM.
System of the example 43. as described in example 37, the DIMM can be RDIMM, LPDIMM, LRDIMM, FB-DIMM,
UDIMM or SODIMM.
System of the example 44. as described in example 37, the memory device may include nonvolatile memory or volatile
Property memory.
System of the example 45. as described in example 44, the volatile memory can be DRAM.
System of the example 46. as described in example 44, the nonvolatile memory can be three dimensional intersection point memory,
Use the memory of chalcogenide phase change material, multi-threshold grade NAND flash, NOR flash memory, single-stage or multistage
PCM, Memister, formula memory difficult to understand, nanometer linear memory, FeTRAM, in conjunction with memristor technology mram memory or
STT-MRAM。
, it is emphasized that providing the abstract of the disclosure to meet 37 C.F.R. chapters and sections 1.72（b）, it is required that reader will be allowed
Quickly determine the abstract of property disclosed in technology.It is claimed by following understanding：It will be not used in interpretation or limitation example
Range or meaning.In addition, in specific implementation mode in front, it can be seen that in order to simplify the purpose of the disclosure, various spies
Sign is aggregated together in single example.Disclosed the method not be interpreted as reflecting that example claimed requires ratio
The intention of the feature more features clearly described in each example.But as accompanying example is reflected, subject matter is few
In individually disclosing exemplary all features.Therefore, following example is hereby incorporated into specific implementation mode, wherein each example is only
It is vertical to be used as individual example.In being appended example, term " comprising " and it " wherein " is used separately as corresponding term " comprising " and " its
In " general English synonym.In addition, term " first ", " second ", " third " etc. are solely for label, and it is not intended to
Numerical requirements are applied to its object.
Although with to this theme of the specific language description of structural features and or methods of action, it is to be understood that accompanying example
Defined in theme be not necessarily limited to special characteristic described above or action.But disclose special characteristic described above
With action as the exemplary forms for realizing claim.
Claims (25)
1. a kind of equipment, including：
Dual inline memory modules（DIMM）The first side on memory device circuit, the circuit includes logic,
At least part of the logic includes hardware, and the logic is used for：
Receive the command/address signal that the first command/address of the target memory device is arrived in instruction；
Want to indicate in command/address signal described in mirror image described first is determined based on the short circuit pin of the memory device
Command/address；And
First command/address is mirrored to the memory device so that indicated in the command/address signal described
First command/address is the mirror image to the second command/address of the memory device in the second side of the DIMM.
2. equipment as described in claim 1, for first command/address to be mirrored to the target memory device
The logic includes for depositing the command/address for arriving the corresponding even-numbered of the target memory device with to the target
The logic that the command/address of corresponding next higher odd-numbered of reservoir device swaps.
3. equipment as described in claim 1 is indicated for being determined based on the short circuit pin in the command/address signal
First command/address be the logic of the mirror image of second command/address include described short for determining
Connect the logic that pin is connected to the power pin of the target memory device.
4. equipment as claimed in claim 3, the power pin includes output storage drain electrode power voltage（VDDQ）Pin.
5. equipment as described in claim 1, the DIMM includes the DIMM of registration（RDIMM）, low-power DIMM（LPDIMM）,
The reduced DIMM of load（LRDIMM）, full buffer DIMM（FB-DIMM）, the DIMM that does not buffer（UDIMM）Or small shape DIMM
（SODIMM）.
6. equipment as described in claim 1, including the memory device, the memory device will include non-volatile deposits
Reservoir or volatile memory, wherein the volatile memory includes dynamic random access memory（DRAM）And it is described non-
Volatile memory is included three dimensional intersection point memory, is dodged using memory, the multi-threshold grade NAND of chalcogenide phase change material
Fast memory, NOR flash memory, single-stage or multi-level phase change memory（PCM）, Memister, formula memory difficult to understand, nano wire
Memory, ferroelectric transistor random access memory（FeTRAM）, in conjunction with the magnetoresistive RAM of memristor technology
（MRAM）Memory or spin-transfer torque MRAM（STT-MRAM）.
7. a kind of method, including：
By dual inline memory modules（DIMM）The first side on target memory device at circuit come receive instruction
To the command/address signal of the first command/address of the target memory device；
Described in determining based on the short circuit pin of the target memory device and want to indicate in command/address signal described in mirror image
First command/address；And
First command/address is mirrored to the target memory device so that indicated in the command/address signal
First command/address is the mirror to the second command/address of the non-targeted memory device in the second side of the DIMM
Picture.
8. it includes inciting somebody to action that first command/address, which the method for claim 7, is mirrored to the target memory device,
To the target memory device corresponding even-numbered command/address to it is corresponding next to the target memory device
The command/address of higher odd-numbered swaps.
9. the institute indicated in the command/address signal the method for claim 7, is determined based on the short circuit pin
It includes that the short circuit pin is connected to the target to state the mirror image that the first command/address is second command/address
The power pin of memory device.
10. method as claimed in claim 9, the power pin includes output storage drain electrode power voltage（VDDQ）Pin.
11. a kind of equipment includes the component of the method for requiring any one of 7 to 10 for perform claim.
12. a kind of equipment, including：
Dual inline memory modules（DIMM）The first side on memory device circuit, the circuit includes logic,
At least part of the logic includes hardware, and the logic is used for：
Receive command/address signal；
It is determined by the command/address logic of the command/address signal designation based on the short circuit pin of the memory device
Whether it has been inverted；And
Interpret the command/address logic by the command/address signal designation based on the determination.
13. equipment as claimed in claim 12, including logic, the logic is used to be connected to institute based on the short circuit pin
The power pin for stating target memory device determines that command/address logic described in the command/address signal designation is anti-
Turn, wherein the power pin is output storage drain electrode power voltage（VDDQ）Pin and referred to by the command/address signal
The command/address logic shown is inverted by the circuit of the register buffer of the DIMM.
14. equipment as claimed in claim 13, the DIMM includes the DIMM of registration（RDIMM）, low-power DIMM
（LPDIMM）, the reduced DIMM of load（LRDIMM）, full buffer DIMM（FB-DIMM）, the DIMM that does not buffer（UDIMM）Or it is small
Shape DIMM（SODIMM）.
15. equipment as claimed in claim 12, including the memory device, the memory device will include non-volatile
Memory or volatile memory, the volatile memory include dynamic random access memory（DRAM）, described non-volatile
Property memory is included three dimensional intersection point memory, is deposited using memory, the multi-threshold grade NAND Flash of chalcogenide phase change material
Reservoir, NOR flash memory, single-stage or multi-level phase change memory（PCM）, Memister, formula memory difficult to understand, nano wire storage
Device, ferroelectric transistor random access memory（FeTRAM）, in conjunction with the magnetoresistive RAM of memristor technology（MRAM）
Memory or spin-transfer torque MRAM（STT-MRAM）.
16. a kind of method, including：
By dual inline memory modules（DIMM）On target memory device receive command/address signal；
It is determined by the command/address logic of the command/address signal designation based on the short circuit pin of the memory device
Whether it has been inverted；And
Interpret the command/address logic by the command/address signal designation based on the determination.
17. the method described in claim 16, including be based on the short circuit pin and be connected to the target memory device
Power pin, determine that command/address logic described in the command/address signal designation has been inverted, wherein the power draws
Foot is output storage drain electrode power voltage（VDDQ）Pin and by the command/address of the command/address signal designation
Logic is inverted by the circuit of the register buffer of the DIMM.
18. a kind of equipment includes the component of the method for requiring any one of 16 to 17 for perform claim.
19. a kind of system, including：
Dual inline memory modules（DIMM）, the dual inline memory modules（DIMM）Including one on the first side
One or more second memory devices on a or multiple first memory devices and the second side；And
Memory device among one or more of first memory devices, the memory device are short with first
It connects pin and includes logic, at least part of the logic includes hardware, and the logic will：
The first command/address signal is received, the signal designation is set to the first command/address of target with the memory device；
Determine whether the first short circuit pin is connected to power pin；And
Carry out first command/address that mirror image is set to target with the memory device based on the determination so that described first
First command/address indicated in command/address signal is to described one in the second side of the DIMM
The mirror image of second command/address of the memory device among a or multiple second memory devices.
20. system as claimed in claim 19, for being mirrored to first command/address from the first one or more
The logic of the memory device among memory device includes that will arrive among first one or more memory devices
The memory device corresponding even-numbered command/address among first one or more memory devices
The memory device corresponding next higher odd-numbered the logic that swaps of command/address.
21. system as claimed in claim 18, the power pin includes output storage drain electrode power voltage（VDDQ）Pin.
22. system as claimed in claim 19 includes being deposited from one or more of first with the second short circuit pin
The memory device among reservoir device, and further include logic, the logic is used for：
Receive the second command/address signal；And
It is identical or not based on the second short circuit pin is connected to the first short circuit pin is connected to power pin
With power pin interpret by the command/address logic of the second command/address signal designation so that ordered by described second
The command/address logic of order/address signal instruction is interpreted as being inverted, wherein being connected with the first short circuit pin
To the identical or different power pin of power pin include identical or different output storage drain electrode power voltage（VDDQ）Draw
Foot.
23. the system as claimed in claim 22 includes by the command/address of the second command/address signal designation
Logic is inverted by the circuit of the register buffer of the DIMM.
24. system as claimed in claim 19, the DIMM includes the DIMM of registration（RDIMM）, low-power DIMM
（LPDIMM）, the reduced DIMM of load（LRDIMM）, full buffer DIMM（FB-DIMM）, the DIMM that does not buffer（UDIMM）Or
Small shape DIMM（SODIMM）.
25. system as claimed in claim 19, including the memory device, the memory device will include non-volatile
Memory or volatile memory, the volatile memory include dynamic random access memory（DRAM）, described non-volatile
Property memory is included three dimensional intersection point memory, is deposited using memory, the multi-threshold grade NAND Flash of chalcogenide phase change material
Reservoir, NOR flash memory, single-stage or multi-level phase change memory（PCM）, Memister, formula memory difficult to understand, nano wire storage
Device, ferroelectric transistor random access memory（FeTRAM）, in conjunction with the magnetoresistive RAM of memristor technology（MRAM）
Memory or spin-transfer torque MRAM（STT-MRAM）.
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| US15/266991 | 2016-09-15 | ||
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Also Published As
| Publication number | Publication date |
|---|---|
| WO2017155608A1 (en) | 2017-09-14 |
| US20170255404A1 (en) | 2017-09-07 |
| US10802532B2 (en) | 2020-10-13 |
| CN114443520A (en) | 2022-05-06 |
| US10310547B2 (en) | 2019-06-04 |
| EP3423945A4 (en) | 2019-11-06 |
| CN108780421B (en) | 2024-01-02 |
| EP3423945A1 (en) | 2019-01-09 |
| EP4235439A1 (en) | 2023-08-30 |
| US20190354132A1 (en) | 2019-11-21 |
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