CN108736885B - Phase-locked loop clock edge triggered clock phase-splitting method - Google Patents

Abstract

The invention discloses a phase-locked loop clock edge triggered clock phase-splitting method, belongs to the field of time interval measurement, and aims to solve the problems of low resolution, high system running frequency and low performance of the conventional clock phase-splitting method. The specific process of the invention is as follows: inputting a clock signal of 100MHz to an input end of a phase-locked loop; frequency multiplication is carried out on the clock signal to 315MHz, and eight phase shifts are carried out on the high-level section; taking the edge of the clock signal after the frequency multiplication and phase shift of the phase-locked loop as a trigger signal; carrying out clock synchronization processing on the detected signal; respectively carrying out time sequence constraint on each transmission path of the clock signal and the signal to be tested; extracting the position where the level of the detected signal jumps at the trigger moment; outputting a high level when the rising edge detection function of the detected signal or the falling edge detection function of the detected signal has a rising edge, otherwise outputting a low level; and obtaining the relative position of the rising edge or the falling edge of the measured signal in one clock period. The invention is used for time interval measurement.

Description

Phase-locked loop clock edge-triggered clock phase splitting method

technical field

The invention relates to a time interval measurement method, which belongs to the field of time interval measurement.

Background technique

Time is one of the basic units of physics. What we usually mean by time has two meanings: one meaning refers to the moment, and the other refers to the time interval. Moment refers to a certain instant of time that continuously passes, which refers to when an event occurs; while time interval refers to how long the interval between two instants is, it refers to the duration of an event.

As a basic physical parameter in scientific research, scientific experiments and engineering technology, precise time provides an indispensable time-base coordinate for the measurement and quantitative research of all dynamic systems and time series processes. Precise time not only plays an important role in basic research fields such as nuclear physics research, particle physics research, geodynamics research, relativity research, pulsar cycle research and artificial satellite dynamics geodesy, but also plays an important role in such fields as aerospace, deep space communication. , satellite launch and monitoring, geological surveying and mapping, navigation communication, power transmission and scientific measurement and other applied research, national defense and national economic construction are also widely used, and have even penetrated into all aspects of people's social life, almost everything.

With the increasing improvement of people's living standards, high-resolution time interval measurement technology is increasingly used in various civil fields. The research on the time interval measurement method will greatly promote the development of key technologies in the fields of science and technology and civil use in our country. The traditional time interval measurement relies on analog measurement, but with the development of science and technology and the requirements of high precision and various limitations of analog measurement methods, this measurement method is far from meeting the needs of time interval measurement, so how to use digital The measurement time interval has become more and more important. Now digital measurement is mainly based on FPGA and ASIC. However, ASIC is limited in its application scope due to its long design cycle, large revision investment, and poor flexibility. However, FPGA has become the main platform for people to realize digital logic because of its advantages of fast running speed, programmability, short development cycle and strong flexibility. Therefore, it is of great practical significance to study the high-speed and precise time interval measurement technology based on FPGA.

Time-to-digital conversion circuit is the basic means of time measurement. It converts the analog signal carrying time information into digital signal and digitizes it, so as to realize the measurement of time information. On the other hand, absolute time information often does not have much meaning, but relative time information is meaningful, so many occasions are the measurement of time interval information.

In many applications, measurements of some physical quantities, such as flow, thickness, density, temperature, frequency, and phase shift, can be converted into measurements of time.

For example, pulsed laser ranging, its principle is similar to radar ranging. Generally, a laser diode is aimed at the target to emit laser pulses. After being reflected by the target, the laser scatters in all directions, and part of the scattered light returns to the sensor receiver and is captured by the optical system. Imaging onto an avalanche photodiode after reception. An avalanche photodiode is an optical sensor with an internal amplification function, so it can detect extremely weak light signals. Record and process the round-trip time from the time the light pulse is sent to when it is received back. Multiply the speed of light (300,000 km/s) by one-half of the round-trip time, which is the distance to be measured. If light travels in the air at a speed c, and the time required for a round trip between points A and B is t, then the distance D between points A and B can be expressed by the following formula:

D=ct/2 (1)

The widely used handheld and portable rangefinders have a range of hundreds of meters to tens of kilometers and a measurement accuracy of about five meters. The high-precision range finder developed in my country for satellite ranging can reach a measurement accuracy of several centimeters. Because the speed of light is so fast, the transit time laser sensor must determine the transit time extremely accurately. To achieve this resolution, the electronics of the transit time ranging sensor must be able to distinguish the following extremely short time intervals.

Or in some applications, it is necessary to control the thickness of metal sheets and pipe walls, etc., at this time, it is necessary to measure the thickness. The corresponding thickness information can be calculated by using the ultrasonic waves reflected by the ultrasonic waves on the surface and back of the object to be tested, and the speed of the ultrasonic waves in the corresponding medium. The most important thing here is the measurement of the time interval between the reflected ultrasonic waves. Therefore, it is of great practical significance to study the high-speed and precise time interval measurement technology.

In the early stage of the development of time measurement technology, electronic technologies such as semiconductor integrated circuits were relatively backward. In this period, analog measurement was the mainstream method of time interval measurement. Such as time amplification method, time-voltage conversion method, etc. These methods integrate the current in the time interval to be measured, convert the time amount that cannot be directly measured into a measurable amount of voltage or charge, and then go through A/D The conversion circuit converts into a digital quantity.

The ever-increasing demand for time measurement drives the development of time measurement technology. At this time, the shortcomings of analog measurement are increasingly exposed, such as being very sensitive to temperature, easily disturbed by external disturbances, complicated in design, and requiring a relatively long conversion time. Especially in high-energy physics experiments, it is difficult to use analog circuit measurement systems to meet the requirements, but digital technology has gradually become the development direction of detector electronics systems due to its flexibility, stability, high speed, parallel processing, and low cost. . As a result, digital measurement technology began to be favored and welcomed by researchers.

With the development of microelectronics technology and technology, digital integrated circuits have gradually developed from electronic tubes, transistors, small and medium-scale integrated circuits, and very large-scale integrated circuits to today's application-specific integrated circuits. The implementation of time-to-digital conversion technology has also completed the transition from separate devices to FPGAs and ASICs. Undoubtedly, the emergence of ASIC (Application-Specific Integrated Circuit) reduces the production cost of products, improves the reliability of the system, reduces the physical size of the design, and promotes the digitalization process of society. However, the limitation of the scope of application of ASIC due to its defects, as well as the strong advantages of FPGA, make FPGA the main application platform for time-to-digital transformation.

Among many time-to-digital measurement technologies, the characteristics of time-to-digital conversion technology based on FPGA are mainly reflected in the special hardware structure of FPGA and the small delay of logic gates. For example, the time delay line method, delay locked loop (DLL) technology, etc., all use the delay of the device itself to measure the time interval. Its basic idea is to find a basic delay unit in the device, cascade the units in a certain way to form a delay chain structure, and let the time to be measured pass through the delay chain to achieve time interpolation. Finally, this time interval is represented by the number of basic delay units, thereby realizing the conversion from time to number.

SUMMARY OF THE INVENTION

The purpose of the present invention is to solve the problems of low resolution, high system operating frequency and low performance of the existing clock phase splitting method, and provide a clock phase splitting method triggered by the edge of the phase-locked loop clock.

The clock phase splitting method of the phase-locked loop clock edge-triggered according to the present invention, the specific process is as follows:

Step 1. Input the clock signal 100MHz to the input end of the phase-locked loop;

Step 2. Multiply the clock signal from 100MHz to 315MHz, perform eight phase shifts on the high-level segment of the input clock, and set the phase shift angles CLK[0] to CLK[7] to 0°, 22.5°, and 45° respectively. , 66.5°, 90°, 112.5°, 135°, 157.5°;

Step 3. Use the edges of the eight-channel clock signals after the phase-locked loop frequency multiplication and phase-shift as sixteen trigger signals;

Step 4. Perform clock synchronization processing on the signal under test;

Step 5. Perform timing constraints on each transmission path of the clock signal and the signal under test respectively;

Step 6. Determine whether the measured signal levels Count[0]~Count[15] are 0 or 1 at the sixteen trigger moments, and 0→1 transition and 1→1 appear in Count[0]~Count[15] The position of 0 jump is extracted;

Step 7. Use event_up_reg[n] or event_down_reg[n] to record the rising edge/falling edge of the rising edge detection function event_up[n] of the measured signal or the falling edge detection function event_down[n] of the measured signal, when the rising edge of the measured signal When the detection function event_up[n] or the falling edge detection function event_down[n] of the signal under test has a rising edge, event_up_reg[n] or event_down_reg[n] outputs a high level, otherwise event_up_reg[n] or event_down_reg[n] outputs a low level ;

Step 8: Obtain the relative position of the rising edge or the falling edge of the signal under test within a clock cycle of 315MHz, and complete the clock phase splitting.

Advantages of the present invention: The clock phase splitting method of the phase-locked loop clock edge-triggered by the present invention can complete high-performance, high-resolution time interval measurement. Compared with the prior art, the time-measurement resolution is improved, and the The operating frequency of the system. First, use a simple binary counter to complete the "coarse" measurement part of the time interval, and the "fine" measurement part adopts the clock phase splitting method, only the high-level part of the clock (half a clock cycle) is phase-shifted eight times, and the original The resolution is increased by 16 times, and the resolution can be higher than 165ps. The equivalent measurement frequency of the present invention is 6080MHz (the input clock is 100MHz, and the frequency after frequency multiplication is 315MHz), and the resolution can be higher than 165ps. The traditional clock phase splitting method The whole clock cycle is averagely phase-shifted. The method proposed by the invention can improve the time measurement resolution, reduce the system operating frequency and achieve higher performance measurement effect under the premise of limited PLL taps.

Description of drawings

Figure 1 is a schematic diagram of the pulse counting method;

Fig. 2 is the principle diagram of interpolation timing method;

Fig. 3 is the overall structure diagram of the data acquisition part;

Fig. 4 is the schematic diagram of phase-locked loop frequency multiplication and phase-shifting;

5 is a schematic diagram of a data transmission path with a clock edge as a trigger signal;

6 is a schematic diagram of the overall output of clock phase-shift interpolation;

Figure 7 is the measured output waveform diagram of the "fine" measurement part.

Detailed ways

Embodiment 1: The clock phase division method of the phase-locked loop clock edge-triggered in this embodiment, the specific process is as follows:

Step 1. Input the clock signal 100MHz to the input end of the phase-locked loop;

Step 2. Multiply the clock signal from 100MHz to 315MHz, perform eight phase shifts on the high-level segment of the input clock, and set the phase shift angles CLK[0] to CLK[7] to 0°, 22.5°, and 45° respectively. , 66.5°, 90°, 112.5°, 135°, 157.5°;

Step 3. Use the edges of the eight-channel clock signals after the phase-locked loop frequency multiplication and phase-shift as sixteen trigger signals;

Step 4. Perform clock synchronization processing on the signal under test;

Step 5. Perform timing constraints on each transmission path of the clock signal and the signal under test respectively;

Step 6. Determine whether the measured signal levels Count[0]~Count[15] are 0 or 1 at the sixteen trigger moments, and 0→1 transition and 1→1 appear in Count[0]~Count[15] The position of 0 jump is extracted;

Step 7. Use event_up_reg[n] or event_down_reg[n] to record the rising edge/falling edge of the rising edge detection function event_up[n] of the measured signal or the falling edge detection function event_down[n] of the measured signal, when the rising edge of the measured signal When the detection function event_up[n] or the falling edge detection function event_down[n] of the signal under test has a rising edge, event_up_reg[n] or event_down_reg[n] outputs a high level, otherwise event_up_reg[n] or event_down_reg[n] outputs a low level ;

Step 8: Obtain the relative position of the rising edge or the falling edge of the signal under test within a clock cycle of 315MHz, and complete the clock phase splitting.

In this embodiment, the edge of the clock signal after frequency multiplication and phase shift is used as a trigger signal, and theoretically, the frequency after frequency multiplication can be further subdivided by 16 times, so as to reach a higher level. As shown in Figure 4, the PLL is a Phase Locked Loop, a phase-locked loop.

Embodiment 2: This embodiment further describes Embodiment 1. The edges of the eight-way clock signal in step 3 include the rising edge and the falling edge of the eight-way clock signal.

Embodiment 3: This embodiment further describes Embodiment 1. The method for extracting the positions where 0→1 transitions and 1→0 transitions occur in Count[0] to Count[15] described in step 5 are as follows:

Calculate Count[n] and Count[n+1]:

When event_up[n]=(～Count[n])&Count[n+1], it is the position of 0→1 transition;

When event_down[n]=(~Count[n+1])&Count[n], it is the position of 1→0 transition;

where n=0,1,...,15.

The invention proposes a precise time interval measurement method based on FPGA, which divides the time interval measurement into two parts: "coarse" measurement and "fine" measurement. It relies on the clock phase splitting method to perform time interpolation, so as to obtain higher time resolution.

The most basic method in the traditional time interval measurement technique is the pulse counting method. The pulse in the pulse counting method refers to the reference clock signal CLK_IN, and the reference clock signal is the time base for measuring time in the pulse counting method, so it is also called the time base signal. The event part of the measurement consists of a start signal (start signal) and a stop signal (stop signal). The measurement principle of the pulse counting method is based on the comparison of physical quantities of the same dimension. Fill the measured time interval with the time base signal, and quantify the measured time interval by counting the pulses of the time base signal. The specific working principle is shown in Figure _1. The start signal turns on the counter at time T1, and the stop count signal stops the counter at time T2. _The time interval ΔT between the start signal edge and the stop signal edge is measured by the counter whose clock is clk. count.

The time-to-digital conversion realized by this method is relatively simple in structure and logic. The resolution is determined by the clock period, the dynamic range of the measurement is determined by the number of bits of the counter, and the measurement accuracy is determined by the stability of the clock.

Since the resolution of the pulse counting method is very low, in order to improve the resolution of time measurement, the time interpolation method is used. Time interpolation is a time measurement technique that obtains high resolution on the basis of low resolution time base.

The measurement resolution of time interpolation is smaller than the time base period. As shown in Figure ₂ , the start signal turns _on the counter at time T1, the stop count signal stops the counter at time T2, and the time interval between the start signal edge and the stop signal edge ΔT is measured and counted by a counter whose clock is clk, where T _clk is the cycle of the reference clock signal CLK_IN, and n is the counter value. ΔT ₁ is the time interval between the rising edge of the measured event signal and the rising edge of the time base signal, ΔT ₂ is the time interval between the falling edge of the event signal and the rising edge of the time base signal, ΔT ₁ and ΔT ₂ are Time-interpolated measurement objects. The tiny time intervals ΔT ₁ and ΔT ₂ which are smaller than the time base period can be further quantified by time interpolation.

The lower part of Fig. 2 is an enlarged schematic view of ΔT ₁ and ΔT ₂ , and the arrows represent the scale for further quantification. Since the time base signal period is a known fixed value, the same interpolation effect can be achieved for two different measurement objects. The time interpolation method adopted in the present invention is the clock phase splitting method.

Clock phase splitting technology refers to the use of multiple phases of the clock cycle to achieve higher time resolution, and is widely used in high-speed digital system design. In some measurement environments, after meeting a certain measurement accuracy, considering the system construction, resource consumption, measurement cycle and other factors, it is a good choice to use the clock phase splitting technology to implement FPGA-based TDC.

Figure 3 is the overall structure diagram of the data acquisition part, and the key part is the middle FPGA-based TDC method. In this method, the rising edge of the input signal is the time signal to be measured, the coarse time measurement is constructed by using the synchronous parallel counter method, the resolution is the period of the system clock CLK_sys, and the coarse time measurement unit is used for multiple channels. The fine time measurement unit includes a multiphase clock-based time interpolation time sampling unit, a data buffer unit and an encoding unit.

The model of the chip used in the present invention is EP4SGX230KF40C2 of the Stratix IV series, and a multi-phase clock circuit is realized by using an internally integrated group phase-locked loop (PLL), thereby obtaining a higher time measurement resolution. The dedicated global clock network (GCLK), local clock network (RCLK), and peripheral clock network (PCLK) in Stratix IV devices form a hierarchical clock architecture that provides up to 236 single clock domains (16GCLKs). +88RCLK+132PCLK) and supports up to 71 single GCLK, RCLK and PCLK clock sources (16GCLK+22RCLK+33PCLK) in each device quadrant. Table 1 lists the clocking resources available in StratixIV devices.

Table 1 Clock Resources in Stratix IV Devices

StratixIV devices provide up to 16 GCLKs that can drive functional blocks throughout the device (for example, adaptive logic modules (ALM), digital signal processing (DSP) blocks, TriMatrix memory blocks, and PLLs) with low skew clock resource. StratixIV device I/O elements (IOEs) and internal logic can drive GCLKs to create internally generated global clocks and other high fanout control signals, such as synchronous or asynchronous clear and clock enable signals.

The signal under test is selected to be transmitted through the global clock line, so that it reaches each acquisition point as close as possible to the same time, so as to realize the realization of clock split-phase interpolation.

As shown in Figure 5, it is the data transmission path with the clock edge as the trigger signal. At the same time, the TimeQuest Timing Analyzer is used to analyze the delay time of each measurement path, and the TimeQuest Timing Analyzer is used to impose timing constraints on the special transmission path, so that the adjacent data transmission paths The delay times are as equal as possible.

Divide the "fine" measurement part into two parts, the rising edge and the falling edge of the signal under test, and carry out timing constraints respectively. According to the previous measurement results, select the appropriate delay time to carry out timing constraints on each path respectively.

Use LogicLock to logically lock the modules with timing constraints in the Chip Planner, so that subsequent programming can inherit the previously constrained path delays as much as possible.

After completing the realization of the "fine" measurement part, it is also necessary to integrate the "coarse" measurement part and the "fine" measurement part, as shown in Figure 6.

Load the program into the DE4 development board (the model of the chip is EP4SGX230KF40C2 of the Stratix IV series), and use the function generator Agilent 33220A to generate the measured signal (square wave with a frequency of 120MHz), and use the Signal Tap to observe the "fine" measurement part. Measure the output waveform and check the resolution it can achieve, as shown in Figure 7.

In the actual measurement part of the experimental data, 5 groups of different time intervals were taken for measurement, each group measured 20 data, and the 5 groups of time intervals were preset as 100ns, 200ns, 500ns, 1000ns and 1500ns.

According to the experimental measurement results, the resolution is about 165ps. The time interval is preset to 100ns and the minimum error value is 211ps (relative to the measurement result of the oscilloscope); the minimum error value of the time interval preset to 200ns is 274ps (relative to the measurement result of the oscilloscope); the time interval is preset to the minimum value of 500ns The error value is 310ps (relative to the measurement result of the oscilloscope); the minimum error value of the time interval preset to 1000ns is 257ps (relative to the measurement result of the oscilloscope); the minimum error value of the time interval preset to 1500ns is 312ps (relative to the oscilloscope measurement result) measurement results).

With a clock input of 100MHz, the equivalent timing frequency is 6080MHz, which effectively improves the timing resolution.

Claims (2)

1. The phase-locked loop clock edge triggered clock phase splitting method is characterized by comprising the following specific processes:

step 1, inputting a clock signal of 100MHz to an input end of a phase-locked loop;

step 2, frequency doubling the clock signal 100MHz to 315MHz, carrying out eight phase shifts on the high level section of the input clock, and setting the phase shift angles CLK [0] to CLK [7] as 0 degree, 22.5 degrees, 45 degrees, 66.5 degrees, 90 degrees, 112.5 degrees, 135 degrees and 157.5 degrees respectively;

step 3, taking the edges of the eight paths of clock signals after the frequency multiplication and phase shift of the phase-locked loop as sixteen trigger signals;

step 4, performing clock synchronization processing on the detected signal;

step 5, respectively carrying out time sequence constraint on each transmission path of the clock signal and the signal to be tested;

step 6, judging whether the measured signal levels Count [0] to Count [15] at sixteen trigger moments are 0 or 1, and extracting the positions of 0 → 1 jump and 1 → 0 jump in the Count [0] to Count [15 ];

step 7, recording the rising edge and the falling edge of the detected signal rising edge detection function event _ up [ n ] by using event _ up _ reg [ n ], recording the rising edge and the falling edge of the detected signal falling edge detection function event _ down [ n ] by using event _ down _ reg [ n ],

when the rising edge detection function event _ up [ n ] of the detected signal has a rising edge, the event _ up _ reg [ n ] outputs a high level,

when the falling edge detection function event _ down [ n ] of the detected signal has a rising edge, the event _ down _ reg [ n ] outputs a high level,

when the rising edge detection function event _ up [ n ] of the detected signal has a falling edge, the event _ up _ reg [ n ] outputs a low level,

when the falling edge detection function event _ down [ n ] of the detected signal has a falling edge, the event _ down _ reg [ n ] outputs a low level;

wherein n is 0,1, …, 15;

and 8, acquiring the relative position of the rising edge or the falling edge of the detected signal in 315MHz of a clock cycle, and completing clock phase splitting.

2. The phase-locked loop clock edge-triggered clock splitting method as claimed in claim 1, wherein the edges of the eight clock signals in step 3 comprise rising edges and falling edges of the eight clock signals.

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