CN108652661A - The FPGA medical ultrasonic imaging systems accelerated using CAPI - Google Patents
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Abstract
The present invention provides the FPGA medical ultrasonic imaging systems for using CAPI to accelerate.The system of the present invention uses the FPGA accelerated using CAPI to realize medical ultrasound image, and imaging algorithm itself is made that corresponding adaptation for the structure of FPGA and improves, its calculation process is set to be suitable for the execution of logic gates, to improve the imaging frame rate of medical ultrasound image.Compared with traditional medical ultrasonic imaging system executed based on computer, the present invention has high computation capability using the FPGA medical ultrasonic imaging systems that CAPI accelerates, the complicated calculations of high definition medical ultrasonic image algorithm can be completed within the extremely short time, can medical ultrasonic image be presented to real-time and high definition.The FPGA that the present invention used accelerated based on CAPI calculates core and directly can freely be used in SuperVessel platforms, at low cost, highly practical.
Description
Technical field
The invention belongs to medical ultrasound image fields, and in particular to the FPGA medical ultrasound images system accelerated using CAPI
System.
Background technology
In medical ultrasonic imaging system, physics array element emits ultrasonic wave and receives echo-signal, then in arithmetic element
In echo signal data be converted to by image data by imaging algorithm and show.Traditional medical ultrasound image imaging system
The core calculations of system are usually realized on central processor CPU, but the fortune of the huge imaging data of high definition imaging algorithm and complexity
Calculation process so that traditional CPU can no longer meet its demand to high-performance high concurrent operation.
The frequency of CPU is continuously improved in recent years, core cpu number is continuously increased on single-chip, double-core, four cores occurs very
To eight cores, but there are bottlenecks for the development of multi-core CPU, and core frequency and operation throughput are difficult to have further breakthrough carry
It is high.There is scholar to propose to integrate more arithmetic elements to improve the computing capability of unit interval, but this can cause equipment volume and
The increase of power consumption, while cost being made to improve.On the other hand, the development of current field programmable gate circuit engineering (FPGA) is fast
Suddenly, hundreds of customization arithmetic core can be integrated in one piece of fpga chip, so that its computation capability is substantially improved, this is
Realize that real-time high-definition medical imaging provides good hardware condition.In addition the CAPI coffrets proposed by IBM, solve
The slower problem of data transmission bauds, has further cleared away and has used FPGA as medical ultrasonic between fpga chip and traditional PC machine
The technical bottleneck of image core computing module.The present invention take full advantage of CAPI coffrets data transmission capabilities and FPGA it is strong
Big computation capability realizes complicated high definition medical imaging algorithm in fpga chip, completes and is accelerated based on CAPI
FPGA medical ultrasonic imaging systems structure.
The calculating core used in ultrasound medical imaging equipment at present is the central processing unit in common computer mostly, should
It realizes simply, the primary demand of medical ultrasound image can be met, but image frame per second is low, separate unit imaging device is of high cost.
Invention content
The main object of the present invention is to solve the problems, such as that current medical ultrasound image device rate is slow of high cost, provides use
The FPGA medical ultrasonic imaging systems that CAPI accelerates, to realize the medical ultrasonic imaging system of the high frame per second of low cost, having used makes
The SuperVessel cloud platforms accelerated with CAPIFPGA have fully excavated fpga chip high concurrent operational capability and have realized that delay is folded
The realization for adding beamforming algorithm has reached the requirement of the high frame per second of low cost in medical ultrasonic imaging system.
The purpose of the present invention is achieved through the following technical solutions.
The FPGA medical ultrasonic imaging systems accelerated using CAPI use the fpga chip based on CAPI transmission technologys real
The core calculations process of existing medical ultrasound image, and ultrasonic imaging delay stack algorithm itself is made that for the structure of FPGA
Corresponding adaptation and improve, its calculation process made to be suitable for the execution of logic gates, to improve medical ultrasound image at
Image-to-frame ratio.
The use of the CAPI FPGA medical ultrasonic imaging systems accelerated include data simulation module, core calculation module and display
Image module；The ultrasound emulation data that data simulation module is obtained using Field II, by network transmission to cloud host, passing through
It crosses after CAPI interfaces are transferred to fpga chip, core calculation module executes parallel delay stack beamforming algorithm, calculates
To image data, return by network transmission, by showing that image module is shown.
Further, the data simulation module simulates the propagation of ultrasonic wave in ultrasonic imaging using Field II emulators
Process simultaneously obtains emulation data；Correspondence is simulated according to real supersonic imaging apparatus corresponding configuration first in data simulation module
Emulated physics data, create transmitting and receive array element, analog detection object is created, then according to scan line analog transmissions one by one
And receive echo data.
Further, core calculation module is the fpga chip based on CAPI transmission technologys, realizes and prolongs in fpga chip
Superposition beamforming algorithm late, with the delay stack beamforming algorithm inputoutput data having the same calculated based on CPU
Stream and the processing of identical delay stack.
Further, display image module carries out Xi Er after core calculation module obtains pixel data to pixel data
Bert variation, log-compressed, tonal range correction and the operations such as picture depth and width calculating, it is finally that image related data is defeated
Go out into corresponding coordinate system, be imaged in screen display, or will be in image storage to file.
Further, core calculation module includes input data separator, line number cycle generator, postpones signal selection
Device, superimposer and data output controller；
Input data separator：For detaching 256 input datas of CAPI buses, and plan that input data is read
The sequence taken；
Line number recycles generator：When the required all input signal datas of a certain row pixel calculating have been read in image
Bi Shi, line number recycle the value that generator will start generation line number cyclic variable j, and the initial value of variable j is 0, in each clock
From increasing 1 in period, until maximum value 1023；
Postpones signal selector：Postpones signal selector will calculate the retardation on corresponding pixel points different data channel,
And select corresponding input signal data；Postpones signal selector contains a retardation calculator and a BRAM storage
Device, bram memory are used to store the input signal data that some data input receiving channel receives；
Superimposer：64 postpones signal selectors are shared in the CAPI designs of parallel delays superposition algorithm, and this 64
The sum of the output valve of postpones signal selector, the brightness value (image (i, j)) of pixel as at changing coordinates (i, j)；It calculates
The sum of two postpones signal selector output valves need an adder, accordingly, calculate 64 postpones signal selector outputs
The sum of value needs 63 adders；In order to enable adder designs pipeline, adder is divided into 6 stages by superimposer module
Level, every layer uses 32,16,8,4,2,1 adders respectively；
Output data controller：The data of output can be deposited in first in bram memory, and every 8 clock cycle pass through
CAPI bus interface exports a data to CPU.
Further, input data separator reads data by following step：
The first step：Within the T clock period, the 0th to the 7th postpones signal selector reads a CAPI input signal number
According to；At (T+1) in the clock cycle, the 8th to the 15th postpones signal selector reads next CAPI input signal datas；With
It is secondary to analogize, until within the T+7 clock cycle, the 56th to the 63rd postpones signal selector reads next CAPI input signals
Data；
Second step：Step described in the first step is repeated, until a certain row pixel in the image of generation is required
All input signal data readings finish；
Third walks：When all pixels point of a certain row in image calculates completion, then returns to the first step and read and generate image
The middle required input signal data process of next column pixel.
It further carries out, core calculation module is realized in the fpga chip accelerated based on CAPI.The pseudocode of lower section
For the core code of serial delay superposition algorithm in medical ultrasound image.In the algorithm, it is super that the echo received is calculated first
The retardation of acoustical signal, and then the echo signal after delay is superimposed to the echo signal output enhanced, i.e. ultrasonic imaging figure
The brightness value of a pixel as in.
The input data of algorithm is three-dimensional array ultrasonic echo data signal, and it is super for ith to define signal (i, k, d)
Sound emission, k-th of value for receiving d-th of signal that array element receives；The output data of algorithm is two dimensional image image, definition
Image (i, j) is the brightness value of the pixel of the i-th row jth row in image.
It is that algorithmic procedure describes below：
1. setting variable i as the cyclic variable of columns, initial value 0 is set；
2. setting variable j as the cyclic variable of line number, initial value 0 is set；
3. setting variable k as the cyclic variable of array number, initial value 0 is set；
4. according to variable i, j, the time of k computing relays and corresponding array index d；
5. executing superposition, variable i mage (i, j) superposed signal signal (i, k, d)；
6. from variable k is increased, if the value of variable k is less than total array number, step 3 is jumped to；
7. from variable j is increased, if the value of variable j is less than total line number, step 2 is jumped to；
8. from variable i is increased, if the value of variable i is less than total columns, step 1 is jumped to；
9. algorithm terminates, image image is returned.
Delay stack algorithm includes three cycles, as shown in the algorithm description of top.The time complexity of the algorithm is：
Complexity=O (LC × RC × RA),
Wherein variables L C (Line Count) indicates picturewide vertical in output image, variable R C (Rows Count)
Indicate that the line number in output image, variable PA (Probe Amount) indicate the probe array element quantity of reception of echoes ultrasonic signal.
Serial delay is superimposed in the core code of beamforming algorithm, and core operation is folded to input data after delay
Add.For a specific pixel (i, j) in the image that ultimately generates, there are the superpositions of PA input data signal, fold
The formula added is as follows：
Wherein, i, j and k are the accumulated variables of LC, RC and PA respectively, but the numerical value of retardation, can pass through specific i, j
It is obtained with the correlation computations of k variables.When variable i is a particular value ifixedWhen, i-th in final imagefixedPixel on row
Brightness value can be calculated by following formula：
By analyzing delay stack algorithm, the image (i calculated on different images line are obtainedfixed, j) when not
There are mutual data dependences.Therefore, the calculating process of delay stack algorithm can be realized with parallelization.It is real in fpga chip
Existing above-mentioned parallel delays are superimposed beamforming algorithm, and dispose and the FPGA cloud masters based on CAPI acceleration on SuperVessel
In machine.
By the corresponding ultrasonic echo data of network transmission in cloud host, and execute corresponding calling code, FPGA cores
Piece unfolding calculation.The data being calculated are sent back by network, by showing that image module is shown.
The present invention is according to existing scientific and technical present situation, with the SuperVessel clouds accelerated using CAPI FPGA
A real-time high-definition medical ultrasonic imaging system is realized on platform.The core meter of medical ultrasound image is realized on fpga chip
Calculation process, and ultrasonic imaging delay stack algorithm itself is made that corresponding adaptation for the structure of FPGA and improves, fully
The realization that fpga chip high concurrent operational capability realizes delay stack beamforming algorithm has been excavated, medical ultrasound image has been reached
The requirement of the high frame per second of low cost in system.
Compared with prior art, of the invention to be mainly reflected in two aspects a little：On the one hand, emphasis of the present invention realizes
Delay stack beamforming algorithm on fpga chip based on CAPI delivery accelerations takes full advantage of FPGA low-power consumption high concurrents
The characteristics of, imaging calculating speed has great promotion compared to traditional medical ultrasonic imaging system based on central processing unit；
On the other hand, the fpga chip based on CAPI delivery accelerations is used in free SuperVessel cloud platforms, by calculating process
In independence to cloud, equipment cost is further decreased, reduces the volume of medical ultrasound image equipment.
Description of the drawings
Fig. 1 is the FPGA medical ultrasonic imaging system workflow schematic diagrams accelerated using CAPI.
Fig. 2 is that parallel delays are superimposed beamforming algorithm realization module map in fpga chip.
Fig. 3 is CAPI FPGA and Host host structure charts in SuperVessel cloud platforms.
Fig. 4 is to export image instance figure using the FPGA medical ultrasonic imaging systems that CAPI accelerates.
Specific implementation mode
The specific implementation of the present invention is described further below in conjunction with attached drawing and example, but the implementation and protection of the present invention
It is without being limited thereto.It is that those skilled in the art can refer to existing skill if place is not described in detail especially it is noted that once having
What art was realized.
Fig. 1 is the workflow schematic diagram of this example.As seen from Figure 1, the FPGA medical ultrasonics accelerated using CAPI
Imaging system design has following module.
1. data simulation module
The communication process of ultrasonic wave in ultrasonic imaging is simulated using Field II emulators and obtains emulation data；In data
Simulate corresponding emulated physics data in emulation module according to real supersonic imaging apparatus corresponding configuration first, create transmitting and
Array element is received, analog detection object is created, then analog transmissions and receives echo data one by one according to scan line.
2. core calculation module
The overall structure of core calculation module is as shown in Fig. 2, the module includes five major parts：Input data detaches
Device, line number cycle generator, postpones signal selector, superimposer and data output controller.It is that this five parts are designed below
The detailed description of principle and implementation pattern：
Input data separator：For detaching 256 input datas of CAPI buses, and plan that input data is read
The sequence taken；
Line number recycles generator：When the required all input signal datas of a certain row pixel calculating have been read in image
Bi Shi, line number recycle the value that generator will start generation line number cyclic variable j, and the initial value of variable j is 0, in each clock
From increasing 1 in period, until maximum value 1023；
Postpones signal selector：Postpones signal selector will calculate the retardation on corresponding pixel points different data channel,
And select corresponding input signal data；Postpones signal selector contains a retardation calculator and a BRAM storage
Device, bram memory are used to store the input signal data that some data input receiving channel receives；
Superimposer：64 postpones signal selectors are shared in the CAPI designs of parallel delays superposition algorithm, and this 64
The sum of the output valve of postpones signal selector, the brightness value (image (i, j)) of pixel as at changing coordinates (i, j)；It calculates
The sum of two postpones signal selector output valves need an adder, accordingly, calculate 64 postpones signal selector outputs
The sum of value needs 63 adders；In order to enable adder designs pipeline, adder is divided into 6 stages by superimposer module
Level, every layer uses 32,16,8,4,2,1 adders respectively；
Output data controller：The data of output can be deposited in first in bram memory, and every 8 clock cycle pass through
CAPI bus interface exports a data to CPU.
3. showing image module
Image module is shown after core calculation module obtains pixel data, to pixel data carry out Hilbert variation,
Log-compressed, tonal range correction and the operations such as picture depth and width calculating, are finally output to correspondence by image related data
Coordinate system in, be imaged in screen display, or by image storage in file.
The system of this example is mainly realized in the FPGA cloud platforms accelerated based on CAPI that SuperVessel is provided, and is counted
According to the ultrasound emulation data that emulation module is obtained using Field II, by network transmission to cloud host, by CAPI interfaces
After being transferred to fpga chip, core calculation module executes parallel delay stack beamforming algorithm, and image data is calculated,
Return by network transmission, by showing that image module is shown.
4. operating procedure
In SuperVessel platforms, the overall structure using the CAPI FPGA cloud hosts accelerated is as shown in Figure 3.
Carry out accelerating algorithm application using CAPI FPGA accelerators on SuperVessel platforms, needs to execute following steps：
1. using XilinxVivado Software for Design FPGA accelerator nucleus modules；
2. integrating FPGA accelerators nucleus module on local x86 machines and CAPI simulation frames carrying out simulating, verifying；
3. compiling the accelerator packet that FPGA accelerators nucleus module and CAPI accelerate frame to constitute on the local machine, and raw
At corresponding bitstream files；
4. accelerator bitstream files are uploaded in SuperVessel cloud platforms；
5. applying for resources of virtual machine in SuperVessel cloud platforms, and it is associated with corresponding accelerator bitstream texts
Then part starts virtual machine and runs accelerator.
In instances, the input signal data of 10 parts of medical ultrasonic images SuperVessel clouds are loaded by network to put down
Platform, wherein the input signal data of every part of image corresponds to a ultrasonoscopy.Framework is accelerated to carry by CAPI in cloud platform
The API of confession, calls FPGA accelerators, BRAM data being transferred to from the corresponding DDR memories of CPU in cloud platform in FPGA
In；It completes to pass data back DDR memories again after image pixel point value calculates.Actual measurement is since data transmission to data transmission knot
The time of beam obtains the total time of parallel delays superposition algorithm cloud computing application operation.Parallel delays superposition algorithm is on FPGA
Calculating time clock cycle for being executed by statistic algorithm determine, therefore, can also extrapolate that data transmission consumed when
Between.The average value that every time parameter is acquired by many experiments, obtained experimental result are：Data transmission period 10.9ms,
Time 0.3ms is calculated, it is total to execute time 11.2ms.At the same time, it is calculated and is obtained together using CPU in SuperVessel cloud platforms
10 medical ultrasonic images of sample, what every image calculated averagely takes as 246ms.Thus it can be calculated, design herein
The speed-up ratio that CAPIFPGA parallel delays superposition algorithms are realized has reached about 22 times.
The image generated in above-mentioned experiment is as shown in Figure 4.It is 4 circular objects of simulation on the left of Fig. 4, is logical on the right side of Fig. 4
Cross the image that medical ultrasonic imaging system is calculated.
This example describes in SuperVessel cloud platforms, and design and evaluation and test are based on CAPI FPGA accelerator arts
Parallel delays superposition algorithm.Experiment evaluation result is shown based on the FPGA accelerated using CAPI in SuperVessel cloud platforms
The speed of service of medical ultrasonic imaging system improves about 22 compared to the speed of service of delay stack algorithm for using CPU to calculate
Times, it calculates frame per second theoretical value and has reached that 89 frames are per second, which meets the demand of the high frame per second of low cost.
Claims (8)
1. the FPGA medical ultrasonic imaging systems accelerated using CAPI, it is characterised in that including data simulation module, core calculations
Module and display image module；The ultrasound emulation data that data simulation module is obtained using Field II, are arrived by network transmission
In cloud host, after CAPI interfaces are transferred to fpga chip, core calculation module executes parallel delay stack Wave beam forming
Image data is calculated in algorithm, returns by network transmission, by showing that image module is shown.
2. the FPGA medical ultrasonic imaging systems according to claim 1 accelerated using CAPI, it is characterised in that the number
The communication process of ultrasonic wave in ultrasonic imaging is simulated using Field II emulators and obtain emulation data according to emulation module；In number
According to corresponding emulated physics data are simulated in emulation module according to real supersonic imaging apparatus corresponding configuration first, transmitting is created
With receive array element, create analog detection object, then analog transmissions and receive echo data one by one according to scan line.
3. the FPGA medical ultrasonic imaging systems according to claim 1 accelerated using CAPI, it is characterised in that core meter
Calculation module is the fpga chip based on CAPI transmission technologys, delay stack beamforming algorithm is realized in fpga chip, with base
The delay stack beamforming algorithm input/output date flow having the same calculated in CPU and the processing of identical delay stack.
4. the FPGA medical ultrasonic imaging systems according to claim 1 accelerated using CAPI, it is characterised in that display figure
As module is after core calculation module obtains pixel data, Hilbert variation, log-compressed, gray scale model are carried out to pixel data
The operations such as correction and picture depth and width calculating are enclosed, finally image related data is output in corresponding coordinate system, is being shielded
Curtain display imaging, or will be in image storage to file.
5. the FPGA medical ultrasonic imaging systems according to claim 1 accelerated using CAPI, it is characterised in that core meter
It includes input data separator, line number cycle generator, postpones signal selector, superimposer and data output control to calculate module
Device；
Input data separator：For detaching 256 input datas of CAPI buses, and plan what input data was read
Sequentially；
Line number recycles generator：When the required all input signal data readings of a certain row pixel calculating finish in image
When, line number recycles the value that generator will start generation line number cyclic variable j, and the initial value of variable j is 0, in each clock week
From increasing 1 in phase, until maximum value 1023；
Postpones signal selector：Postpones signal selector will calculate the retardation on corresponding pixel points different data channel, and select
Select corresponding input signal data；Postpones signal selector contains a retardation calculator and a bram memory,
Bram memory is used to store the input signal data that some data input receiving channel receives；
Superimposer：64 postpones signal selectors are shared in the CAPI designs of parallel delays superposition algorithm, and this 64 postpone
The sum of output valve of signal selector, the brightness value (image (i, j)) of pixel as at changing coordinates (i, j)；Calculate two
The sum of postpones signal selector output valve needs an adder, accordingly, calculate 64 postpones signal selector output valves it
With 63 adders of needs；In order to enable adder designs pipeline, adder is divided into 6 phase layers by superimposer module
Secondary, every layer uses 32,16,8,4,2,1 adders respectively；
Output data controller：The data of output can be deposited in first in bram memory, and every 8 clock cycle are total by CAPI
Line interface exports a data to CPU.
6. the FPGA medical ultrasonic imaging systems according to claim 5 accelerated using CAPI, it is characterised in that input number
Data are read by following step according to separator：
The first step：Within the T clock period, the 0th to the 7th postpones signal selector reads a CAPI input signal data；
At (T+1) in the clock cycle, the 8th to the 15th postpones signal selector reads next CAPI input signal datas；With secondary
Analogize, until within the T+7 clock cycle, the 56th to the 63rd postpones signal selector reads next CAPI input signals number
According to；
Second step：Step described in the first step is repeated, until a certain row pixel in the image of generation is required all
Input signal data reading finishes；
Third walks：When all pixels point of a certain row in image calculates completion, then return under the first step reads and generate in image
The required input signal data process of one row pixel.
7. the FPGA medical ultrasonic imaging systems according to claim 6 accelerated using CAPI, it is characterised in that core meter
Module is calculated to realize in the fpga chip accelerated based on CAPI；It executes in parallel delay stack beamforming algorithm, counts first
The retardation of the echo ultrasonic signal received, and then it is defeated that the echo signal after delay is superimposed to the echo signal enhanced
Go out, i.e., the brightness value of a pixel in ultrasonic imaging image；
The input data of algorithm is three-dimensional array ultrasonic echo data signal, defines signal (i, k, d) and is sent out for ith ultrasound
It penetrates, k-th of value for receiving d-th of signal that array element receives；The output data of algorithm is two dimensional image image, defines image
(i, j) is the brightness value of the pixel of the i-th row jth row in image；
It is the process of algorithm below：
(1) variable i is set as the cyclic variable of columns, sets initial value 0；
(2) variable j is set as the cyclic variable of line number, sets initial value 0；
(3) variable k is set as the cyclic variable of array number, sets initial value 0；
(4) according to variable i, j, the time of k computing relays and corresponding array index d；
(5) superposition, variable i mage (i, j) superposed signal signal (i, k, d) are executed；
(6) from variable k is increased, if the value of variable k is less than total array number, step (3) is jumped to；
(7) from variable j is increased, if the value of variable j is less than total line number, step (2) is jumped to；
(8) from variable i is increased, if the value of variable i is less than total columns, step (1) is jumped to；
(9) algorithm terminates, and returns to image image；
Delay stack algorithm includes three cycles, as shown in the algorithm description of top；The time complexity of the algorithm is：
Complexity=O (LC × RC × RA),
Wherein variables L C (Line Count) indicates that picturewide vertical in output image, variable R C (Rows Count) indicate
The line number in image is exported, variable PA (Probe Amount) indicates the probe array element quantity of reception of echoes ultrasonic signal.
8. the FPGA medical ultrasonic imaging systems according to claim 7 accelerated using CAPI, it is characterised in that delay is folded
The calculating process of computation system can be realized with parallelization, realize that parallel delays are superimposed beamforming algorithm, and portion in fpga chip
Administration in the upper FPGA cloud hosts based on CAPI acceleration of SuperVessel.
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| WO2019196394A1 (en) * | 2018-04-10 | 2019-10-17 | 华南理工大学 | Medical ultrasonic imaging system using fpga accelerated by capi |
| CN112075955A (en) * | 2019-06-14 | 2020-12-15 | 法国爱科森有限公司 | Method and device for measuring ultrasonic parameters of viscoelastic medium |
| US11850098B2 (en) | 2019-06-14 | 2023-12-26 | Echosens | Method and device for measuring an ultrasound parameter of a viscoelastic medium |
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| CN109947682A (en) * | 2019-03-21 | 2019-06-28 | 浪潮商用机器有限公司 | A kind of server master board and server |
| CN112075955A (en) * | 2019-06-14 | 2020-12-15 | 法国爱科森有限公司 | Method and device for measuring ultrasonic parameters of viscoelastic medium |
| US11850098B2 (en) | 2019-06-14 | 2023-12-26 | Echosens | Method and device for measuring an ultrasound parameter of a viscoelastic medium |
| CN112075955B (en) * | 2019-06-14 | 2024-03-19 | 法国爱科森有限公司 | Method and device for measuring ultrasonic parameters of viscoelastic medium |
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