CN108564926B - Drive circuit and display device - Google Patents
Drive circuit and display device Download PDFInfo
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- CN108564926B CN108564926B CN201810008700.3A CN201810008700A CN108564926B CN 108564926 B CN108564926 B CN 108564926B CN 201810008700 A CN201810008700 A CN 201810008700A CN 108564926 B CN108564926 B CN 108564926B
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2320/00—Control of display operating conditions
- G09G2320/06—Adjustment of display parameters
- G09G2320/068—Adjustment of display parameters for control of viewing angle adjustment
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Abstract
The invention provides a driving circuit which comprises a voltage output circuit, a first data selector and a second data selector, wherein the voltage output circuit is connected with the first data selector and the second data selector. The voltage output circuit outputs a first selection voltage, a second selection voltage, and a third selection voltage. The first data selector receives the first control signal and outputs a first common voltage, and the second data selector receives the second control signal and outputs a second common voltage. The invention also provides a display panel. According to the driving circuit and the display device provided by the invention, the first data selector outputs the first common voltage through the first control signal, and the second data selector outputs the second common voltage through the second control signal, so that the voltage required by a wide visual angle or a narrow visual angle is provided for the display panel, the driving and the switching of the wide visual angle are realized, better contrast can be obtained, and the display image quality is better.
Description
Technical Field
The invention relates to the technical field of liquid crystal display, in particular to a driving circuit and a display device.
Background
A Liquid Crystal Display (LCD) has advantages of good picture quality, small size, light weight, low driving voltage, low power consumption, no radiation, and relatively low manufacturing cost, and is dominant in the field of flat panel displays. The liquid crystal display device includes opposing color filter substrates (CF) and a thin film transistor array substrate (TFTarray) and a liquid crystal layer (LC layer) interposed therebetween.
Liquid crystal display devices are now gradually developed toward wide viewing angles, and wide viewing angles can be realized by using liquid crystal display devices of an in-plane switching mode (IPS) or a fringe field switching mode (FFS). However, in the current society, people pay more and more attention to protecting their privacy, and do not like to take out and share with people. In public places, the content is always expected to be kept secret when the user watches a mobile phone or browses a computer. Therefore, the display with single viewing angle mode has not been able to satisfy the user's requirement. In addition to the requirement of a wide viewing angle, there is also a need to be able to switch or adjust the display device to a narrow viewing angle mode where privacy is required. However, the contrast of the existing wide and narrow viewing angle display screen is poor under the narrow viewing angle, and the display of the image quality is directly influenced.
Disclosure of Invention
In view of the above, the present invention is directed to a driving circuit and a display device, which can realize driving and switching of wide and narrow viewing angles, obtain better contrast, and improve display quality.
The invention provides a driving circuit which comprises a voltage output circuit, a first data selector and a second data selector. The voltage output circuit is used for outputting a first selection voltage, a second selection voltage and a third selection voltage, wherein the first selection voltage is a direct current common voltage, the second selection voltage is greater than the first selection voltage, and the third selection voltage is less than the first selection voltage. The first data selector selects one of a first selection voltage, a second selection voltage and a third selection voltage as a first common voltage according to a first control signal and outputs the first common voltage to the display panel, wherein the first control signal comprises an enable signal, a shutdown signal, a viewing angle control signal and a first timing signal. The second data selector selects one of a first selection voltage, a second selection voltage and a third selection voltage as a second common voltage to be output to the display panel according to a second control signal, the second control signal comprises the enable signal, the shutdown signal, the view angle control signal and a second time sequence signal, and the second time sequence signal and the first time sequence signal are two signals with equal amplitude and opposite phase.
When the driving circuit is used for driving the display panel displaying a wide viewing angle, the first common voltage and the second common voltage are both first selection voltages; when the driving circuit is used for driving the display panel displaying a narrow viewing angle, the first common voltage is the second selection voltage and the second common voltage is the third selection voltage when displaying an nth frame image, and the first common voltage is the third selection voltage and the second common voltage is the second selection voltage when displaying an (n + 1) th frame image.
In one embodiment of the invention, the voltage output circuit comprises a first resistor and a second resistor. The first end of the first resistor receives a reference high voltage, and the second end of the first resistor outputs the second selection voltage. And the first end of the second resistor is connected with the second end of the first resistor, and the second end of the second resistor is grounded.
In one embodiment of the invention, the voltage output circuit comprises a third resistor and a fourth resistor. The first end of the third resistor receives a half-working voltage, and the second end of the third resistor outputs the third selection voltage. The first end of the fourth resistor is connected with the second end of the third resistor, and the second end of the fourth resistor receives a reference low voltage.
In one embodiment of the present invention, the voltage output circuit includes a first voltage follower, a second voltage follower, and a third voltage follower, wherein a first input terminal of the first voltage follower receives a first selection voltage, a non-inverting input terminal of the first voltage follower receives a dc common voltage, an inverting input terminal of the first voltage follower is connected to an output terminal of the first voltage follower, and an output terminal of the first voltage follower outputs the first selection voltage; the positive phase input end of the second voltage follower is connected with the first end of the second resistor, the negative phase input end of the second voltage follower is connected with the output end of the second voltage follower, and the output end of the second voltage follower outputs a second selection voltage; the positive phase input end of the third voltage follower is connected with the first end of the fourth resistor, the negative phase input end of the third voltage follower is connected with the output end of the third voltage follower, and the output end of the third voltage follower outputs a third selection voltage.
In one embodiment of the present invention, the first timing signal is a square wave signal.
In one embodiment of the present invention, when the enable signal is at a low level, the first data selector stops outputting the first common voltage, and the second data selector stops outputting the second common voltage.
In an embodiment of the invention, when the enable signal is at a high level and the shutdown signal or the view angle control signal is at a low level, the first common voltage and the second common voltage are both the first selection voltage.
In an embodiment of the invention, when the enable signal, the shutdown signal, and the view angle control signal are all at a high level, the first common voltage is the second selection voltage if the first timing signal is at a high level, the first common voltage is the third selection voltage if the first timing signal is at a low level, the second common voltage is the second selection voltage if the second timing signal is at a high level, and the second common voltage is the third selection voltage if the second timing signal is at a low level.
The invention further provides a display device, which comprises the driving circuit and a display panel, wherein the driving circuit provides a first common voltage line for outputting the first common voltage and a second common voltage line for outputting the second common voltage, a pixel unit on the display panel is connected with a source data line and is connected with the first common voltage line or the second common voltage line, and when one frame of image is displayed, the voltage polarity on the source data line connected with the pixel unit is the same as the voltage polarity on the first common voltage line or the second common voltage line connected with the pixel unit.
In an embodiment of the present invention, m source data lines are sequentially arranged on the display panel, the pixel unit connected to the 1 st source data line is connected to the first common voltage line, the pixel unit connected to the 2 nd and 3 rd source data lines is connected to the second common voltage line, the pixel unit connected to the 4 th and 5 th source data lines is connected to the first common voltage line, the pixel unit connected to the 6 th and 7 th source data lines is connected to the second common voltage line, and so on.
According to the driving circuit and the display device provided by the invention, the first data selector outputs the first common voltage through the first control signal, and the second data selector outputs the second common voltage through the second control signal, so that the voltage required by a wide viewing angle or a narrow viewing angle is provided for the display panel, the driving and switching of the wide and narrow viewing angles are realized, better contrast can be obtained, and the display image quality is better.
Drawings
Fig. 1 is a circuit connection diagram of a driving circuit according to an embodiment of the invention.
Fig. 2 is a schematic diagram of an output of a first data selector of a driving circuit according to an embodiment of the invention.
Fig. 3 is a schematic diagram of an output of a second data selector of the driving circuit according to an embodiment of the invention.
Fig. 4 is a schematic connection diagram of a display device according to an embodiment of the invention.
FIG. 5 is a timing diagram illustrating voltages received by a pixel unit in a wide viewing angle mode according to an embodiment of the invention.
FIG. 6 is a timing diagram illustrating voltages received by a pixel unit in a narrow viewing angle mode according to an embodiment of the invention.
Detailed Description
To further illustrate the technical means and effects of the present invention for achieving the intended purpose, the following detailed description is given to specific embodiments, methods, steps, structures, features and effects of the driving circuit for switching between wide and narrow viewing angles according to the present invention with reference to the accompanying drawings and preferred embodiments.
The foregoing and other aspects, features and advantages of the invention will be apparent from the following more particular description of preferred embodiments, as illustrated in the accompanying drawings. While the present invention has been described in terms of embodiments with a view to achieving the intended purpose and with a view to achieving a more complete and detailed understanding of the invention, reference is now made to the drawings, which are for purposes of illustration and description, and are not intended to limit the invention.
Fig. 1 is a circuit connection diagram of a driving circuit according to an embodiment of the invention. The driving circuit of the present embodiment includes a voltage output circuit 100, a first data selector 200, and a second data selector 300. The voltage output circuit 100 is configured to output a first selection voltage DCV1, a second selection voltage DCV2, and a third selection voltage DCV3, wherein the first selection voltage DCV1 is a dc common voltage DCVCOM, the second selection voltage DCV2 is greater than the first selection voltage DCV1, and the third selection voltage DCV3 is less than the first selection voltage DCV 1. The first data selector 200 is connected to the voltage output circuit 100, and the first data selector 200 selects one of the first selection voltage DCV1, the second selection voltage DCV2, and the third selection voltage DCV3 as a first common voltage AC1 to output to the display panel 400 according to a first control signal including an enable signal EN, a shutdown signal XON, a viewing angle control signal HVA, and a first timing signal V1. The second data selector 300 is connected to the voltage output circuit 100, the second data selector 300 selects one of the first selection voltage DCV1, the second selection voltage DCV2 and the third selection voltage DCV3 as the second common voltage AC2 to be output to the display panel 400 according to a second control signal, which includes an enable signal EN, a shutdown signal XON, a viewing angle control signal HVA and a second timing signal V2, wherein the second timing signal V2 and the first timing signal V1 are two signals with equal amplitude and opposite phase.
Wherein, when the driving circuit is used for driving the display panel 400 displaying a wide viewing angle, the first common voltage AC1 and the second common voltage AC2 are both the first selection voltage DCV 1; when the driving circuit is used to drive the display panel 400 displaying a narrow viewing angle, the first common voltage AC1 is the second selection voltage DCV2 and the second common voltage AC2 is the third selection voltage DCV3 when an nth frame image is displayed, and the first common voltage AC1 is the third selection voltage DCV3 and the second common voltage AC2 is the second selection voltage DCV2 when an n +1 th frame image is displayed.
In one embodiment of the present invention, the voltage output circuit 100 includes a first resistor R1 and a second resistor R2. The first terminal of the first resistor R1 may receive, but is not limited to, the reference high voltage VGH, and the second terminal of the first resistor R1 outputs the second selection voltage DCV 2. The first terminal of the second resistor R2 is connected to the second terminal of the first resistor R1, and the second terminal of the second resistor R2 may be, but is not limited to, ground. The first resistor R1, the second resistor R2, the reference high voltage VGH, and the ground terminal form a resistor voltage divider circuit, and the obtained second selection voltage DCV2 can be greater than the first selection voltage DCV1, that is, greater than the dc common voltage DCVCOM, by setting the resistance values of the first resistor R1 and the second resistor R2.
In one embodiment of the present invention, the voltage output circuit 100 includes a third resistor R3 and a fourth resistor R4. The first terminal of the third resistor R3 may receive, but is not limited to, a half-operating voltage HAVDD, and the second terminal of the third resistor R3 outputs a third selection voltage DCV 3. A first terminal of the fourth resistor R4 is connected to a second terminal of the third resistor R3, and a second terminal of the fourth resistor R4 may receive, but is not limited to, the reference low voltage VGL. The third resistor R3, the fourth resistor R4, the half-operating voltage HAVDD, and the reference low voltage VGL form a resistor divider circuit, and the third selection voltage DCV3 can be made smaller than the first selection voltage DCV1, that is, smaller than the dc common voltage DCVCOM, by setting the resistances of the third resistor R3 and the fourth resistor R4.
In one embodiment of the present invention, the voltage output circuit 100 includes a first voltage follower U1, a second voltage follower U2, and a third voltage follower U3, wherein a non-inverting input terminal of the first voltage follower U1 receives a dc common voltage DCVCOM, an inverting input terminal of the first voltage follower U1 is connected to an output terminal of the first voltage follower U1, and an output terminal of the first voltage follower U1 outputs a first selection voltage DCV 1. The non-inverting input terminal of the second voltage follower U2 is connected to the first terminal of the second resistor R2, the inverting input terminal of the second voltage follower U2 is connected to the output terminal of the second voltage follower U2, and the output terminal of the second voltage follower U2 outputs the second selection voltage DCV 2. A non-inverting input terminal of the third voltage follower U3 is connected to the first terminal of the fourth resistor R4, an inverting input terminal of the third voltage follower U3 is connected to the output terminal of the third voltage follower U3, and the output terminal of the third voltage follower U3 outputs the third selection voltage DCV 3. Specifically, the first voltage follower U1 to the third voltage follower U3 are all voltage followers, and the voltage followers are circuits with a gain equal to one, and output voltages of the voltage followers follow input voltages, so that output impedance of the voltage output circuit 100 is reduced, driving current is increased, driving capability is enhanced, anti-interference capability is increased, and reliability of the voltage output circuit 100 is improved.
The power supply voltages of the first voltage follower U1, the second voltage follower U2 and the third voltage follower U3 can be, but are not limited to, a reference high voltage VGH and a reference low voltage VGL.
In one embodiment of the present invention, the first timing signal V1 may be, but is not limited to, a square wave signal, for example, the first timing signal V1 may be a sine wave signal, a sawtooth wave signal, or the like. Since the second timing signal V2 and the first timing signal V1 are two signals with equal amplitude and opposite phase, when the first timing signal V1 is a square wave signal, the second timing signal V2 is a square wave signal with equal amplitude and opposite phase to the first timing signal V1.
In one embodiment of the present invention, the output of the first data selector 200 is shown in Table 1. In table 1, the first four columns are the enable signal EN, the shutdown signal XON, the view angle control signal HVA and the first timing signal V1 of the first control signal, respectively, where 0 represents a low level, 1 represents a high level, X represents a low level or a high level, and the last column is the first common voltage AC1 and its voltage value.
Table 1:
fig. 2 is a schematic diagram of an output of a first data selector 200 of a driving circuit according to an embodiment of the invention. Fig. 2 is a waveform diagram of table 1, but it does not limit the specific timing of the enable signal EN, the shutdown signal XON, the view angle control signal HVA and the first timing signal V1.
The output of the second data selector 300 is shown in table 2. In table 2, the first four columns are the enable signal EN, the shutdown signal XON, the view angle control signal HVA and the second timing signal V2 of the second control signal, respectively, where 0 represents a low level, 1 represents a high level, X represents a low level or a high level, and the last column is the second common voltage AC2 and its voltage value.
Table 2:
fig. 3 is a diagram illustrating an output of a second data selector 300 of a driving circuit according to an embodiment of the present invention. Fig. 3 is a waveform diagram of table 2, but it does not limit the specific timing of the enable signal EN, the shutdown signal XON, the view angle control signal HVA and the second timing signal V2.
In this embodiment, when the enable signal EN is low, the first data selector 200 stops outputting the first common voltage AC1, and the second data selector 300 stops outputting the second common voltage AC 2.
In this embodiment, when the enable signal EN is at a high level and the shutdown signal XON is at a low level, the first common voltage AC1 and the second common voltage AC2 are both the first selection voltage DCV1, that is, the voltage value is the dc common voltage DCVCOM, which can be used to release the charges of the pixel unit when all the TFT switches connected to the gate of the display device are turned on.
In this embodiment, when the enable signal EN, the shutdown signal XON are at a high level, and the view angle control signal HVA is at a low level, the first common voltage AC1 and the second common voltage AC2 are both the first selection voltage DCV1, i.e. the voltage value is the dc common voltage DCVCOM. When the display panel 400 displaying a wide viewing angle is driven, the driving circuit of the present embodiment provides the first selection voltage DCV1 and the second selection voltage DCV2, and makes the first common voltage AC1 and the second common voltage AC2 form a larger liquid crystal voltage VLC with the voltage on the source data line of the display device.
In this embodiment, when the enable signal EN, the shutdown signal XON, and the view angle control signal HVA are all high, the first common voltage AC1 is determined by the first timing signal V1, specifically, when the first timing signal V1 is high, the first common voltage AC1 may be, but is not limited to, the second selection voltage DCV2, and when the first timing signal V1 is low, the first common voltage AC1 may be, but is not limited to, the third selection voltage DCV 3; the second common voltage AC2 is determined by the second timing signal V2, and specifically, the second common voltage AC2 can be, but is not limited to, the second selection voltage DCV2 when the second timing signal V2 is high, and the second common voltage AC2 can be, but is not limited to, the third selection voltage DCV3 when the second timing signal V2 is low. When the display panel 400 displaying a narrow viewing angle is driven, the driving circuit of the present embodiment provides the first selection voltage DCV1 and the second selection voltage DCV2, and makes the first common voltage AC1 and the second common voltage AC2 form a smaller liquid crystal voltage VLC with the voltage on the source data line of the display device.
The driving circuit of the present embodiment enables the first data selector 200 to output the first common voltage AC1 through the first control signal, and enables the second data selector 300 to output the second common voltage AC2 through the second control signal, so as to provide the display panel 400 with the voltage required by the wide viewing angle or the narrow viewing angle, thereby implementing the driving and switching of the wide and narrow viewing angles.
Fig. 4 is a schematic connection diagram of a display device according to an embodiment of the invention. An embodiment of the present invention provides a display device, which includes the driving circuit and the display panel 400 of the above-mentioned embodiment, the driving circuit provides a first common voltage line 410 outputting a first common voltage AC1 and a second common voltage line 420 outputting a second common voltage AC2, the display panel 400 includes a plurality of pixel units arranged horizontally and vertically, a column of the pixel units is connected to a same source data line and is connected to the same first common voltage line 410 or the second common voltage line 420, and when displaying a frame image, a voltage polarity on the source data line connected to the pixel units is the same as a voltage polarity on the connected first common voltage line 410 or the connected second common voltage line 420.
In an embodiment of the present invention, m source data lines are sequentially arranged on the display panel 400, a pixel cell connected to the 1 st source data line D1 is connected to the first common voltage line 410, a pixel cell connected to the 2 nd source data line D2 and the 3 rd source data line D3 is connected to the second common voltage line 420, a pixel cell connected to the 4 th source data line D4 and the 5 th source data line D5 is connected to the first common voltage line 410, a pixel cell connected to the 6 th source data line D6 and the 7 th source data line D7 is connected to the second common voltage line 420, and so on.
FIG. 5 is a timing diagram of voltages received by the pixel unit in the wide viewing angle mode according to the embodiment of the invention corresponding to FIG. 4. It can be seen that when the display panel 400 displaying a wide viewing angle is driven, the first and second common voltages AC1 and AC2 are the first selection voltage DCV1, i.e., the dc common voltage DCVCOM, and a large liquid crystal voltage VLC is formed between the first common voltage AC1 and the voltage D1 on the source data line of the display device, and between the second common voltage AC2 and the voltages D2 and D3 on the source data line of the display device.
FIG. 6 is a timing diagram illustrating voltages received by a pixel unit in a narrow viewing angle mode according to an embodiment of the invention corresponding to FIG. 4. It can be seen that when the display panel 400 displaying a narrow viewing angle is driven, the first common voltage AC1 is always in phase with the voltage on the 1 st source data line and is simultaneously inverted when displaying the next frame image, and the second common voltage AC2 is always in phase with the voltages on the 2 nd and 3 rd source data lines and is simultaneously inverted when displaying the next frame image. Further, the liquid crystal voltage VLC formed between the first common voltage AC1 and the voltage D1 on the source data line of the display device, and between the second common voltage AC2 and the voltages D2, D3 on the source data line of the display device is small.
The display device of the present embodiment may be, but is not limited to, a normally black mode. When the display panel 400 displaying a wide viewing angle is driven, the user may set the viewing angle control signal HVA of the driving circuit to a low level, and the first and second common voltages AC1 and AC2 outputted through the first and second data selectors 200 and 300 are the first selection voltage DCV1, i.e., the dc common voltage DCVCOM, so that the voltages on the first and second common voltages AC1 and AC2 and the source data line of the display device may form a larger liquid crystal voltage VLC, such that when the display panel 400 displaying a wide viewing angle is driven, the picture of the display device is a white picture and the viewing angle is large.
In driving the display panel 400 displaying a narrow viewing angle, the user may set the viewing angle control signal HVA of the driving circuit to a high level, output the first and second common voltages AC1 and AC2 through the first and second data selectors 200 and 300, respectively, and the first common voltage AC1 determines to output the second or third selection voltages DCV2 and DCV3 from the first timing signal V1 and the second common voltage AC2 determines to output the second or third selection voltages DCV2 and DCV3 from the second timing signal V2. In order to drive the display panel 400 displaying a narrow viewing angle, the voltage on the source data line connected to one pixel cell is identical in polarity to the voltage on the first common voltage line 410 or the second common voltage line 420 connected to the pixel cell, specifically, m source data lines are sequentially arranged on the display panel 400, the first common voltage AC1 is always in phase with the voltage on the 1 st source data line and is simultaneously inverted when displaying the next frame image, the second common voltage AC2 is always in phase with the voltages on the 2 nd and 3 rd source data lines and is simultaneously inverted when displaying the next frame image, similarly, the first common voltage AC1 is always in phase with the voltages on the 4 th and 5 th source data lines and is simultaneously inverted when displaying the next frame image, the second common voltage AC2 is always in phase with the voltages on the 6 th and 7 th source data lines, and when displaying the next frame of image, the inversion is carried out at the same time, and the connection of the m source electrode data lines is finished by analogy in turn.
Compared with the narrow viewing angle technical solution in the prior art, the liquid crystal voltage VLC in the prior art is the difference between the dc common voltage DCVCOM and the voltage on the source data line, and when the liquid crystal voltage VLC in the embodiment displays a frame image, the difference between the first common voltage AC1 or the second common voltage AC2 connected to the pixel unit and the voltage on the source data line can be seen in fig. 6.
According to the driving circuit and the display device provided by the invention, the first data selector 200 outputs the first common voltage AC1 through the first control signal, and the second data selector 300 outputs the second common voltage AC2 through the second control signal, so that the voltage required by a wide viewing angle or a narrow viewing angle is provided for the display panel 400, the driving and the switching of the wide viewing angle and the narrow viewing angle are realized, better contrast can be obtained, and the display image quality is better.
Although the present invention has been described with reference to the preferred embodiments, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (10)
1. A driver circuit, comprising:
a voltage output circuit (100), the voltage output circuit (100) for outputting a first selection voltage (DCV1), a second selection voltage (DCV2), and a third selection voltage (DCV3), the first selection voltage (DCV1) being a DC Common Voltage (DCVCOM), the second selection voltage (DCV2) being greater than the first selection voltage (DCV1), the third selection voltage (DCV3) being less than the first selection voltage (DCV 1);
a first data selector (200), the first data selector (200) selecting one of a first selection voltage (DCV1), a second selection voltage (DCV2), and a third selection voltage (DCV3) to be output as a first common voltage (AC1) to the display panel (400) according to a first control signal, the first control signal including an enable signal (EN), a shutdown signal (XON), a viewing angle control signal (HVA), and a first timing signal (V1);
a second data selector (300), the second data selector (300) selecting one of a first selection voltage (DCV1), a second selection voltage (DCV2) and a third selection voltage (DCV3) to be output as a second common voltage (AC2) to the display panel (400) according to a second control signal, the second control signal including the enable signal (EN), the shutdown signal (XON), the view angle control signal (HVA) and a second timing signal (V2), wherein the second timing signal (V2) and the first timing signal (V1) are two signals of equal amplitude and opposite phase;
wherein the first common voltage (AC1) and the second common voltage (AC2) are both a first selection voltage (DCV1) when a driving circuit is used to drive the display panel (400) displaying a wide viewing angle; when a driving circuit is used to drive the display panel (400) displaying a narrow viewing angle, the first common voltage (AC1) is the second selection voltage (DCV2) and the second common voltage (AC2) is the third selection voltage (DCV3) when an nth frame image is displayed, and the first common voltage (AC1) is the third selection voltage (DCV3) and the second common voltage (AC2) is the second selection voltage (DCV2) when an n +1 th frame image is displayed.
2. The drive circuit of claim 1, wherein the voltage output circuit (100) comprises a first resistor (R1), a second resistor (R2);
a first terminal of the first resistor (R1) receives a reference high Voltage (VGH), and a second terminal of the first resistor (R1) outputs the second selection voltage (DCV 2);
the first end of the second resistor (R2) is connected with the second end of the first resistor (R1), and the second end of the second resistor (R2) is grounded.
3. The drive circuit of claim 2, wherein the voltage output circuit (100) comprises a third resistor (R3), a fourth resistor (R4);
a first terminal of the third resistor (R3) receives a half-operating voltage (HAVDD), and a second terminal of the third resistor (R3) outputs the third selection voltage (DCV 3);
a first terminal of the fourth resistor (R4) is connected to a second terminal of the third resistor (R3), and a second terminal of the fourth resistor (R4) receives a reference low Voltage (VGL).
4. The drive circuit according to claim 3, wherein the voltage output circuit (100) comprises a first voltage follower (U1), a second voltage follower (U2), a third voltage follower (U3), wherein;
a non-inverting input terminal of the first voltage follower (U1) receives a DC Common Voltage (DCVCOM), an inverting input terminal of the first voltage follower (U1) is connected to an output terminal of the first voltage follower (U1), and an output terminal of the first voltage follower (U1) outputs a first selection voltage (DCV 1);
a non-inverting input terminal of the second voltage follower (U2) is connected with a first terminal of a second resistor (R2), an inverting input terminal of the second voltage follower (U2) is connected with an output terminal of the second voltage follower (U2), and an output terminal of the second voltage follower (U2) outputs a second selection voltage (DCV 2);
the non-inverting input end of the third voltage follower (U3) is connected with the first end of a fourth resistor (R4), the inverting input end of the third voltage follower (U3) is connected with the output end of the third voltage follower (U3), and the output end of the third voltage follower (U3) outputs a third selection voltage (DCV 3).
5. The driver circuit according to claim 1, wherein the first timing signal (V1) is a square wave signal.
6. The driving circuit of claim 1, wherein the first data selector (200) stops outputting the first common voltage (AC1) and the second data selector (300) stops outputting the second common voltage (AC2) when the enable signal (EN) is low.
7. The driving circuit according to claim 6, wherein the first common voltage (AC1), the second common voltage (AC2) are the first selection voltage (DCV1) when the enable signal (EN) is high and the shutdown signal (XON) or the view angle control signal (HVA) is low.
8. The driving circuit as claimed in claim 7, wherein when the enable signal (EN), the shutdown signal (XON) and the view angle control signal (HVA) are all high, the first timing signal (V1) is high, the first common voltage (AC1) is the second selection voltage (DCV2), the first timing signal (V1) is low, the first common voltage (AC1) is the third selection voltage (DCV3), the second timing signal (V2) is high, the second common voltage (AC2) is the second selection voltage (DCV2), and the second timing signal (V2) is low, the second common voltage (AC2) is the third selection voltage (DCV 3).
9. A display device comprising a driving circuit according to any one of claims 1 to 8 and a display panel (400), wherein the driving circuit provides a first common voltage line (410) for outputting the first common voltage (AC1) and a second common voltage line (420) for outputting the second common voltage (AC2), each column of pixel cells on the display panel (400) is connected to a corresponding one of the source data lines and to the first common voltage line (410) or the second common voltage line (420), and when displaying one frame of image, the polarity of the voltage on the source data line to which the pixel cells are connected is the same as the polarity of the voltage on the first common voltage line (410) or the second common voltage line (420) to which the pixel cells are connected.
10. The display device according to claim 9, wherein m source data lines are sequentially arranged on the display panel (400), the pixel units connected to the 1 st source data line are connected to the first common voltage line (410), the pixel units connected to the 2 nd and 3 rd source data lines are connected to the second common voltage line (420), the pixel units connected to the 4 th and 5 th source data lines are connected to the first common voltage line (410), the pixel units connected to the 6 th and 7 th source data lines are connected to the second common voltage line (420), and so on.
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| CN110767193A (en) * | 2019-11-11 | 2020-02-07 | 昆山龙腾光电股份有限公司 | Alternating-current public voltage generating circuit and method and display device |
| CN111243537B (en) * | 2020-01-16 | 2022-03-01 | 昆山龙腾光电股份有限公司 | Common voltage generating circuit, method and display device |
| CN111429855B (en) * | 2020-04-03 | 2022-03-01 | 昆山龙腾光电股份有限公司 | Visual angle switching circuit and display device |
| TWI738417B (en) * | 2020-07-10 | 2021-09-01 | 友達光電股份有限公司 | Display device and driving method thereof |
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