CN108538780A - The manufacturing method of bit line/storage node contacts embolism and polysilicon contact film - Google Patents
The manufacturing method of bit line/storage node contacts embolism and polysilicon contact film Download PDFInfo
- Publication number
- CN108538780A CN108538780A CN201810347664.3A CN201810347664A CN108538780A CN 108538780 A CN108538780 A CN 108538780A CN 201810347664 A CN201810347664 A CN 201810347664A CN 108538780 A CN108538780 A CN 108538780A
- Authority
- CN
- China
- Prior art keywords
- substrate
- boiler tube
- deposition
- tube board
- storage node
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 208000005189 Embolism Diseases 0.000 title claims abstract description 36
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 35
- 238000003860 storage Methods 0.000 title claims description 77
- 229910021420 polycrystalline silicon Inorganic materials 0.000 title claims description 26
- 229920005591 polysilicon Polymers 0.000 title claims description 16
- 238000000151 deposition Methods 0.000 claims abstract description 139
- 230000008021 deposition Effects 0.000 claims abstract description 130
- 239000000758 substrate Substances 0.000 claims abstract description 123
- 230000001590 oxidative effect Effects 0.000 claims abstract description 62
- 238000000034 method Methods 0.000 claims abstract description 60
- 238000005530 etching Methods 0.000 claims abstract description 55
- 239000000126 substance Substances 0.000 claims abstract description 23
- 239000007792 gaseous phase Substances 0.000 claims abstract description 21
- 239000007789 gas Substances 0.000 claims description 57
- 239000000463 material Substances 0.000 claims description 24
- 238000004140 cleaning Methods 0.000 claims description 22
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 20
- 238000009413 insulation Methods 0.000 claims description 19
- 238000004518 low pressure chemical vapour deposition Methods 0.000 claims description 14
- 239000006227 byproduct Substances 0.000 claims description 12
- 229910052757 nitrogen Inorganic materials 0.000 claims description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 9
- 239000012495 reaction gas Substances 0.000 claims description 9
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 claims description 8
- 238000000231 atomic layer deposition Methods 0.000 claims description 8
- 238000002955 isolation Methods 0.000 claims description 8
- 229910000040 hydrogen fluoride Inorganic materials 0.000 claims description 7
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims description 7
- 229910052710 silicon Inorganic materials 0.000 claims description 7
- 239000010703 silicon Substances 0.000 claims description 7
- JOHWNGGYGAVMGU-UHFFFAOYSA-N trifluorochlorine Chemical compound FCl(F)F JOHWNGGYGAVMGU-UHFFFAOYSA-N 0.000 claims description 7
- 229920006395 saturated elastomer Polymers 0.000 claims description 6
- 238000006701 autoxidation reaction Methods 0.000 claims description 4
- 238000000059 patterning Methods 0.000 claims description 4
- 238000011065 in-situ storage Methods 0.000 claims description 2
- 239000004065 semiconductor Substances 0.000 description 7
- QKCGXXHCELUCKW-UHFFFAOYSA-N n-[4-[4-(dinaphthalen-2-ylamino)phenyl]phenyl]-n-naphthalen-2-ylnaphthalen-2-amine Chemical compound C1=CC=CC2=CC(N(C=3C=CC(=CC=3)C=3C=CC(=CC=3)N(C=3C=C4C=CC=CC4=CC=3)C=3C=C4C=CC=CC4=CC=3)C3=CC4=CC=CC=C4C=C3)=CC=C21 QKCGXXHCELUCKW-UHFFFAOYSA-N 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 4
- 239000007769 metal material Substances 0.000 description 4
- 230000003647 oxidation Effects 0.000 description 4
- 238000007254 oxidation reaction Methods 0.000 description 4
- 206010021143 Hypoxia Diseases 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 3
- 238000006243 chemical reaction Methods 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 229910021419 crystalline silicon Inorganic materials 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 230000007954 hypoxia Effects 0.000 description 3
- 239000011810 insulating material Substances 0.000 description 3
- 239000001301 oxygen Substances 0.000 description 3
- 229910052760 oxygen Inorganic materials 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- 230000007704 transition Effects 0.000 description 3
- 238000001312 dry etching Methods 0.000 description 2
- 239000012528 membrane Substances 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 239000002245 particle Substances 0.000 description 2
- 239000012071 phase Substances 0.000 description 2
- 239000000047 product Substances 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 238000012512 characterization method Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000002425 crystallisation Methods 0.000 description 1
- 230000008025 crystallization Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000003344 environmental pollutant Substances 0.000 description 1
- 239000000945 filler Substances 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 231100000719 pollutant Toxicity 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The present invention at least provides a kind of manufacturing method of bit line contact embolism, including:A substrate is provided, substrate has bit line contact hole in a insulating layer;It will be placed in a deposition boiler tube board with the substrate in bit line contact hole, and be formed in the natural oxidizing layer of bit line contact hole bottom by the removal of chemical gaseous phase lithographic method, wherein natural oxidizing layer is formed in substrate in the waiting process before entering deposition boiler tube board;Depositing bitlines contact film above substrate in deposition boiler tube board, so that bit line contact film is filled in bit line contact hole and cover insulating layer;And etching bit line contact film, until exposing insulating layer, to form bit line contact embolism, which can reduce contact resistance, improve electrical property.
Description
Technical field
The present invention relates to a kind of semiconductor applications more particularly to bit line contact embolism, storage node contacts embolism and polycrystalline
Silicon contacts the manufacturing method of film.
Background technology
In the manufacturing process of DRAM (Dynamic Random Access Memory, dynamic random access memory) device
In, deposit polycrystalline silicon (polysilicon, abbreviation poly) is needed to form the conductive knot of bit line contact (Bit line contact)
Structure and storage node contacts (Storage node contact) conductive structure.With the size micro of integrated circuit, to poly
Contact resistance requirement it is higher and higher.
In the stand-by period before entering boiler tube board deposition poly, the exposed section of front layer poly or silicon substrate is due to oxidation
Natural oxidizing layer can be formed, natural oxidizing layer can influence contact resistance, reduce bit line contact conductive structure and storage node contacts
The conductive capability of conductive structure.In the prior art, removing natural oxidizing layer is removed by way of wet-cleaning before poly depositions, but
This mode needs the stand-by period between stringent management and control Wet clean to poly depositions, and not only control is difficult, but also can make to connect
Resistance of getting an electric shock is fluctuated larger by stand-by period difference;Also a kind of mode is to be nitrogen (N in the stand-by period2) brush to reduce ring
Oxygen concentration in border, to alleviate the formation of natural oxidizing layer, but this mode needs to extend the stand-by period.
Invention content
The embodiment of the present invention provides the manufacturer of a kind of bit line contact embolism, storage node contacts embolism and semiconductor devices
Method, to solve or alleviate one or more technical problems in the prior art.
As the one side of the embodiment of the present invention, the embodiment of the present invention provides a kind of manufacturer of bit line contact embolism
Method, including:
A substrate is provided, the substrate has bit line contact hole in a insulating layer;
It will be placed in a deposition boiler tube board with the substrate in institute's bitline contact hole, and etched by chemical gaseous phase
Method removes the natural oxidizing layer for being formed in bitline contact bottom hole portion of institute, wherein the natural oxidizing layer is formed in the lining
Bottom is in the waiting process before entering the deposition boiler tube board;
Depositing bitlines contact film above the substrate in the deposition boiler tube board, make institute's bitline contact film
It is filled in institute's bitline contact hole and covers the insulating layer;And
Institute's bitline contact film is etched, until exposing the insulating layer, to form bit line contact embolism.
Preferably, the chemical gaseous phase lithographic method includes:
The pressure in the deposition boiler tube board is controlled in the range of 0.1 support to 100 support and the deposition boiler tube machine
Temperature in platform is in the range of 100 degrees Celsius to 625 degrees Celsius;
Be passed through etching gas to the deposition boiler tube board, the etching gas be selected from by hydrogen fluoride, chlorine trifluoride and
One of the group that Nitrogen trifluoride is constituted;
The etching gas is maintained at the predetermined time in the deposition boiler tube board so that the etching gas with it is described
Natural oxidizing layer is reacted;And
Nitrogen is vacuumized and injected to deposition boiler tube board cycle, makes remaining etching gas and the etching gas
The deposition boiler tube board is discharged in the byproduct of reaction gas of body and the natural oxidizing layer.
Preferably, the predetermined time is set according to the thickness of the natural oxidizing layer, so that the autoxidation
Layer is reacted completely.
Preferably, the step of one substrate of the offer includes:
Prepare the substrate;
Device isolation structure and buried gate are formed in the substrate;
Insulating layer is formed in the top of the substrate;
The insulating layer is etched, until exposing the substrate, to form institute's bitline contact hole in the insulating layer;
The substrate in cleaning tool bitline contact hole.
Preferably, the mode of the cleaning tool substrate in bitline contact hole includes wet-cleaning.
Preferably, the material of institute's bitline contact film is selected from polysilicon, and the deposition of institute's bitline contact film is logical
Low-pressure chemical vapor deposition mode, atomic layer deposition mode, atomic layer seed deposition combination low-pressure chemical vapor deposition is crossed to answer
A kind of in conjunction mode and plasma enhanced chemical vapor deposition mode carries out.
Preferably, the material of institute's bitline contact film is selected from original position P DOPOS doped polycrystalline silicons, institute's bitline contact film
Deposition step includes:
The pressure in the deposition boiler tube board is controlled in the range of 0.05 support to 4 support and the deposition boiler tube machine
Temperature in platform is in the range of 350 degrees Celsius to 625 degrees Celsius;And
Depositional mode to be saturated adatom layer seed deposits the original position P DOPOS doped polycrystalline silicons, wherein control doping P
A concentration of per cubic centimeter 1019A to per cubic centimeter 5 × 1021It is a.
As the other side of the embodiment of the present invention, the embodiment of the present invention provides a kind of system of storage node contacts embolism
Method is made, including:
A substrate is provided, the insulation system and the storage section in the insulation system that the substrate has covering bit line
Point contact slot;
It will be placed in a deposition boiler tube board with the substrate of the storage node contacts slot, and pass through chemical gaseous phase
Lithographic method removes removing natural oxidizing layer, wherein the natural oxidizing layer is formed in the substrate of the storage node contacts trench bottom
It goes up and is formed in the substrate in the waiting process before entering the deposition boiler tube board;
Storage node contacts film is deposited in the deposition boiler tube board above the substrate, makes the memory node
Contact film is filled in the storage node contacts slot and covers the insulation system;And
Patterning etches the storage node contacts film to form storage node contacts embolism.
Preferably, the chemical gaseous phase lithographic method includes:
The pressure in the deposition boiler tube board is controlled in the range of 0.1 support to 100 support and the deposition boiler tube machine
Temperature in platform is in the range of 100 degrees Celsius to 625 degrees Celsius;
Be passed through etching gas to the deposition boiler tube board, the etching gas be selected from by hydrogen fluoride, chlorine trifluoride and
One of the group that Nitrogen trifluoride is constituted;
The etching gas is maintained at the predetermined time in the deposition boiler tube board so that the etching gas with it is described
Natural oxidizing layer is reacted;And
Nitrogen is vacuumized and injected to deposition boiler tube board cycle, makes remaining etching gas and the etching gas
The deposition boiler tube board is discharged in the byproduct of reaction gas of body and the natural oxidizing layer.
Preferably, the predetermined time is set according to the thickness of the natural oxidizing layer, so that the autoxidation
Layer is reacted completely.
Preferably, the step of one substrate of the offer includes:
Prepare the substrate;
Bit line contact embolism and the bit line are formed on the substrate, the bit line covers institute's bitline contact embolism;
Form the insulation system;
The insulation system is etched, until exposing the substrate, to form the memory node in the insulation system
Contact groove;
Cleaning tool has the substrate of the storage node contacts slot.
Preferably, it includes wet-cleaning that cleaning tool, which has the mode of the substrate of the storage node contacts slot,.
Preferably, the material of the storage node contacts film is selected from polysilicon, the storage node contacts film
Deposition is by low-pressure chemical vapor deposition mode, atomic layer deposition mode, atomic layer seed deposition combination low pressure chemical phase
The complex method of deposition and a kind of in plasma enhanced chemical vapor deposition mode carry out.
Preferably, the material of the storage node contacts film is selected from original position P DOPOS doped polycrystalline silicons, and the memory node connects
Touch film deposition step include:
The pressure in the deposition boiler tube board is controlled in the range of 0.05 support to 4 support and the deposition boiler tube machine
Temperature in platform is in the range of 350 degrees Celsius to 625 degrees Celsius;And
Depositional mode to be saturated adatom layer seed deposits the original position P DOPOS doped polycrystalline silicons, wherein control doping P
A concentration of per cubic centimeter 1019A to per cubic centimeter 5 × 1021It is a.
As the other side of the embodiment of the present invention, the embodiment of the present invention also provides a kind of system of polysilicon contact film
Method is made, including:
Prepare substrate;
Clean the substrate;
The substrate is placed in a deposition boiler tube board, the natural oxygen of substrate surface is removed by chemical gaseous phase lithographic method
Change layer, wherein the natural oxidizing layer is formed in the substrate in the waiting process before entering the deposition boiler tube board;
Deposit polycrystalline silicon contacts film above the substrate in the deposition boiler tube board.
Preferably, described the step of removing the natural oxidizing layer by chemical gaseous phase lithographic method, includes:
The pressure in the deposition boiler tube board is controlled in the range of 0.1 support to 100 support and the deposition boiler tube machine
Temperature in platform is in the range of 100 degrees Celsius to 625 degrees Celsius;
Be passed through etching gas to the deposition boiler tube board, the etching gas be selected from by hydrogen fluoride, chlorine trifluoride and
One of the group that Nitrogen trifluoride is constituted;
The etching gas is maintained at the predetermined time in the deposition boiler tube board so that the etching gas with it is described
Natural oxidizing layer is reacted;And
Vacuumize and inject nitrogen to boiler tube board cycle, make remaining etching gas and the etching gas and
The boiler tube board is discharged in the byproduct of reaction gas of the natural oxidizing layer.
As the other side of the embodiment of the present invention, the embodiment of the present invention also provides a kind of storage node contacts embolism
Manufacturing method, including:
A substrate is provided, the substrate has bit line contact hole in a insulating layer;
It will be placed in a deposition boiler tube board with the substrate in institute's bitline contact hole, and etched by chemical gaseous phase
Method removes the first natural oxidizing layer for being formed in bitline contact bottom hole portion of institute, wherein first natural oxidizing layer is formed
In the substrate with institute's bitline contact hole in the waiting process before entering the deposition boiler tube board;
Depositing bitlines contact film above the substrate in the deposition boiler tube board, make institute's bitline contact film
It is filled in institute's bitline contact hole and covers the insulating layer;And
Institute's bitline contact film is etched, until exposing the insulating layer, to form bit line contact embolism.
The bit line of covering institute bitline contact embolism and the insulation system of the covering bit line are formed on the substrate
Side, and storage node contacts slot is formed in the insulating layer;
It will be placed in the deposition boiler tube board with the substrate of the storage node contacts slot, and pass through chemical gas
Phase lithographic method removes the second nature oxide layer, wherein the second nature oxide layer is formed in the storage node contacts slot
On the substrate of bottom and the substrate with the storage node contacts slot is formed in before entering the deposition boiler tube board
Waiting process in;
Storage node contacts film is deposited in the deposition boiler tube board above the substrate, makes the memory node
Contact film is filled in the storage node contacts slot and covers the insulating layer;And
Patterning etches the storage node contacts film to form storage node contacts embolism.The embodiment of the present invention uses
Above-mentioned technical proposal can reduce contact resistance, improve electrical property.
Above-mentioned general introduction is merely to illustrate that the purpose of book, it is not intended to be limited in any way.Except foregoing description
Schematical aspect, except embodiment and feature, by reference to attached drawing and the following detailed description, the present invention is further
Aspect, embodiment and feature, which will be, to be readily apparent that.
Description of the drawings
In the accompanying drawings, unless specified otherwise herein, otherwise run through the identical reference numeral of multiple attached drawings and indicate same or analogous
Component or element.What these attached drawings were not necessarily to scale.It should be understood that these attached drawings are depicted only according to the present invention
Some disclosed embodiments, and should not serve to limit the scope of the present invention.
Fig. 1 is the flow chart of the manufacturing method of the polysilicon membrane of embodiment one.
Fig. 2-1 to Fig. 2-3 is the manufacturing process schematic diagram of the polysilicon contact film of embodiment one.
Fig. 3-1 to Fig. 3-4 is the manufacturing process schematic diagram of the bit line contact film of embodiment two.
Fig. 4-1 to Fig. 4-4 is the manufacturing process schematic diagram of the storage node contacts film of embodiment three.
Reference sign:
10:Deposition boiler tube board; 20:Etching gas;
110:Substrate; 121:First natural oxidizing layer;
122:The second nature oxide layer; 140:Polysilicon contact film;
210:Substrate; 222:Third Nature oxide layer;
230:Storage node contacts film; 231:Storage node contacts embolism;
232:Storage node contacts slot;
240:Bit line contact film; 241:Bit line contact hole;
242:Bit line contact embolism; 243:Bit line;
251:Isolated groove; 252:Bed course;
253:Device isolation structure; 260:Buried gate;
261:Buried gate groove; 262:Grid oxic horizon;
263:Wordline; 270:Insulation system;
271:First insulating layer; 272:Second insulating layer;
273:Third insulating layer; 274:Third insulating layer;
275:5th insulating layer; 280:Dielectric layer;
290:Transition zone; 322:4th natural oxidizing layer;
S110~S140:Step.
Specific implementation mode
Hereinafter, certain exemplary embodiments are simply just described.As one skilled in the art will recognize that
Like that, without departing from the spirit or scope of the present invention, described embodiment can be changed by various different modes.
Therefore, attached drawing and description are considered essentially illustrative rather than restrictive.
In the description of the present invention, it is to be understood that, term "center", " longitudinal direction ", " transverse direction ", " length ", " width ",
" thickness ", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outside", " up time
The orientation or positional relationship of the instructions such as needle ", " counterclockwise ", " axial direction ", " radial direction ", " circumferential direction " be orientation based on ... shown in the drawings or
Position relationship is merely for convenience of description of the present invention and simplification of the description, and does not indicate or imply the indicated device or element must
There must be specific orientation, with specific azimuth configuration and operation, therefore be not considered as limiting the invention.
In addition, term " first ", " second " are used for description purposes only, it is not understood to indicate or imply relative importance
Or implicitly indicate the quantity of indicated technical characteristic.Define " first " as a result, the feature of " second " can be expressed or
Implicitly include one or more this feature.In the description of the present invention, the meaning of " plurality " is two or more,
Unless otherwise specifically defined.
In the present invention unless specifically defined or limited otherwise, fisrt feature the "upper" of second feature or "lower"
It may include that the first and second features are in direct contact, can also not be to be in direct contact but pass through it including the first and second features
Between other characterisation contact.Moreover, fisrt feature second feature " on ", " side " and " above " include fisrt feature
Right over second feature and oblique upper, or it is merely representative of fisrt feature level height and is higher than second feature.Fisrt feature is
Two features " under ", " lower section " and " following " include fisrt feature right over second feature and oblique upper, or be merely representative of
One characteristic level height is less than second feature.
Following disclosure provides many different embodiments or example is used for realizing the different structure of the present invention.In order to
Simplify disclosure of the invention, hereinafter the component of specific examples and setting are described.Certainly, they are merely examples, and
And it is not intended to limit the present invention.In addition, the present invention can in different examples repeat reference numerals and/or reference letter,
This repetition is for purposes of simplicity and clarity, itself not indicate between discussed various embodiments and/or setting
Relationship.
In the manufacturing process of semiconductor devices, different technique will carry out in board or reative cell or else together, partly lead
Body device needs to undergo the stand-by period before entering a certain board, since it is desired that semiconductor devices is carried to from a upper board
The process of the board is also easy to produce natural oxidizing layer in the stand-by period.The embodiment of the present invention is intended to provide a kind of semiconductor devices
Manufacturing method, the influence to avoid natural oxidizing layer to contact resistance improves semiconductor to realize good Ohmic contact
The electrical property of device.
Embodiment one
As shown in Figure 1, the present embodiment provides a kind of manufacturing method of polysilicon membrane, including step S110~step
S140。
Step S110, prepares substrate 110, and substrate 110 can be silicon (Si) or polysilicon.Due to the effect of autoxidation,
The first natural oxidizing layer 121 can be formed on 110 surface of substrate, as shown in Fig. 2-1.
Step S121 cleans substrate 110, can in cleaning machine with wet-cleaning (Wet clean, it is also referred to as wet
Method etch) mode remove the first oxide layer 121 and other pollutants, as shown in Fig. 2-2.
Enter in the waiting process before deposition boiler tube board 10 in substrate 110,110 surface of substrate can form the second nature oxygen
Change layer 122, as Figure 2-3, according to the difference of stand-by period, the thickness of the second nature oxide layer 122 is also different, and usually 3
AngstromIt arrives
Substrate 110 is placed in deposition boiler tube board 10 by step S122, certainly by chemical gaseous phase lithographic method removal second
Right oxide layer 122, as Figure 2-3.
In step 122, include by the step of chemical gaseous phase lithographic method removal the second nature oxide layer 122:Xiang Chen
Product boiler tube board 10 is passed through etching gas 20, which can select hydrogen fluoride (HF), can also select chlorine trifluoride
(ClF3) or Nitrogen trifluoride (NF3), HF, ClF can also be selected3And NF3Arbitrary combination;Etching gas 20 is maintained at deposition
Predetermined time in boiler tube board 10 so that etching gas 20 is chemically reacted with the second nature oxide layer 122, and generates reaction
Byproduct gas;Then, vacuumize and inject N to the cycle of deposition boiler tube board 102, make remaining etching gas 20 and reaction
Deposition boiler tube board 10 is discharged in byproduct gas.It should be noted that the setting of predetermined time can be according to the second nature oxide layer
122 thickness is set, and when the thickness of the second nature oxide layer 122 is larger, the longer predetermined time is needed, so that second
Natural oxidizing layer 122 can be etched, and gas 10 is complete to react, to completely remove the second nature oxide layer 122.
Further, during removing the second nature oxide layer 122, the pressure in deposition boiler tube board 10 should be controlled
It is 0.1 support (Torr) to 100Torr, and it is 100 degrees Celsius (DEG C) to 625 DEG C to control the temperature in deposition boiler tube board 10.
Step S140, deposit polycrystalline silicon contacts film 140 above substrate 110 in deposition boiler tube board 10, such as Fig. 2-3
It is shown.The material of polysilicon contact film 140 can select non-crystalline silicon (amorphous silicon), can also select crystallization
Silicon (crystallize silicon), the mode that deposit polycrystalline silicon contacts film 140 can be low-pressure chemical vapor deposition
(LPCVD) mode or atomic layer deposition (ALD) mode or atomic layer seed (Seed) deposition combine the complex method of LPCVD or wait
Gas ions enhance chemical vapor deposition (PECVD) mode.
That is, step S122 and step S140 is carried out in the same deposition boiler tube board 10, due to deposition boiler tube
It is in hypobaric hypoxia state in board 10, natural oxidizing layer will not be generated again after removal the second nature oxide layer 122, to avoid
Influence of the natural oxidizing layer to contact resistance so as to realize good Ohmic contact, and can reduce contact resistance, improve half
The electrical property of conductor device, the manufacturing method of the present embodiment can also reduce the control difficulty for generating technique, be conducive to improve generation
Efficiency.
Embodiment two
The present embodiment provides a kind of manufacturing methods of bit line contact embolism, please refer to Fig. 3-1 to Fig. 3-4, need to illustrate
It is that identical filling pattern shows same structure or same material in figure.
As shown in figure 3-1, substrate 210 is prepared, then forms device isolation structure 253 and flush type grid on substrate 210
Pole 260.The forming method of device isolation structure 253 may include first depositing bed course 252 on substrate 210, wherein bed course 252
Material can be oxide (OX);Next, utilizing shallow-trench isolation (Shallow Trench Isolation, STI) technique
Bed course 252 and substrate 210 are selectively etched, substrate 210 is made to be etched the isolated groove 251 for isolating device, then, profit
It is buried with chemical vapor deposition (Chemical Vapor Deposition, abbreviation CVD) technique or other depositing operation formation
Enter to the insulating materials in isolated groove 251 and to insulating materials execution CMP process until exposing bed course 252,
To form device isolation structure 253, it is used for isolating device, wherein insulating materials can be OX.The shape of buried gate 260
May include utilizing graphical photolithography method etched substrate 210 at method, to form buried gate groove 261;Then pass through
Oxidation technology forms grid oxic horizon 262 in the bottom of buried gate groove 261 and madial wall;Then it is partially filled with metal material
Expect that, in buried gate groove 261, to form wordline 263, the metal material for forming wordline 263 can be one or more metals
The mixture of material.
With continued reference to Fig. 3-1, next, form the first insulating layer 271 in the top of substrate 210, the first insulating layer 271
Material can be silicon nitride (SiN);Then, the first insulating layer 271 is etched by graphic method, until exposing substrate 210, from
And bit line contact hole 241 is formed in the first insulating layer 271.
Then, the cleaning method cleaning in embodiment one may be used in substrate 210 of the cleaning with bit line contact hole 241
Substrate 210.Next, substrate 210 is transported to deposition boiler tube board 10 from cleaning machine, enter deposition boiler tube in substrate 210
In waiting process before board 10, the bottom in bit line contact hole 241 is such as schemed because oxidation can form Third Nature oxide layer 222
Shown in 3-2.
Next by the substrate 210 in bit line contact hole 241 merging deposition boiler tube board 10, pass through chemical gaseous phase etching side
Method removes Third Nature oxide layer 222, and as shown in Fig. 3-3, the step of removing Third Nature oxide layer 222 is referred to embodiment
Step S122 in one, i.e., be passed through etching gas 20 to deposition boiler tube board 10;Etching gas 20 is maintained at deposition boiler tube machine
Predetermined time in platform 10 so that etching gas 20 is chemically reacted with Third Nature oxide layer 222, and generates byproduct of reaction
Gas;Then, vacuumize and inject N to the cycle of deposition boiler tube board 102, make remaining etching gas 20 and byproduct of reaction
Deposition boiler tube board 10 is discharged in gas.The setting of predetermined time can be set according to the thickness of Third Nature oxide layer 222, when
When the thickness of Third Nature oxide layer 222 is larger, the longer predetermined time is needed, so that Third Nature oxide layer 222 can be by
Etching gas 10 reacts completely, to completely remove Third Nature oxide layer 222.
Then, depositing bitlines contact film 240 above substrate 210 in deposition boiler tube board 10, keep bit line contact thin
240 filler wire contact hole 241 of film simultaneously covers the first insulating layer 271, as shown in Fig. 3-3.The material of bit line contact film 240 is excellent
Be selected as polysilicon, such as select non-crystalline silicon or silicon metal, the mode of depositing bitlines contact film 240 can be LPCVD or ALD or
Complex method or PECVD mode of the atomic layer Seed depositions in conjunction with LPCVD.
Preferably, in the present embodiment, the material of bit line contact film 240 is phosphorus in situ (P) DOPOS doped polycrystalline silicon, specifically
The deposition step on ground, bit line contact film 240 includes:It is 0.05Torr to 4Torr to control the pressure in deposition boiler tube board 10,
And it is 350 DEG C to 625 DEG C to control the temperature in deposition boiler tube board 10;And to be saturated the depositional mode of adatom layer seed
Deposit original position P doped polycrystalline silicon films, wherein a concentration of per cubic centimeter the 10 of control doping P particles19It is a to per cubic centimeter
5×1021It is a.
Next, as shown in Figure 3-4, bit line contact film 240 can be etched in a manner of dry etching (Dry etch), directly
To the first insulating layer 271 is exposed, to form bit line contact embolism 242, it is formed by the first insulating layer 271 covering bit line contact bolt
The side wall of plug 242.
In the present embodiment, the removal of Third Nature oxide layer 222 and bit line contact film 240 are deposited on the same deposition
It carries out in boiler tube board 10, due to being in hypobaric hypoxia state in deposition boiler tube board 10, going after removing natural oxidizing layer will not be again
Natural oxidizing layer is generated, to avoid influence of the natural oxidizing layer to contact resistance, so as to realize good Ohmic contact,
And bit line contact resistance can be reduced, the electrical property of bit line is improved, the manufacturing method of the present embodiment, which can also reduce, generates technique
Control difficulty is conducive to improve formation efficiency.
Embodiment three
The present embodiment provides a kind of manufacturing methods of storage node contacts embolism, and what can be formed based on embodiment two has position
It is carried out on the substrate 210 of line contact plug 242.It should be noted that Fig. 3-1 to Fig. 3-4 shows the front cross-sectional of substrate 210
Figure, next Fig. 4-1 to Fig. 4-4 show the side sectional view of substrate 210.
As shown in Fig. 4-1, continues the bit line 243 for forming covering bit line contact embolism 242 on substrate 210, form bit line
243 material can be the mixture of one or more metals, and the mode for forming bit line 243 can be first deposited metal material,
Then the metal material is graphically etched, to form bit line 243;Then, second insulating layer 272 is formed, to cover bit line 243
Top and side wall, the material of second insulating layer 272 can be the material identical with the first insulating layer 271.
Next, third insulating layer 273, the 4th insulating layer 274 and the 5th insulating layer 275 are formed, as shown in Fig. 4-1.Its
In, third insulating layer 273 covers the first insulating layer 271 and second insulating layer 272, the material of third insulating layer 273 and can select
Silicon oxynitride (SiON);4th insulating layer 274 covers third insulating layer 273, and the material of the 4th insulating layer 274 can select OX;
5th insulating layer 275 covers and surrounds the 4th insulating layer 274, third insulating layer 273 and the first insulating layer 271, the 5th insulation
The material of layer 275 can select material identical with the first insulating layer 271, such as select SiN.
Then, etching includes the first insulating layer 271, second insulating layer 272, third insulating layer 273, the 4th insulating layer 274
It is connect until exposing substrate 210 with forming memory node in insulation system 270 with the insulation system 270 of the 5th insulating layer 275
Slot 232 is touched, the bottom of storage node contacts slot 232 and substrate top surface are coplanar, as shown in Fig. 4-1.
Then, substrate 210 of the cleaning with storage node contacts slot 232, may be used the cleaning method in embodiment one
Clean the substrate 210 with storage node contacts slot 232.Next, by the substrate 210 with storage node contacts slot 232 from
Cleaning machine is transported to deposition boiler tube board 10, enters deposition boiler tube board in the substrate 210 with storage node contacts slot 232
In waiting process before 10, because oxidation can form the 4th natural oxidizing layer on the substrate 210 of 232 bottom of storage node contacts slot
322, as shown in the Fig. 4-2.
Next the substrate 210 with dielectric layer 280 is placed in deposition boiler tube board 10, passes through chemical gaseous phase etching side
Method removes removing natural oxidizing layer 322, and as shown in Fig. 4-3, the step of going to removing natural oxidizing layer 322 is referred to the step in embodiment one
Rapid S122 is passed through etching gas 20 to deposition boiler tube board 10;Etching gas 20 is maintained in deposition boiler tube board 10 pre-
It fixes time, so that etching gas 20 is chemically reacted with natural oxidizing layer 322, and generates byproduct of reaction gas;Then, right
The cycle of deposition boiler tube board 10 vacuumizes and injects N2, make remaining etching gas 20 and byproduct of reaction gas discharge deposition
Boiler tube board 10.It should be noted that the setting of predetermined time can be set according to the thickness of the 4th natural oxidizing layer 322,
When the thickness of the 4th natural oxidizing layer 322 is larger, the longer predetermined time is needed, so that the 4th natural oxidizing layer 322 can be with
The gas 10 that is etched reacts completely, to completely remove the 4th natural oxidizing layer 322.
Then, deposition storage node contacts film 230 makes storage save above substrate 210 in deposition boiler tube board 10
Point contact film 230 is filled in storage node contacts slot 232 and covers insulation system 270, as shown in Fig. 4-3.Memory node
The material of contact film 230 can select polysilicon, such as non-crystalline silicon or silicon metal, deposition storage node contacts film 230
Mode can be the complex method or PECVD modes of LPCVD or ALD or atomic layer Seed depositions in conjunction with LPCVD.
Preferably, in the present embodiment, the material of storage node contacts film 230 can be selected from original position P doped polycrystallines
Silicon, specifically, the deposition step of storage node contacts film 230 includes:Pressure in control deposition boiler tube board 10 is
0.05Torr is to 4Torr, and it is 350 DEG C to 625 DEG C to control the temperature in deposition boiler tube board 10;And to be saturated adatom
The depositional mode of layer seed deposits original position P DOPOS doped polycrystalline silicons, wherein a concentration of per cubic centimeter the 10 of control doping P particles19It is a
To per cubic centimeter 5 × 1021It is a.
Next, as shown in Fig. 4-4, storage node contacts can be graphically etched in a manner of dry etching (Dry etch)
Film 230, until exposing the 4th insulating layer 274 (falling the top etch of the 5th insulating layer 275) and substrate 210, with shape
At storage node contacts embolism 231;Then, transition zone 290 and medium are formed between adjacent storage node contacts embolism 231
Layer 280, wherein transition zone 290 surrounds side wall and the bottom of dielectric layer 280.
In the present embodiment, being deposited on for the removal of the 4th natural oxidizing layer 322 and storage node contacts film 230 is same
It carries out in deposition boiler tube board 10, due to being in hypobaric hypoxia state in deposition boiler tube board 10, goes after removing natural oxidizing layer not
Natural oxidizing layer can be generated again, to avoid influence of the natural oxidizing layer to contact resistance, so as to realize good ohm
Contact, and can reduce storage node contacts resistance, improve the electrical property of semiconductor devices, and the manufacturing method of the present embodiment can be with
The control difficulty for generating technique is reduced, is conducive to improve formation efficiency.
In above example, in the heavy of deposit polycrystalline silicon contact film (bit line contact film or storage node contacts film)
Chemical gaseous phase lithographic method, which is first carried out, in product boiler tube board removes the natural oxidizing layer, then deposit polycrystalline silicon contacts film, from
And influence of the natural oxidizing layer to contact resistance is avoided, it realizes good Ohmic contact, improves electrical property.
The above description is merely a specific embodiment, but scope of protection of the present invention is not limited thereto, any
Those familiar with the art in the technical scope disclosed by the present invention, can readily occur in its various change or replacement,
These should be covered by the protection scope of the present invention.Therefore, protection scope of the present invention should be with the guarantor of the claim
It protects subject to range.
Claims (17)
1. a kind of manufacturing method of bit line contact embolism, which is characterized in that including:
A substrate is provided, the substrate has bit line contact hole in a insulating layer;
It will be placed in a deposition boiler tube board with the substrate in institute's bitline contact hole, and pass through chemical gaseous phase lithographic method
Removal is formed in the natural oxidizing layer in bitline contact bottom hole portion of institute, wherein the natural oxidizing layer is formed in the substrate and exists
Into in the waiting process before the deposition boiler tube board;
Depositing bitlines contact film above the substrate in the deposition boiler tube board, and institute's bitline contact film is made to fill
In institute's bitline contact hole and cover the insulating layer;And
Institute's bitline contact film is etched, until exposing the insulating layer, to form bit line contact embolism.
2. manufacturing method according to claim 1, which is characterized in that the chemical gaseous phase lithographic method includes:
The pressure in the deposition boiler tube board is controlled in the range of 0.1 support to 100 support and in the deposition boiler tube board
Temperature in the range of 100 degrees Celsius to 625 degrees Celsius;
It is passed through etching gas to the deposition boiler tube board, the etching gas is selected from by hydrogen fluoride, chlorine trifluoride and trifluoro
Change one of the group that nitrogen is constituted;
The etching gas is maintained at the predetermined time in the deposition boiler tube board, so that the etching gas and the nature
Oxide layer is reacted;And
Vacuumize and inject nitrogen to deposition boiler tube board cycle, make remaining etching gas and the etching gas and
The deposition boiler tube board is discharged in the byproduct of reaction gas of the natural oxidizing layer.
3. manufacturing method according to claim 2, which is characterized in that the predetermined time is according to the natural oxidizing layer
Thickness is set, so that the natural oxidizing layer is reacted completely.
4. manufacturing method according to claim 1, which is characterized in that the step of one substrate of the offer includes:
Prepare the substrate;
Device isolation structure and buried gate are formed in the substrate;
Insulating layer is formed in the top of the substrate;
The insulating layer is etched, until exposing the substrate, to form institute's bitline contact hole in the insulating layer;
The substrate in cleaning tool bitline contact hole.
5. manufacturing method according to claim 4, which is characterized in that the substrate in cleaning tool bitline contact hole
Mode include wet-cleaning.
6. manufacturing method according to claim 1, which is characterized in that the material of institute's bitline contact film is selected from polycrystalline
The deposition of silicon, institute's bitline contact film is by low-pressure chemical vapor deposition mode, atomic layer deposition mode, atomic layer seed
The one kind deposited in the complex method and plasma enhanced chemical vapor deposition mode in conjunction with low-pressure chemical vapor deposition is come
It carries out.
7. manufacturing method according to any one of claims 1 to 6, which is characterized in that the material of institute's bitline contact film
Selected from P DOPOS doped polycrystalline silicons in situ, the deposition step of institute's bitline contact film includes:
The pressure in the deposition boiler tube board is controlled in the range of 0.05 support to 4 support and in the deposition boiler tube board
Temperature in the range of 350 degrees Celsius to 625 degrees Celsius;And
Depositional mode to be saturated adatom layer seed deposits the original position P DOPOS doped polycrystalline silicons, wherein control doping P's is dense
Degree is per cubic centimeter 1019A to per cubic centimeter 5 × 1021It is a.
8. a kind of manufacturing method of storage node contacts embolism, which is characterized in that including:
A substrate is provided, there is the substrate insulation system of covering bit line and the memory node in the insulation system to connect
Touch slot;
It will be placed in a deposition boiler tube board with the substrate of the storage node contacts slot, and etched by chemical gaseous phase
Method removes removing natural oxidizing layer, wherein the natural oxidizing layer is formed on the substrate of the storage node contacts trench bottom simultaneously
The substrate is formed in the waiting process before entering the deposition boiler tube board;
Storage node contacts film is deposited in the deposition boiler tube board above the substrate, makes the storage node contacts
Film is filled in the storage node contacts slot and covers the insulation system;And
Patterning etches the storage node contacts film to form storage node contacts embolism.
9. manufacturing method according to claim 8, which is characterized in that the chemical gaseous phase lithographic method includes:
The pressure in the deposition boiler tube board is controlled in the range of 0.1 support to 100 support and in the deposition boiler tube board
Temperature in the range of 100 degrees Celsius to 625 degrees Celsius;
It is passed through etching gas to the deposition boiler tube board, the etching gas is selected from by hydrogen fluoride, chlorine trifluoride and trifluoro
Change one of the group that nitrogen is constituted;
The etching gas is maintained at the predetermined time in the deposition boiler tube board, so that the etching gas and the nature
Oxide layer is reacted;And
Vacuumize and inject nitrogen to deposition boiler tube board cycle, make remaining etching gas and the etching gas and
The deposition boiler tube board is discharged in the byproduct of reaction gas of the natural oxidizing layer.
10. manufacturing method according to claim 8, which is characterized in that the predetermined time is according to the natural oxidizing layer
Thickness set so that the natural oxidizing layer is reacted completely.
11. manufacturing method according to claim 8, which is characterized in that the step of one substrate of the offer includes:
Prepare the substrate;
Bit line contact embolism and the bit line are formed on the substrate, the bit line covers institute's bitline contact embolism;
Form the insulation system;
The insulation system is etched, until exposing the substrate, to form the storage node contacts in the insulation system
Slot;
Cleaning tool has the substrate of the storage node contacts slot.
12. manufacturing method according to claim 11, which is characterized in that cleaning tool has the institute of the storage node contacts slot
The mode for stating substrate includes wet-cleaning.
13. manufacturing method according to claim 8, which is characterized in that the material of the storage node contacts film is selected from
In polysilicon, the deposition of the storage node contacts film be by low-pressure chemical vapor deposition mode, atomic layer deposition mode,
The complex method and plasma enhanced chemical vapor deposition mode of atomic layer seed deposition combination low-pressure chemical vapor deposition
In a kind of carry out.
14. according to claim 8 to 13 any one of them manufacturing method, which is characterized in that the storage node contacts film
Material be selected from original position P DOPOS doped polycrystalline silicons, the deposition step of the storage node contacts film includes:
The pressure in the deposition boiler tube board is controlled in the range of 0.05 support to 4 support and in the deposition boiler tube board
Temperature in the range of 350 degrees Celsius to 625 degrees Celsius;And
Depositional mode to be saturated adatom layer seed deposits the original position P DOPOS doped polycrystalline silicons, wherein control doping P's is dense
Degree is per cubic centimeter 1019A to per cubic centimeter 5 × 1021It is a.
15. a kind of manufacturing method of polysilicon contact film, which is characterized in that including:
Prepare substrate;
Clean the substrate;
The substrate is placed in a deposition boiler tube board, the autoxidation of substrate surface is removed by chemical gaseous phase lithographic method
Layer, wherein the natural oxidizing layer is formed in the substrate in the waiting process before entering the deposition boiler tube board;
Deposit polycrystalline silicon contacts film above the substrate in the deposition boiler tube board.
16. manufacturing method according to claim 15, which is characterized in that described to remove institute by chemical gaseous phase lithographic method
The step of stating natural oxidizing layer include:
The pressure in the deposition boiler tube board is controlled in the range of 0.1 support to 100 support and in the deposition boiler tube board
Temperature in the range of 100 degrees Celsius to 625 degrees Celsius;
It is passed through etching gas to the deposition boiler tube board, the etching gas is selected from by hydrogen fluoride, chlorine trifluoride and trifluoro
Change one of the group that nitrogen is constituted;
The etching gas is maintained at the predetermined time in the deposition boiler tube board, so that the etching gas and the nature
Oxide layer is reacted;And
To the boiler tube board cycle vacuumize and inject nitrogen, make remnants etching gas and the etching gas with it is described
The boiler tube board is discharged in the byproduct of reaction gas of natural oxidizing layer.
17. a kind of manufacturing method of storage node contacts embolism, which is characterized in that including:
A substrate is provided, the substrate has bit line contact hole in a insulating layer;
It will be placed in a deposition boiler tube board with the substrate in institute's bitline contact hole, and pass through chemical gaseous phase lithographic method
Removal is formed in first natural oxidizing layer in bitline contact bottom hole portion of institute, wherein first natural oxidizing layer is formed in tool
The substrate in bitline contact hole is in the waiting process before entering the deposition boiler tube board;
Depositing bitlines contact film above the substrate in the deposition boiler tube board, and institute's bitline contact film is made to fill
In institute's bitline contact hole and cover the insulating layer;And
Institute's bitline contact film is etched, until exposing the insulating layer, to form bit line contact embolism.
The bit line of covering institute bitline contact embolism and the insulation system of the covering bit line are formed above the substrate, and
Storage node contacts slot is formed in the insulating layer;
It will be placed in the deposition boiler tube board with the substrate of the storage node contacts slot, and carved by chemical gaseous phase
Etching method removes the second nature oxide layer, wherein the second nature oxide layer is formed in the storage node contacts trench bottom
Substrate on and be formed in the substrate with the storage node contacts slot enter the deposition boiler tube board before etc.
During waiting for;
Storage node contacts film is deposited in the deposition boiler tube board above the substrate, makes the storage node contacts
Film is filled in the storage node contacts slot and covers the insulating layer;And
Patterning etches the storage node contacts film to form storage node contacts embolism.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201810347664.3A CN108538780A (en) | 2018-04-18 | 2018-04-18 | The manufacturing method of bit line/storage node contacts embolism and polysilicon contact film |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201810347664.3A CN108538780A (en) | 2018-04-18 | 2018-04-18 | The manufacturing method of bit line/storage node contacts embolism and polysilicon contact film |
Publications (1)
Publication Number | Publication Date |
---|---|
CN108538780A true CN108538780A (en) | 2018-09-14 |
Family
ID=63481468
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201810347664.3A Pending CN108538780A (en) | 2018-04-18 | 2018-04-18 | The manufacturing method of bit line/storage node contacts embolism and polysilicon contact film |
Country Status (1)
Country | Link |
---|---|
CN (1) | CN108538780A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN111446156A (en) * | 2020-04-03 | 2020-07-24 | 合肥晶合集成电路有限公司 | Semiconductor structure forming method and semiconductor structure |
CN115274663A (en) * | 2021-04-30 | 2022-11-01 | 长鑫存储技术有限公司 | Semiconductor structure and forming method thereof |
Citations (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4855258A (en) * | 1987-10-22 | 1989-08-08 | Ncr Corporation | Native oxide reduction for sealing nitride deposition |
EP0638923A2 (en) * | 1993-07-30 | 1995-02-15 | Applied Materials, Inc. | Low temperature etching in cold-wall CVD systems |
US6013134A (en) * | 1998-02-18 | 2000-01-11 | International Business Machines Corporation | Advance integrated chemical vapor deposition (AICVD) for semiconductor devices |
CN1292571A (en) * | 1999-09-10 | 2001-04-25 | 三星电子株式会社 | Semiconductor memory device with capacitor protective layer and preparing method thereof |
CN1448992A (en) * | 2002-03-30 | 2003-10-15 | 海力士半导体有限公司 | Method of forming contact plug in semiconductor device |
CN1574290A (en) * | 2003-05-21 | 2005-02-02 | 海力士半导体有限公司 | Method of manufacturing semiconductor device |
CN1577823A (en) * | 2003-06-25 | 2005-02-09 | 三星电子株式会社 | Semiconductor device and method of manufacturing the same |
CN101191252A (en) * | 2006-11-20 | 2008-06-04 | 上海华虹Nec电子有限公司 | Method for removing natural oxidizing layer before silicon chip low-temperature epitaxy growth |
CN102044495A (en) * | 2009-10-09 | 2011-05-04 | 海力士半导体有限公司 | Method for manufacturing semiconductor device with buried gate |
CN102142366A (en) * | 2010-01-28 | 2011-08-03 | 无锡华润上华半导体有限公司 | Method for forming self-aligned metallic silicide |
KR20110105168A (en) * | 2010-03-18 | 2011-09-26 | 주식회사 하이닉스반도체 | Semiconductor device and method for manuafacturing of the same |
CN102453957A (en) * | 2010-10-25 | 2012-05-16 | 上海华虹Nec电子有限公司 | Method for reducing germanium-silicon epitaxial surface defects |
US20120156869A1 (en) * | 2010-12-15 | 2012-06-21 | Jong-Han Shin | Method for fabricating semiconductor device with buried gate |
CN107507761A (en) * | 2017-08-31 | 2017-12-22 | 长江存储科技有限责任公司 | A kind of polysilicon deposition method and polysilicon deposition equipment |
-
2018
- 2018-04-18 CN CN201810347664.3A patent/CN108538780A/en active Pending
Patent Citations (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4855258A (en) * | 1987-10-22 | 1989-08-08 | Ncr Corporation | Native oxide reduction for sealing nitride deposition |
EP0638923A2 (en) * | 1993-07-30 | 1995-02-15 | Applied Materials, Inc. | Low temperature etching in cold-wall CVD systems |
US6013134A (en) * | 1998-02-18 | 2000-01-11 | International Business Machines Corporation | Advance integrated chemical vapor deposition (AICVD) for semiconductor devices |
CN1292571A (en) * | 1999-09-10 | 2001-04-25 | 三星电子株式会社 | Semiconductor memory device with capacitor protective layer and preparing method thereof |
CN1448992A (en) * | 2002-03-30 | 2003-10-15 | 海力士半导体有限公司 | Method of forming contact plug in semiconductor device |
CN1574290A (en) * | 2003-05-21 | 2005-02-02 | 海力士半导体有限公司 | Method of manufacturing semiconductor device |
CN1577823A (en) * | 2003-06-25 | 2005-02-09 | 三星电子株式会社 | Semiconductor device and method of manufacturing the same |
CN101191252A (en) * | 2006-11-20 | 2008-06-04 | 上海华虹Nec电子有限公司 | Method for removing natural oxidizing layer before silicon chip low-temperature epitaxy growth |
CN102044495A (en) * | 2009-10-09 | 2011-05-04 | 海力士半导体有限公司 | Method for manufacturing semiconductor device with buried gate |
CN102142366A (en) * | 2010-01-28 | 2011-08-03 | 无锡华润上华半导体有限公司 | Method for forming self-aligned metallic silicide |
KR20110105168A (en) * | 2010-03-18 | 2011-09-26 | 주식회사 하이닉스반도체 | Semiconductor device and method for manuafacturing of the same |
CN102453957A (en) * | 2010-10-25 | 2012-05-16 | 上海华虹Nec电子有限公司 | Method for reducing germanium-silicon epitaxial surface defects |
US20120156869A1 (en) * | 2010-12-15 | 2012-06-21 | Jong-Han Shin | Method for fabricating semiconductor device with buried gate |
CN107507761A (en) * | 2017-08-31 | 2017-12-22 | 长江存储科技有限责任公司 | A kind of polysilicon deposition method and polysilicon deposition equipment |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN111446156A (en) * | 2020-04-03 | 2020-07-24 | 合肥晶合集成电路有限公司 | Semiconductor structure forming method and semiconductor structure |
CN115274663A (en) * | 2021-04-30 | 2022-11-01 | 长鑫存储技术有限公司 | Semiconductor structure and forming method thereof |
CN115274663B (en) * | 2021-04-30 | 2024-08-02 | 长鑫存储技术有限公司 | Semiconductor structure and forming method thereof |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US9646975B2 (en) | Lateral stack of cobalt and a cobalt-semiconductor alloy for control gate electrodes in a memory structure | |
US9419012B1 (en) | Three-dimensional memory structure employing air gap isolation | |
JP5147183B2 (en) | Capacitor having nanotube and method of manufacturing the same | |
CN110462829A (en) | Three dimensional memory device and its manufacturing method with discrete direct source electrode band contact | |
CN110088901A (en) | The three dimensional memory device and its manufacturing method of mechanical stability semiconductor pedestal with enhancing | |
KR101831936B1 (en) | Method for forming a thin film and method for manufacturing a semiconductor device by using the same | |
WO2018093446A1 (en) | Three-dimensional memory device having select gate electrode that is thicker than word lines and method of making thereof | |
WO2017074552A1 (en) | Robust nucleation layers for enhanced fluorine protection and stress reduction in 3d nand word lines | |
US6608341B2 (en) | Trench capacitor with capacitor electrodes | |
WO2016167984A1 (en) | A metal-semiconductor alloy region for enhancing on current in a three-dimensional memory structure | |
CN102265400A (en) | Carbon-based memory elements exhibiting reduced delamination and methods of forming the same | |
JP2002343743A (en) | Method of forming contact plug of semiconductor device | |
CN108538780A (en) | The manufacturing method of bit line/storage node contacts embolism and polysilicon contact film | |
JP2002134715A (en) | Semiconductor integrated circuit device and method for manufacturing the same | |
US6204119B1 (en) | Manufacturing method for a capacitor in an integrated memory circuit | |
CN114400287A (en) | Semiconductor device and preparation method thereof | |
KR19980071626A (en) | Manufacturing method of capacitor for semiconductor device | |
EP0941552B1 (en) | Semiconductor device with memory capacitor and method of manufacturing such a device | |
CN207977313U (en) | Semiconductor devices | |
JP2007141904A (en) | Capacitor and its manufacturing method | |
CN110911348A (en) | Method for forming contact plug of semiconductor integrated circuit device | |
US20090197384A1 (en) | Semiconductor memory device and method for manufacturing semiconductor memory device | |
US8138572B2 (en) | Semiconductor device and method for fabricating the same | |
CN113496954B (en) | Memory forming method and memory | |
WO2022213514A1 (en) | Fabrication method for memory and memory |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PB01 | Publication | ||
PB01 | Publication | ||
SE01 | Entry into force of request for substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
TA01 | Transfer of patent application right |
Effective date of registration: 20181008 Address after: 230000 room 630, Hai Heng mansion 6, Cui Wei Road, Hefei economic and Technological Development Zone, Anhui Applicant after: Changxin Storage Technology Co., Ltd. Address before: 230000 room 526, Hai Heng mansion 6, Cui Wei Road, Hefei economic and Technological Development Zone, Anhui Applicant before: Ever power integrated circuit Co Ltd |
|
TA01 | Transfer of patent application right | ||
RJ01 | Rejection of invention patent application after publication |
Application publication date: 20180914 |
|
RJ01 | Rejection of invention patent application after publication |