CN108493099A - A kind of wafer bonding method - Google Patents
A kind of wafer bonding method Download PDFInfo
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- CN108493099A CN108493099A CN201810322837.6A CN201810322837A CN108493099A CN 108493099 A CN108493099 A CN 108493099A CN 201810322837 A CN201810322837 A CN 201810322837A CN 108493099 A CN108493099 A CN 108493099A
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- 238000000034 method Methods 0.000 title claims abstract description 84
- 230000008569 process Effects 0.000 claims abstract description 27
- 238000005530 etching Methods 0.000 claims description 54
- 239000011241 protective layer Substances 0.000 claims description 17
- 238000005406 washing Methods 0.000 claims description 16
- 238000004140 cleaning Methods 0.000 claims description 12
- 239000007789 gas Substances 0.000 claims description 12
- 239000010410 layer Substances 0.000 claims description 10
- 229910015844 BCl3 Inorganic materials 0.000 claims description 6
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 claims description 6
- XPDWGBQVDMORPB-UHFFFAOYSA-N Fluoroform Chemical compound FC(F)F XPDWGBQVDMORPB-UHFFFAOYSA-N 0.000 claims description 6
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 claims description 6
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 claims description 6
- 238000001312 dry etching Methods 0.000 claims description 4
- 229920002120 photoresistant polymer Polymers 0.000 claims description 4
- VHUUQVKOLVNVRT-UHFFFAOYSA-N Ammonium hydroxide Chemical compound [NH4+].[OH-] VHUUQVKOLVNVRT-UHFFFAOYSA-N 0.000 claims description 3
- 239000004642 Polyimide Substances 0.000 claims description 3
- 239000000908 ammonium hydroxide Substances 0.000 claims description 3
- 239000008367 deionised water Substances 0.000 claims description 3
- 229910021641 deionized water Inorganic materials 0.000 claims description 3
- 229920001721 polyimide Polymers 0.000 claims description 3
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims description 3
- 230000007547 defect Effects 0.000 abstract description 8
- 230000009467 reduction Effects 0.000 abstract description 4
- 235000012431 wafers Nutrition 0.000 description 154
- 239000000758 substrate Substances 0.000 description 11
- 239000002184 metal Substances 0.000 description 7
- 238000010586 diagram Methods 0.000 description 6
- 238000005516 engineering process Methods 0.000 description 6
- 238000004519 manufacturing process Methods 0.000 description 6
- 239000000126 substance Substances 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 150000004767 nitrides Chemical class 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- 230000006870 function Effects 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 4
- 238000000576 coating method Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 206010037660 Pyrexia Diseases 0.000 description 2
- 230000000295 complement effect Effects 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- FAQYAMRNWDIXMY-UHFFFAOYSA-N trichloroborane Chemical compound ClB(Cl)Cl FAQYAMRNWDIXMY-UHFFFAOYSA-N 0.000 description 2
- 230000009471 action Effects 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005496 eutectics Effects 0.000 description 1
- 238000000227 grinding Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/185—Joining of semiconductor bodies for junction formation
- H01L21/187—Joining of semiconductor bodies for junction formation by direct bonding
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02057—Cleaning during device manufacture
- H01L21/0206—Cleaning during device manufacture during, before or after processing of insulating layers
- H01L21/02065—Cleaning during device manufacture during, before or after processing of insulating layers the processing being a planarization of insulating layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31127—Etching organic layers
- H01L21/31133—Etching organic layers by chemical means
- H01L21/31138—Etching organic layers by chemical means by dry-etching
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- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Cleaning Or Drying Semiconductors (AREA)
Abstract
The invention discloses a kind of wafer bonding methods, the wafer bonding method passed through after the step of providing the first wafer and the second wafer, before the step of being mutually bonded in the front of first wafer with the front of second wafer, the step of increasing by a pretreating process, the pretreating process can reduce the residue of (or even removal) first wafer and/or second wafer, to, in the step of being mutually bonded in the front of first wafer with the front of second wafer, (reduction) wafer bonding cavity blemish rate can be improved, reduce the general defect rate of product, promote properties of product.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, more particularly to a kind of wafer bonding method.
Background technology
The appearance of three dimensional integrated circuits provides a new technology solution for the sustainable development of semiconductor and microelectric technique
Certainly scheme, by the way that the identical or different chip of two or more functions is carried out the three-dimensionally integrated performance that chip can be improved, simultaneously
The metal interconnection between functional chip can also be greatly shortened, reduce fever, power consumption and delay, and to realize sophisticated functions
System on chip provides may.
In three dimensional integrated circuits, wafer bonding method is core emphasis, and wherein wafer bonding cavity blemish rate is to weigh
One core parameter of wafer bonding method, wafer bonding cavity blemish rate can influence the general defect rate of product.Therefore, having must
A kind of wafer bonding method improving wafer bonding cavity blemish rate is provided.
Invention content
Technical problem to be solved by the invention is to provide a kind of wafer bonding methods, can be effectively improved wafer bonding sky
Hole defect rate, to enhance product performance.
In order to solve the above technical problems, a kind of wafer bonding method provided by the invention, including：
First wafer and the second wafer are provided；
Pretreating process is carried out to reduce the residue of first wafer to first wafer, and/or, to described the
Two wafers carry out pretreating process to reduce the residue of second wafer；
The front of first wafer is mutually bonded with the front of second wafer.
Further, in the wafer bonding method, the step of pretreating process, includes：In first wafer
Positive or described second wafer one protective layer of front surface coated, by side washing technique remove the part protective layer to expose
The edge at the edge of first wafer or second wafer；Pass through the side of first wafer of the first etching removal exposure
The residue at the edge of edge or second wafer；Positive or described second crystalline substance of first wafer is removed by the second etching
Round positive remaining protective layer；Cleaning is carried out to the front of positive or described second wafer of first wafer.
Further, in the wafer bonding method, the thickness of the protective layer isThe guarantor
Sheath is photoresist layer or polyimide layer.
Preferably, in the wafer bonding method, the side washing width of the side washing technique is 0.2mm~5.0mm.
Further, in the wafer bonding method, first etching and second etching are dry etching.
Preferably, in the wafer bonding method, the etching gas of first etching includes CF4、CHF3、C4F8、
SF6、Cl2, HBr and BCl3At least one of, alternatively, the etching gas of first etching includes CF4、CHF3、C4F8、SF6、
Cl2, HBr and BCl3At least one of with Ar formed mixed gas.
Preferably, in the wafer bonding method, the chamber pressure of first etching is 50mT~500mT, described
The power of first etching is 100W~4000W, and the time of first etching is 10s~300s.
Preferably, in the wafer bonding method, the etching gas of second etching includes O2、N2、CF4And N2H2In
At least one.
Preferably, in the wafer bonding method, the chamber pressure of second etching is 200mT~400mT, described
The power of second etching is 300W~4000W, and the time of second etching is 20s~360s.
Preferably, in the wafer bonding method, the solution of the cleaning include hydrofluoric acid, hydrochloric acid, hydrogen peroxide,
The time of at least one of ammonium hydroxide and deionized water, the cleaning is 5s~360s.
Compared with prior art, the invention has the advantages that：
The wafer bonding method of the present invention by the first wafer is provided and the step of the second wafer after, by described the
The step of front of one wafer is with before positive the step of being mutually bonded of second wafer, increasing by a pretreating process, it is described
Pretreating process can reduce the residue of (or even removal) described first wafer and/or second wafer, to by institute
In the step of front for stating the first wafer is mutually bonded with the front of second wafer, (reduction) wafer bonding cavity can be improved
Ratio of defects reduces the general defect rate of product, promotes properties of product.
Description of the drawings
Fig. 1 and Fig. 2 is corresponding structural schematic diagram in a kind of wafer bonding method；
Fig. 3 is the flow diagram of wafer bonding method described in the embodiment of the present invention；
Fig. 4 is the flow diagram of pretreating process described in wafer bonding method described in the embodiment of the present invention；
Fig. 5 to Fig. 9 is the corresponding structural schematic diagram of each step in wafer bonding method described in the embodiment of the present invention.
Specific implementation mode
In the manufacturing process of three dimensional integrated circuits, wafer bonding method includes：First wafer 10 and the second wafer are provided
20, as shown in Figure 1, first wafer 10 can be device wafers, the device wafers include a device architecture；Described second
Wafer 20 can be carrier wafer, and the carrier wafer includes a circuit structure corresponding with the device architecture；Then, will
The front 100 of first wafer mutually bonds together to form bonding wafer with the front 200 of the second wafer, as shown in Fig. 2, still, it should
Bonding wafer will appear wafer bonding cavity blemish C, with back-illuminated type CMOS (Complementary Metal Oxide
Semiconductor, complementary metal oxide semiconductor) for image sensor, wafer bonding cavity blemish C can continue rear
Grain defect is generated in continuous processing procedure, to influence product optical property.
Inventor has found that wafer bonding cavity blemish C frequently occurs in the edge of bonding wafer, and by deeply grinding
Study carefully it has furthermore been found that before the front 100 of first wafer is mutually bonded with the front 200 of second wafer, described
(those of ordinary skill in the art know A, in wafer manufacturing process, in wafer at the chamfering of the edge of one wafer 10
The edge of front and back can all have A at chamfering) there are residue B, as shown in Figure 1；Then, by first wafer
Front 100 be mutually bonded with the front 200 of second wafer during, by surface activation technique, the residue B meetings
It peels off to the surface of first wafer 10, then, bonding wafer will form wafer at the position where the residue
It is bonded cavity blemish C, as shown in Figure 2.
Based on the studies above and discovery, inventor proposes a kind of new wafer bonding method, as shown in figure 3, including：
Step S1, first wafer and the second wafer are provided；
Step S2, pretreating process is carried out to reduce the residue of first wafer to first wafer, and/or,
Pretreating process is carried out to reduce the residue of second wafer to second wafer；
Step S3, the front of positive and second wafer of first wafer is mutually bonded.
The wafer bonding method by the first wafer is provided and the step of the second wafer after, will first crystalline substance
The step of round front is with before positive the step of being mutually bonded of second wafer, increasing by a pretreating process, the pre- place
Science and engineering skill can reduce the residue of (or even removal) described first wafer and/or second wafer, to by described the
In the step of front of one wafer is mutually bonded with the front of second wafer, (reduction) wafer bonding cavity blemish can be improved
Rate reduces the general defect rate of product, promotes properties of product.
A kind of wafer bonding method of the present invention is described in more detail below in conjunction with flow chart and schematic diagram,
In illustrate the preferred embodiment of the present invention, it should be appreciated that those skilled in the art can change invention described herein, and
Still the advantageous effects of the present invention are realized.Therefore, following description should be understood as knowing extensively for those skilled in the art
Road, and it is not intended as limitation of the present invention.
The present invention is more specifically described by way of example with reference to attached drawing in the following passage.It is wanted according to following explanation and right
Ask book, advantages and features of the invention that will become apparent from.It should be noted that attached drawing is all made of very simplified form and uses non-
Accurately ratio, only for the purpose of facilitating and clarifying the purpose of the embodiments of the invention.
A kind of content of wafer bonding method of the present invention is discussed in detail in the embodiment of wafer bonding method exemplified below,
It will be clear that present disclosure is not restricted to following embodiment, other pass through the normal of those of ordinary skill in the art
The improvement of rule technological means is also within the thought range of the present invention.
It please refers to Fig.1, Fig. 3-Fig. 9, wherein Fig. 3, Fig. 4 show that the flow of wafer bonding method described in the present embodiment is shown
It is intended to, Fig. 1, Fig. 5 to Fig. 9 show the corresponding structural schematic diagram of each step in wafer bonding method described in the present embodiment.
First, step S1 is executed, provides the first wafer 10 and the second wafer 20, as shown in Figure 1.Preferably, the present embodiment
In, first wafer 10 is device wafers, and the device wafers include a device architecture, and the device architecture includes micro electronmechanical
System (MEMS), memory (Memory) and inductor (Sensor) etc., the device architecture have micro-system, storage, sensing
The functions such as device；First wafer 10 further includes the first substrate, it is preferred that first substrate is silicon substrate, oxide substrate
Or nitride, the device architecture are located on first substrate；Second wafer 20 is carrier wafer, the carrier
Wafer includes a circuit structure corresponding with the device architecture, and the circuit structure includes that combinational logic circuit, sequential are patrolled
Circuit is collected, connection carrier is provided for wafer bonding by the circuit structure；Second wafer 20 further includes and described first
Corresponding second substrate of substrate, it is preferred that second substrate may be silicon substrate, oxide substrate or nitride
Deng the circuit structure is located on second substrate.In the process for manufacturing first wafer 10 and second wafer 20
In, A can have some residues B at the chamfering of A and/or second wafer 20 at the chamfering of first wafer 10, such as more
Crystal silicon, oxide, nitride or metal etc..
Then, step S2 is executed, pretreating process is carried out to reduce the residual of first wafer to first wafer
Object, and/or, pretreating process is carried out to reduce the residue of second wafer to second wafer.Preferably, in this reality
It applies in example, only for carrying out pretreating process to first wafer 10.Obviously, those of ordinary skill in the art are readily appreciated that
, it in the actual production process, can be according to actual conditions, selectively to first wafer 10 and second wafer
20 carry out pretreating process, do not limit herein.
Preferably, in the present embodiment, as shown in figure 4, the pretreating process includes：
Step S21, in one protective layer of front surface coated of first wafer 10, the part guarantor is removed by side washing technique
Sheath is to expose the edge of first wafer 10；
Step S22, pass through the residue at the edge of first wafer 10 of the first etching removal exposure；
Step S23, the positive remaining protective layer of first wafer 10 is removed by the second etching；
Step S24, cleaning is carried out to the front of first wafer.
Specifically, first, in one protective layer 30 of front surface coated of first wafer 10, the protective layer 30 can be light
Resistance layer or class photoresist layer, such as can be, but not limited to as positive/negative photoresist layer or polyimide layer, the thickness of the protective layer 30
Can beSuch as can beOrDeng；Then, it is removed by side washing technique
The part protective layer is to expose the edge of first wafer 10, it is preferred that the side washing width d of the side washing technique can be with
For 0.2mm~5.0mm, as shown in Figure 5.Above-mentioned coating processes and side washing technique carry out in litho machine, after the coating process,
Remove in the side washing region at the edge that side washing liquid is sprayed at first wafer 10 by nozzle that (its side washing width d can by side washing
With between 0.2mm~5.0mm ranges), to dissolve the protective layer in side washing region, to expose first wafer
10 edge A at the chamfering is exposed.
Then, pass through the residue at the edge of first wafer 10 of the first etching removal exposure, i.e., described first quarter
Residue B of the etching off except A at the chamfering.Preferably, first etching is dry etching, as shown in fig. 6, using plasma
Body etches the residue B, and the etching gas of first etching may include CF4、CHF3、C4F8、SF6、Cl2, HBr and BCl3
At least one of, alternatively, the etching gas of first etching can also include CF4、CHF3、C4F8、SF6、Cl2, HBr and BCl3
At least one of with Ar formed mixed gas；The chamber pressure of first etching is 50mT~500mT, first etching
Power be 100W~4000W, the time of first etching is 10s~300s, such as can be 60s, 120s or 240s.
Next, removing the positive remaining protective layer 30 of first wafer 10 by the second etching.Preferably, described
The etching gas of second etching or dry etching, second etching may include O2、N2、CF4And N2H2In at least
It is a kind of.The chamber pressure of second etching is 200mT~400mT, and the power of second etching is 300W~4000W, institute
State the second etching time be 20s~360s, such as can be 60s, 120s, 180s or 240s, as shown in Figure 7.
Then, cleaning is carried out to the front of first wafer 10, as shown in figure 8, the purpose of the cleaning
It is to remove some the etching accessory substances generated in first etching and second etching technics.Preferably, described
The solution of cleaning may include at least one of hydrofluoric acid, hydrochloric acid, hydrogen peroxide, ammonium hydroxide and deionized water, the cleaning
The time of technique is 5s~360s, such as can be 60s, 120s, 180s or 240s.It obviously, can foundation in actual process
The type of practical cleaning situation and the accessory substance, can selectively carry out that technique is cleaned multiple times, until the front of wafer meets
Process requirements, this is that those of ordinary skill in the art are readily comprehensible, and this will not be repeated here.By above-mentioned pretreating process, just
The residue B at A at the chamfering of first wafer 10 can be removed, subsequent technique is conducive to.
Finally, after completing above-mentioned pretreating process, just by the front 100 of first wafer and second wafer
Face 20 phase bonding, as shown in Figure 9.In the present embodiment, the front 100 of first wafer can be, but not limited to for oxide skin(coating),
Nitride layer or metal layer, then bonding technology can be, but not limited to as silicon base and oxide bond, oxide and oxide key
Close, oxide be bonded with nitride and metal and metal bonding, the bonding technology can be eutectic bonding, metal heat pressing
One kind in bonding, silicon melting bonding and polymer-bonded bonding.The bonding technology forms bonding crystalline substance using bonding machine platform
Circle, bonding wafer can improve the function of chip and not limited by one single chip manufacturing process, moreover it is possible to shorten functional chip it
Between metal interconnection, to effectively reduce the performances such as fever, power consumption, delay.
In the present embodiment, because of the pretreating process by front, residue at the chamfering of first wafer 10 by
Greatly reduce or even completely remove, then the wafer bonding cavity blemish rate of the bonding wafer formed can substantially reduce, and can drop
The wafer bonding cavity blemish rate of low entire product, to promote properties of product.
To sum up, wafer bonding method of the invention is by after the step of providing the first wafer and the second wafer, inciting somebody to action
Before the step of front of first wafer is mutually bonded with the front of second wafer, increase the step of a pretreating process
Suddenly, the pretreating process can reduce the residue of (or even removal) first wafer and/or second wafer, from
And in the step of being mutually bonded in the front of first wafer with the front of second wafer, (reduction) crystalline substance can be improved
Round key closes cavity blemish rate, reduces the general defect rate of product, promotes properties of product.
Obviously, various changes and modifications can be made to the invention without departing from essence of the invention by those skilled in the art
God and range.In this way, if these modifications and changes of the present invention belongs to the range of the claims in the present invention and its equivalent technologies
Within, then the present invention is also intended to include these modifications and variations.
Claims (10)
1. a kind of wafer bonding method, which is characterized in that including：
First wafer and the second wafer are provided；
Pretreating process is carried out to reduce the residue of first wafer to first wafer, and/or, it is brilliant to described second
Circle carries out pretreating process to reduce the residue of second wafer；
The front of first wafer is mutually bonded with the front of second wafer.
2. wafer bonding method as described in claim 1, which is characterized in that the step of pretreating process includes：
In one protective layer of front surface coated of positive or described second wafer of first wafer, part is removed by side washing technique
The protective layer is to expose the edge of first wafer or the edge of second wafer；
Pass through the residual at the edge of second wafer at the edge or exposure of first wafer of the first etching removal exposure
Object；
The positive remaining protective layer of positive or described second wafer of first wafer is removed by the second etching；
Cleaning is carried out to the front of positive or described second wafer of first wafer.
3. wafer bonding method as claimed in claim 2, which is characterized in that the thickness of the protective layer isThe protective layer is photoresist layer or polyimide layer.
4. wafer bonding method as claimed in claim 2, which is characterized in that the side washing width of the side washing technique is 0.2mm
~5.0mm.
5. wafer bonding method as claimed in claim 2, which is characterized in that first etching and second etching are
Dry etching.
6. wafer bonding method as claimed in claim 5, which is characterized in that the etching gas of first etching includes CF4、
CHF3、C4F8、SF6、Cl2, HBr and BCl3At least one of, alternatively, the etching gas of first etching includes CF4、CHF3、
C4F8、SF6、Cl2, HBr and BCl3At least one of with Ar formed mixed gas.
7. wafer bonding method as claimed in claim 5, which is characterized in that it is described first etching chamber pressure be 50mT~
The power of 500mT, first etching are 100W~4000W, and the time of first etching is 10s~300s.
8. wafer bonding method as claimed in claim 5, which is characterized in that the etching gas of second etching includes O2、
N2、CF4And N2H2At least one of.
9. wafer bonding method as claimed in claim 5, which is characterized in that the chamber pressure of second etching is 200mT
The power of~400mT, second etching are 300W~4000W, and the time of second etching is 20s~360s.
10. wafer bonding method as claimed in claim 2, which is characterized in that the solution of the cleaning include hydrofluoric acid,
The time of at least one of hydrochloric acid, hydrogen peroxide, ammonium hydroxide and deionized water, the cleaning is 5s~360s.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111564362A (en) * | 2020-06-12 | 2020-08-21 | 武汉新芯集成电路制造有限公司 | Wafer edge processing method |
| CN115070515A (en) * | 2022-06-20 | 2022-09-20 | 长春长光圆辰微电子技术有限公司 | Method for reducing CMP large area edge peeling in GOI production |
| CN115579282A (en) * | 2022-11-04 | 2023-01-06 | 湖北三维半导体集成创新中心有限责任公司 | Method for processing wafer |
Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050215056A1 (en) * | 2004-03-29 | 2005-09-29 | Patrick Morrow | Bonded wafer processing method |
| CN102640267A (en) * | 2009-12-17 | 2012-08-15 | 朗姆研究公司 | Method and apparatus for processing bevel edge |
| CN102709175A (en) * | 2012-05-23 | 2012-10-03 | 上海宏力半导体制造有限公司 | Forming method of photoresist layer in deep groove process |
| CN103019050A (en) * | 2011-09-22 | 2013-04-03 | 三星电子株式会社 | Diluent composition for RRC process and EBR process, and apparatus for supplying the same |
| CN104779178A (en) * | 2014-01-13 | 2015-07-15 | 中芯国际集成电路制造(上海)有限公司 | Bottom anti-reflective coating forming method |
| CN105070668A (en) * | 2015-08-06 | 2015-11-18 | 武汉新芯集成电路制造有限公司 | Wafer-level chip packaging method |
| CN106876252A (en) * | 2017-02-14 | 2017-06-20 | 上海华虹宏力半导体制造有限公司 | The lithographic method of semiconductor devices |
| CN108054107A (en) * | 2017-12-01 | 2018-05-18 | 武汉新芯集成电路制造有限公司 | A kind of wafer bonding method based on pre-modified technique |
| CN108054081A (en) * | 2017-11-30 | 2018-05-18 | 武汉新芯集成电路制造有限公司 | A kind of wafer bonding method based on pretreating process |
-
2018
- 2018-04-11 CN CN201810322837.6A patent/CN108493099A/en active Pending
Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050215056A1 (en) * | 2004-03-29 | 2005-09-29 | Patrick Morrow | Bonded wafer processing method |
| CN102640267A (en) * | 2009-12-17 | 2012-08-15 | 朗姆研究公司 | Method and apparatus for processing bevel edge |
| CN103019050A (en) * | 2011-09-22 | 2013-04-03 | 三星电子株式会社 | Diluent composition for RRC process and EBR process, and apparatus for supplying the same |
| CN102709175A (en) * | 2012-05-23 | 2012-10-03 | 上海宏力半导体制造有限公司 | Forming method of photoresist layer in deep groove process |
| CN104779178A (en) * | 2014-01-13 | 2015-07-15 | 中芯国际集成电路制造(上海)有限公司 | Bottom anti-reflective coating forming method |
| CN105070668A (en) * | 2015-08-06 | 2015-11-18 | 武汉新芯集成电路制造有限公司 | Wafer-level chip packaging method |
| CN106876252A (en) * | 2017-02-14 | 2017-06-20 | 上海华虹宏力半导体制造有限公司 | The lithographic method of semiconductor devices |
| CN108054081A (en) * | 2017-11-30 | 2018-05-18 | 武汉新芯集成电路制造有限公司 | A kind of wafer bonding method based on pretreating process |
| CN108054107A (en) * | 2017-12-01 | 2018-05-18 | 武汉新芯集成电路制造有限公司 | A kind of wafer bonding method based on pre-modified technique |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111564362A (en) * | 2020-06-12 | 2020-08-21 | 武汉新芯集成电路制造有限公司 | Wafer edge processing method |
| CN111564362B (en) * | 2020-06-12 | 2023-06-09 | 武汉新芯集成电路制造有限公司 | Wafer edge processing method |
| CN115070515A (en) * | 2022-06-20 | 2022-09-20 | 长春长光圆辰微电子技术有限公司 | Method for reducing CMP large area edge peeling in GOI production |
| CN115579282A (en) * | 2022-11-04 | 2023-01-06 | 湖北三维半导体集成创新中心有限责任公司 | Method for processing wafer |
| CN115579282B (en) * | 2022-11-04 | 2024-03-22 | 湖北三维半导体集成创新中心有限责任公司 | Wafer processing method |
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Application publication date: 20180904 |