CN108490344B - Analog circuit fault diagnosis method based on training sample optimization - Google Patents
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Abstract
The invention discloses an analog circuit fault diagnosis method based on training sample optimization, which comprises the steps of firstly, carrying out parameter scanning on each fault element in an analog circuit, and forming a real part and an imaginary part of output voltage of a measuring point into a vector to obtain an output voltage set; then, for the output voltage set obtained by each fault element, an output voltage scatter diagram is obtained by drawing in a plurality of domains, the intersection areas of the output voltage scatter diagrams of the fault elements are obtained in pairs, the output voltage data points positioned in the intersection areas are the output voltage intersection points of the two fault elements, and the output voltage data points are deleted in the respective output voltage sets; taking the processed output voltage set of each fault element as input and the serial number of the fault element as output, and training a preset classification model to obtain a fault classifier; when the analog circuit breaks down, the output voltage vector of the measuring point is obtained and input into a fault classifier to obtain a fault diagnosis result. The invention can effectively improve the accuracy of fault diagnosis.
Description
Technical Field
The invention belongs to the technical field of analog circuit fault diagnosis, and particularly relates to an analog circuit fault diagnosis method based on training sample optimization.
Background
Under the fault state of the analog circuit, the output voltage of the measuring point can be monitored to deviate from the value in the normal working state, and under the fault state, the test data of the output voltage can be acquired from the measuring point, so that the fault of the analog circuit can be diagnosed according to the output voltage of the measuring point.
In the document "Yang C, Tians, Liu Z, et al. fat Modeling on compact plate and method for Analog Circuits [ J].IEEE Transactions onInstrumentation&Measurement,2013,62(10):2730-2738.”The method comprises the steps that a single device is subjected to parameter scanning by the analog circuit under the condition of effective sinusoidal excitation, and voltage quantity obtained by circuit measuring points forms a circle or a line segment in a complex plane with a real part and an imaginary part as coordinates. Meanwhile, an implicit function equation f (U) satisfied by a real part and an imaginary part of circuit output is provided in an analytic mode through circuit analysisor,Uoj) 0. Obtaining such implicit functions is generally difficult, but can often be expressed by simulation or curve fitting.
The source of analog circuit fault diagnosis tolerances is generated by the circuit design process. The nominal value (design value) of a parameter of a faulty component in an analog circuit is known, but the actual value of a particular circuit varies randomly from and to its nominal value, which is generally not exactly equal to its nominal value, so that a floating range of component parameters is given at the beginning of the circuit design, which is called the tolerance of the device. The circuit with tolerance can affect the fault diagnosis of the circuit, and the isolation rate of the fault diagnosis is reduced.
Disclosure of Invention
The invention aims to overcome the defects of the prior art and provides a training sample optimization-based analog circuit fault diagnosis method, which is used for processing a fault element output voltage set obtained through parameter scanning, deleting output voltage intersection points among fault elements and training a fault classifier by using the optimized output voltage set as a training sample so as to improve the fault diagnosis accuracy.
In order to achieve the above object, the method for diagnosing the fault of the analog circuit based on the training sample optimization of the present invention comprises the following steps:
s1: recording the number of fault elements in the analog circuit as M, sequentially selecting each fault element to perform parameter scanning, wherein the parameter scanning range of the mth fault element is
M is 1,2, …, M, the parameter scanning range is determined according to the actual requirement, the other fault components take random values in the tolerance range,carrying out Monte Carlo simulation for a plurality of times during each parameter scanning to obtain the output voltage of the measuring point t; recording the output voltage u obtained from the m-th faulty elementmn＝αmn+jβmn，αmn、βmnRespectively represent the output voltage umnJ is an imaginary unit, N is 1,2, …, Nm，NmRepresenting the quantity of output voltage obtained by parameter scanning of the mth fault element, forming a real part and an imaginary part of the output voltage into a vector to obtain an output voltage set U of each fault elementm＝[Um1,Um2,…,UmNm]Wherein U ismn＝[αmn,βmn]；
S2: for the output voltage obtained by each fault element, an output voltage scatter diagram is obtained by drawing in a complex domain; two fault element output voltage scatter diagrams are obtained, output voltage data points in the intersection areas are output voltage intersection points of two fault elements, the output voltage intersection points are deleted from the output voltage sets, and the output voltage set of the m-th fault element after processing is recorded as U'm；
S3: collecting output voltage of m-th fault element U'mTaking a vector of each output voltage as input, taking a corresponding fault element serial number m as output, and training a preset classification model to obtain a fault classifier;
s4: when the analog circuit is in fault, the same excitation during parameter scanning is used as the input of the analog circuit to obtain the output voltage u of the measuring point tf＝αf+jβfWill vector [ α ]f,βf]The fault classifier obtained in step S3 is input, and the classification result output by the fault classifier is the fault diagnosis result.
The invention relates to an analog circuit fault diagnosis method based on training sample optimization, which comprises the steps of firstly, carrying out parameter scanning on each fault element in an analog circuit, and forming a real part and an imaginary part of output voltage of a measuring point into a vector to obtain an output voltage set; then, for the output voltage set obtained by each fault element, an output voltage scatter diagram is obtained by drawing in a plurality of domains, the intersection areas of the output voltage scatter diagrams of the fault elements are obtained in pairs, the output voltage data points positioned in the intersection areas are the output voltage intersection points of the two fault elements, and the output voltage data points are deleted in the respective output voltage sets; taking the processed output voltage set of each fault element as input and the serial number of the fault element as output, and training a preset classification model to obtain a fault classifier; when the analog circuit breaks down, the output voltage vector of the measuring point is obtained and input into a fault classifier to obtain a fault diagnosis result. According to the invention, the accuracy of fault diagnosis can be effectively improved by optimizing the training samples.
Drawings
FIG. 1 is a flow chart of an embodiment of a method for diagnosing faults of an analog circuit based on training sample optimization according to the present invention;
FIG. 2 is a circuit diagram of a second order Thomas filter circuit in the present embodiment;
FIG. 3 is an output voltage scattergram of a defective element in the present embodiment;
FIG. 4 shows the resistor R in this embodiment2And R3The output voltage scatter diagram of (1);
FIG. 5 is an enlarged view of the output voltage crossing region of FIG. 4;
FIG. 6 is a scatter plot of the intersection of the output voltages of the intersection region shown in FIG. 5 after the intersection has been deleted;
FIG. 7 shows a resistance R2Output voltage set neutralization resistor R3A map of intersection regions of the convex hull;
FIG. 8 shows a resistance R3Output voltage set neutralization resistor R2Map of intersection regions of convex hulls.
Detailed Description
The following description of the embodiments of the present invention is provided in order to better understand the present invention for those skilled in the art with reference to the accompanying drawings. It is to be expressly noted that in the following description, a detailed description of known functions and designs will be omitted when it may obscure the subject matter of the present invention.
Examples
FIG. 1 is a flowchart of an embodiment of a method for diagnosing a fault of an analog circuit based on training sample optimization according to the present invention. As shown in fig. 1, the method for diagnosing the fault of the analog circuit based on the training sample optimization of the present invention specifically includes the following steps:
s101: scanning parameters:
recording the number of fault elements in the analog circuit as M, sequentially selecting each fault element to perform parameter scanning, wherein the parameter scanning range of the mth fault element is
M is 1,2, …, M, the parameter scanning range is determined according to the actual requirement, obviously
pmIndicating the nominal value of the m-th failed element, the parameter sweep range of the m-th failed element
It needs to be larger than the tolerance range, and the other fault components take random values in the tolerance range. And carrying out Monte Carlo simulation for a plurality of times during each parameter scanning to obtain the output voltage of the measuring point t. Recording the output voltage u obtained by the m-th fault elementmn＝αmn+jβmn，αmn、βmnRespectively represent the output voltage umnJ is an imaginary unit, N is 1,2, …, Nm，NmRepresenting the quantity of output voltage obtained by parameter scanning of the mth fault element, forming a real part and an imaginary part of the output voltage into a vector to obtain an output voltage set U of each fault elementm＝[Um1,Um2,…,UmNm]Wherein U ismn＝[αmn,βmn]。
Due to the tolerance of the components of the analog circuit, when a faulty component fails, the specific values of the parameters of other faulty components cannot be guaranteed, and only the other faulty components are known to float around their respective nominal values, i.e. to change within the tolerance range. Experience has shown that the tolerance range for resistive devices is 5% and the tolerance range for capacitive devices is 10%. Therefore, when the parameter scanning is carried out on the fault element, other fault elements take values randomly within the tolerance range.
Due to tolerances, when two or more devices are modeled in the same complex plane, a large intersection area occurs, so that it is not possible to determine to which device a data point in this area belongs when performing fault diagnosis. If all fault data are directly adopted to train the fault classifier, the fault isolation rate of the fault classifier is reduced, so that the fault diagnosis accuracy is reduced, and therefore training samples need to be optimized, and data in the output voltage intersection area are deleted.
S102: optimizing a training sample:
and for the output voltage obtained by each fault element, an output voltage scatter diagram is obtained by drawing in a complex domain. Then, intersection areas of the output voltage scatter diagrams of the fault elements are obtained in pairs, output voltage data points in the intersection areas are output voltage intersection points of the two fault elements, output voltage intersection points are deleted from the output voltage sets, and the output voltage set of the m-th fault element after processing is recorded as U'm。
The invention provides two methods for deleting the intersection point of the output voltage, namely a curved quadrilateral method and a convex hull method, and the two methods are specifically explained below.
● curved quadrilateral method
Through research, four outermost intersection points, which are respectively marked as A, B, C, D, exist in the intersection area of the output voltage scatter diagram of the two fault elements in the complex number domain. The intersection region where the intersection points of the output voltages to be deleted are located may be A, B, C, D curved quadrilateral regions connected by four outermost intersection points, which are represented approximately by A, B, C, D quadrilateral regions connected in sequence in this embodiment. Based on the above analysis, a specific method for deleting the intersection point of the output voltage by using the curved quadrilateral method can be obtained as follows:
and (3) calculating coordinates of A, B, C, D of four outermost intersections of intersection areas of the two fault element output voltage scatter diagrams, forming a quadrilateral area by using A, B, C, D as a vertex, calculating an edge equation of the quadrilateral area, and respectively judging whether each output voltage in the two fault element output voltage sets is located in the quadrilateral area, if so, the output voltage is the intersection point and is deleted from the corresponding output voltage set, otherwise, no operation is performed.
● convex hull method
The geometry of the convex hull is defined as: in a real vector space V, for a given set X, the intersection S of all convex sets containing X is taken to be the convex hull of X. With respect to finding the output voltage intersection to which the present invention is directed, the problem translates into finding the convex hull intersection of the two sets of data points. In order to realize the aim, the plane coefficients of two convex hulls are used for geometric calculation, so that the intersection point of output voltages is obtained and deleted, and the specific method comprises the following steps:
recording the output voltage set of two fault elements as UmAnd Um′First, obtain UmIn this embodiment, the convhull _ nd function of Matlab is used to obtain the convex hull plane coefficients. At Um' Mizhong search results in a search belonging to UmThe output voltages of the convex hulls form an output voltage intersection point set interm′. Then obtain Um′Convex hull plane coefficient of (1) in UmThe search in the Chinese language obtains the Chinese language belonging to Um′The output voltages of the convex hulls form an output voltage intersection point set interm. Collecting the output voltage intersection points to intermThe vector in (1) drives it from UmDeleting, and collecting the output voltage intersection points to interm′Vector in (1) is from Um′Is deleted.
S103: training a fault classifier:
collecting output voltage of m-th fault element U'mThe vector of each output voltage is used as input, the corresponding fault element serial number m is used as output, and a preset classification model is trained to obtain a fault classifier.
S104: fault diagnosis:
when the analog circuit is in fault, the same excitation during parameter scanning is used as the input of the analog circuit to obtain the output voltage u of the measuring point tf＝αf+jβfWill vector [ α ]f,βf]Inputting the fault classifier obtained in step S103, and the classification result output by the fault classifier is the fault diagnosis result.
In order to better illustrate the technical effects of the present invention, a specific second-order thomas filter circuit is used as an example to illustrate the specific implementation process of the present invention. Fig. 2 is a circuit diagram of a second-order thomas filter circuit in the present embodiment. As shown in FIG. 2, in this embodiment, the frequency of the circuit excitation signal is set to 902Hz, the output point of the last stage amplifier is selected as the measuring point t, and the resistor R is used1,R2,R3,R4,R5,R6As a faulty element in the present embodiment. Firstly, the resistor R is obtained through simulation1,R2,R3,R4,R5,R6And then drawing the fault data in the complex domain to obtain an output voltage scatter diagram. Fig. 3 is an output voltage scatter diagram of a defective element in the present embodiment. As shown in FIG. 3, the resistor R in this embodiment1The effect on the output of the measuring point is linear, so that the output voltage scatter diagram is a line segment overall, and the other 5 resistors R2,R3,R4,R5,R6The output voltage scatter diagram is an arc, and the resistance R is4,R5,R6Belonging to a fuzzy group, so that the output voltage scatter diagram is relatively approximate.
For simplicity of description, only the resistor R is selected in this embodiment2And R3For example, a specific process of deleting the output voltage intersection and fault diagnosis will be described. FIG. 4 shows the resistor R in this embodiment2And R3The output voltage scatter diagram of (1). As shown in fig. 4, the output voltage has a sample capacity of 21000 samples, and there is a "fuzzy region" where a part of the samples intersect, and when a circuit fails, if a vector formed by a real part and an imaginary part of the output voltage obtained at a measurement point is in the "fuzzy region", it is impossible to know which element has failed, which affects the accuracy of fault diagnosis. Selecting SVM (Support Vector Machine) as a classification model, using all fault data in FIG. 4 as input, and setting a resistor R2The corresponding labels are 1,Resistance R3And (5) training the SVM to obtain a fault classifier, wherein the corresponding label is 0. Then several resistors R are generated2Or resistance R3The real part and the imaginary part of the fault output voltage at the measuring point t are solved to obtain a corresponding vector which is input to the fault classifier, and the accuracy of the diagnosis result obtained through statistics is 93%.
The resistor R is then deleted by the method of the invention2And R3And (4) at the intersection point of the output voltages, retraining the SVM.
Firstly, a curved quadrilateral method is adopted. Fig. 5 is an enlarged view of the output voltage crossing region of fig. 4. As shown in FIG. 5, there are four outermost intersections A, B, C, D in the output voltage intersection region, where point A is referenced as (x)1,y1) The coordinate of the point B is (x)2,y2) And the coordinate of the point C is (x)3,y3) D point coordinate is (x)4,y4) The edge equations of the four sides AB, AC, DC and DB are respectively obtained as follows:
when the output voltages in the two sets of output voltages of the fault elements meet the following condition, namely the intersection point of the output voltages is:
fig. 6 is a scatter diagram in which the output voltage intersection points in the intersection area shown in fig. 5 are deleted. Resistance R after training sample optimization by adopting curved quadrilateral method2And R3Is used as input, a resistor R is arranged2The corresponding label is 1, the resistance R3And (5) training the SVM to obtain a fault classifier, wherein the corresponding label is 0. Then several resistors R are generated2Or resistance R3And (3) performing real part and virtual part solution on the fault output voltage to obtain a corresponding vector, inputting the vector into a fault classifier, and counting to obtain that the accuracy of a diagnosis result is 99.3% (8639/8700), which is obviously higher than 93% of the accuracy of the training sample before optimization.
Then convex hull method is adopted. FIG. 7 shows a resistance R2Output voltage set neutralization resistor R3Map of intersection regions of convex hulls. As shown in FIG. 7, the gray curve is the resistance R3The convex hull of the output voltage set, and the gray data point in the convex hull is the resistance R2Output voltage set neutralization resistor R3Data points in the intersection region of the convex hull, i.e., points that need to be deleted.
FIG. 8 shows a resistance R3Output voltage set neutralization resistor R2Map of intersection regions of convex hulls. As shown in FIG. 8, the gray curve is the resistance R2The convex hull of the output voltage set, and the gray data point in the convex hull is the resistance R3Output voltage set neutralization resistor R2Data points in the intersection region of the convex hull, i.e., points that need to be deleted.
Resistance R after training sample optimization by convex hull method2And R3Is used as input, a resistor R is arranged2The corresponding label is 1, the resistance R3And (5) training the SVM to obtain a fault classifier, wherein the corresponding label is 0. Then several resistors R are generated2Or resistance R3And (3) performing real part and virtual part solution on the fault output voltage to obtain a corresponding vector, inputting the vector into a fault classifier, and counting to obtain that the accuracy of the diagnosis result is 100% (8498/8498), which is obviously higher than 93% of the accuracy of the training sample before optimization.
In conclusion, by optimizing the training samples, the influence caused by the element tolerance problem can be effectively reduced, and the accuracy of fault diagnosis is improved.
Although illustrative embodiments of the present invention have been described above to facilitate the understanding of the present invention by those skilled in the art, it should be understood that the present invention is not limited to the scope of the embodiments, and various changes may be made apparent to those skilled in the art as long as they are within the spirit and scope of the present invention as defined and defined by the appended claims, and all matters of the invention which utilize the inventive concepts are protected.
Claims (3)
1. A fault diagnosis method of an analog circuit based on training sample optimization is characterized by comprising the following steps:
s1: recording the number of fault elements in the analog circuit as M, sequentially selecting each fault element to perform parameter scanning, wherein the parameter scanning range of the mth fault element is
The parameter scanning range is determined according to actual needs, other fault elements take values randomly within a tolerance range, and Monte Carlo simulation is performed for a plurality of times during each parameter scanning to obtain the output voltage of the measuring point t; recording the output voltage u obtained from the m-th faulty elementmn＝αmn+jβmn，αmn、βmnRespectively representing output voltage UmnJ is an imaginary unit, N is 1,2, …, Nm，NmRepresenting the quantity of output voltage obtained by parameter scanning of the mth fault element, forming a real part and an imaginary part of the output voltage into a vector to obtain an output voltage set of each fault element
Wherein U ismn＝[αmn,βmn]；
S2: for the output voltage obtained by each fault element, an output voltage scatter diagram is obtained by drawing in a complex domain; two fault element output voltage scatter diagrams are obtained, output voltage data points in the intersection areas are output voltage intersection points of two fault elements, the output voltage intersection points are deleted from the output voltage sets, and the output voltage set of the m-th fault element after processing is recorded as U'm；
S3: collecting output voltage of m-th fault element U'mTaking a vector of each output voltage as input, taking a corresponding fault element serial number m as output, and training a preset classification model to obtain a fault classifier;
s4: when analog circuit is in failure, the same excitation in parameter scanning is used asThe input of the analog circuit is used for obtaining the output voltage u of the measuring point tf＝αf+jβfWill vector [ α ]f,βf]The fault classifier obtained in step S3 is input, and the classification result output by the fault classifier is the fault diagnosis result.
2. The analog circuit fault diagnosis method according to claim 1, wherein the determination of the intersection point of the output voltages in step S2 is performed by a curved quadrilateral method, which comprises: and (3) calculating coordinates of A, B, C, D of four outermost intersections of intersection areas of the two fault element output voltage scatter diagrams, forming a quadrilateral area by using A, B, C, D as a vertex, calculating an edge equation of the quadrilateral area, and respectively judging whether each output voltage in the two fault element output voltage sets is located in the quadrilateral area, if so, the output voltage is the intersection point and is deleted from the corresponding output voltage set, otherwise, no operation is performed.
3. The analog circuit fault diagnosis method according to claim 1, wherein the determination of the intersection point of the output voltages in step S2 is performed by a convex hull method, specifically: recording the output voltage set of two fault elements as UmAnd Um′First, obtain UmConvex hull plane coefficient of (1) in Um′The search in the Chinese language obtains the Chinese language belonging to UmThe output voltages of the convex hulls form an output voltage intersection point set interm′(ii) a Then obtain Um′Convex hull plane coefficient of (1) in UmThe search in the Chinese language obtains the Chinese language belonging to Um′The output voltages of the convex hulls form an output voltage intersection point set interm(ii) a Collecting the output voltage intersection points to intermThe vector in (1) drives it from UmDeleting, and collecting the output voltage intersection points to interm′Vector in (1) is from Um′Is deleted.
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