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CN108346628B - Power module and manufacturing method thereof - Google Patents

Power module and manufacturing method thereof Download PDF

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Publication number
CN108346628B
CN108346628B CN201710063328.1A CN201710063328A CN108346628B CN 108346628 B CN108346628 B CN 108346628B CN 201710063328 A CN201710063328 A CN 201710063328A CN 108346628 B CN108346628 B CN 108346628B
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Prior art keywords
power
layer
insulating
terminal
conductive layer
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CN201710063328.1A
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CN108346628A (en
Inventor
李慧
杨胜松
廖雯祺
杨钦耀
李艳
张建利
曾秋莲
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BYD Semiconductor Co Ltd
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BYD Semiconductor Co Ltd
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Priority to CN201710063328.1A priority Critical patent/CN108346628B/en
Priority to PCT/CN2018/073367 priority patent/WO2018137559A1/en
Publication of CN108346628A publication Critical patent/CN108346628A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H01L23/3677—Wire-like or pin-like cooling fins or heat sinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/24137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/24221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/24225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

The invention provides a power module and a manufacturing method thereof, wherein the power module comprises: the insulating medium substrate is provided with a first conducting layer on the upper surface and a heat conducting path reaching the first conducting layer from the lower surface; the power semiconductor chip is attached to the upper surface of the insulating medium substrate; the insulating layer covers the insulating medium substrate and covers the chip, a through hole positioned above the chip is formed in the insulating layer, and a conductive substance is filled in the through hole; and the second conducting layer is arranged on the insulating layer and is electrically connected with the chip through the conducting substance. The packaging does not need to open a plastic packaging mold, so that the production cost is saved; in addition, the power semiconductor chip is electrically connected with the upper conductive layer by arranging the through hole on the insulating layer and filling the conductive substance, so that the size of the module is reduced, and the miniaturization of the module is facilitated.

Description

Power module and manufacturing method thereof
Technical Field
The present invention relates to the field of hybrid integrated circuits, and more particularly, to a power module and a method for manufacturing the same.
Background
The power semiconductor module is a device for packaging a plurality of semiconductor chips together according to a certain circuit structure. In an IGBT (Insulated Gate Bipolar Transistor) module, the IGBT chip and the diode chip are integrated on a common base plate, and the power devices of the module are Insulated from their mounting surfaces (i.e., heat sinks).
The traditional plastic package molding of the power semiconductor module needs die sinking, so that the cost is high; in addition, the power semiconductor module comprises an electric switching block for supporting, and the module is large in size and small in integration level.
Disclosure of Invention
The invention aims to provide a power module and a manufacturing method thereof, and aims to solve the problems that a traditional power semiconductor module needs to be opened, comprises an electric switching block for supporting and has a large module volume.
The present invention provides a power module, comprising:
the upper surface of the insulating medium substrate is provided with a first patterned conducting layer, and the insulating medium substrate is provided with a heat conducting path reaching the first conducting layer from the lower surface;
the power semiconductor chip is attached to the upper surface of the insulating medium substrate and is electrically connected with the first conductive layer;
the insulating layer covers the insulating medium substrate and covers the power semiconductor chip, the insulating layer is provided with a first through hole penetrating through the upper surface and the lower surface of the insulating layer, and the through hole is filled with a conductive substance electrically connected with the power semiconductor chip;
and the patterned second conducting layer is arranged on the insulating layer, and the second conducting layer is used for connecting the power semiconductor chip circuit through the conducting substance and the first conducting layer.
The invention also provides a manufacturing method of the power module, which comprises the following steps:
arranging an insulating medium substrate with a first conducting layer on the upper surface, and arranging a heat conducting path reaching the first conducting layer from the lower surface;
arranging at least one power semiconductor chip on the first conductive layer to be electrically connected with the first conductive layer;
arranging an insulating layer on the insulating medium substrate, and coating the power semiconductor chip;
and arranging a second conducting layer on the insulating layer, forming a through hole penetrating through the insulating layer and the second conducting layer, and filling a conducting substance in the through hole to ensure that the second conducting layer connects the power semiconductor chip circuit through the conducting substance and the first conducting layer.
The power module and the manufacturing method thereof have the advantages that the module package does not need to be carried out by a plastic package mold, so that the production cost is saved; a heat conduction path is arranged on the insulating medium substrate, so that the heat dissipation performance is improved; in addition, the power semiconductor chip is electrically connected with the upper conductive layer by arranging the through hole on the insulating layer and filling the conductive substance, so that the size of the module is reduced, and the miniaturization of the module is facilitated.
Drawings
FIG. 1 is a schematic diagram of a power module according to a preferred embodiment of the present invention;
FIG. 2 is a schematic structural diagram of a power module according to an embodiment of the present invention;
FIG. 3 is a diagrammatic illustration of the overall layout of the power module shown in FIG. 2;
FIG. 4 is a circuit schematic of a half-bridge drive circuit;
FIG. 5 is a schematic structural diagram of a power module according to another embodiment of the present invention;
FIG. 6 is a diagrammatic illustration of the overall layout of the power module shown in FIG. 5;
FIG. 7 is a schematic structural diagram of a heat dissipating plate according to an embodiment of the present invention;
FIG. 8 is a flow chart of a method for manufacturing a power module according to a preferred embodiment of the invention.
Detailed Description
In order to make the technical problems, technical solutions and advantageous effects to be solved by the present invention more clearly understood, the present invention is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
Referring to fig. 1, the power module in the preferred embodiment of the invention includes an insulating dielectric substrate 10, at least one power semiconductor chip 20, an insulating layer 40 and a second conductive layer 50.
The insulating medium substrate 10 has upper and lower surfaces oppositely arranged, wherein at least one surface is coated with metal, and the middle layer is an insulating medium layer 11. In this embodiment, the insulating dielectric substrate 10 is coated with metal on the upper surface to form a patterned first conductive layer 12, and the lower surface may be coated with metal to form another patterned conductive layer 13, or a heat dissipation fin may be directly disposed.
When the insulating medium substrate 10 uses a PCB (printed circuit board), the insulating medium layer 11 (resin layer) of the PCB has too poor heat conductivity. Therefore, in the present embodiment, a heat conduction path is opened from the lower surface to the first conductive layer 12 in the insulating dielectric substrate 10. The insulating dielectric substrate 10 is provided with an opening 14 reaching or penetrating the first conductive layer 12 from the lower surface (i.e., the conductive layer 13), and the opening 14 is filled with an insulating and heat-conducting material to improve the heat dissipation capability of the lower surface of the power module. It is to be understood that the manner of improving the heat dissipation capability is not limited to the case of using a PCB as the insulating dielectric substrate 10, or any other case of using a metal-clad insulating dielectric substrate.
The power semiconductor chip 20 in this embodiment includes an IGBT (fast recovery diode) and an FRD (fast recovery diode), and constitutes a drive circuit. The power semiconductor chip 20 has polarity pins on both the upper and lower surfaces thereof, and in this embodiment, when the power semiconductor chip 20 is an IGBT, the upper surface has two polarity pins, which are a gate and an emitter, respectively, and the lower surface has a collector. When the power semiconductor chip 20 is FRD, the upper surface has an anode and the lower surface has a cathode, or vice versa.
The power semiconductor chip 20 is attached to the upper surface of the insulating dielectric substrate 10 and electrically connected to the first conductive layer 12. Specifically, when a circuit pattern is formed on the first conductive layer 12 and the power semiconductor chip 20 is attached to the circuit pattern by soldering or pressure bonding, the polarity pins on the lower surface thereof are connected to the corresponding circuit pattern forming circuit to be led out.
The insulating layer 40 covers the insulating dielectric substrate 10 to cover the power semiconductor chip 20 therein, and the insulating layer 40 covers the insulating dielectric substrate 10 in a laminating manner. Specifically, in the product, the lower surface of the insulating layer 40 is provided with a groove for accommodating the power semiconductor chip 20. A plurality of through holes 42 penetrating through the upper and lower surfaces of the insulating layer 40 are formed at predetermined positions of the insulating layer 40, the plurality of through holes 42 respectively reach the power semiconductor chip 20 and the second conductive layer 50 through the insulating layer 40, and conductive materials electrically connected with the power semiconductor chip 20 and the second conductive layer 50 are filled in the through holes 42. Preferably, the vias 42 of the same circuit connection path are arranged as many as possible while ensuring the reliability of the bonding between the metalized vias 42 and the chip, so as to ensure the overcurrent capability of the circuit and improve the heat dissipation capability of the upper portion of the chip.
In the manufacturing process, in the present embodiment, the insulating layer 40 is formed by heating and curing a prepreg (Pre-pregnant), and the conductive material in the through hole 42 is metalized while heating; the prepreg mainly comprises resin and a reinforcing material, the reinforcing material can be glass fiber cloth, paper base, composite materials and the like, the thermal expansion coefficient of the prepreg is matched with that of the power semiconductor chip 20, and the failure problem caused by overlarge stress on the device due to the fact that the thermal expansion coefficient of the power device is not matched with that of the packaging material is avoided.
The second conductive layer 50 is disposed on the insulating layer 40, specifically, stacked on the insulating layer 40 by lamination. The second conductive layer 50 electrically connects the power semiconductor chip 20 to the first conductive layer 12 via the conductive material and the power semiconductor chip 20.
In this embodiment, a circuit pattern is formed on the second conductive layer 50, and the polarity pins on the upper surface of the power semiconductor chip 20 are electrically connected to the corresponding circuit pattern for leading out. In this way, the power semiconductor chip 20 is electrically connected to the second conductive layer 50 through the metalized through hole 42 formed in the insulating layer 40, and the electrical connection is realized by replacing an electrical switching block, so that the size of the module is reduced, and the module is miniaturized.
In this embodiment, the second conductive layer 50 is a conductive metal sheet, and may be made of a copper sheet, an aluminum sheet, or other conductive metal materials. In other embodiments, the second conductive layer 50 may be formed by metal coating the lower surface of another insulating dielectric substrate. The other insulating dielectric substrate has upper and lower surfaces disposed opposite to each other, wherein at least one of the upper and lower surfaces is coated with metal to form the second conductive layer 50. The upper surface can be coated with metal to form another conductive layer, and can also be provided with radiating fins.
Referring to fig. 2 and 3, in one embodiment, the power semiconductor chip 20 includes an IGBT21 and an FRD 22. The power module comprises an outgoing terminal 60 (i.e. a power module pin), one end of the outgoing terminal 60 is fixedly and electrically connected with the first conductive layer 12 or the second conductive layer 50, and is electrically connected to the corresponding polarity pins of the IGBT21 and the FRD 22 by matching with the conductive substance in the through hole 42, and the other end of the outgoing terminal 60 extends outwards. The lead-out terminal 60 is used to lead out the IGBT21 and the FRD 22 as a preset circuit to use the terminals of the circuit for connection with an external circuit. Lead terminal 60 may be fixed to first conductive layer 12 or may be fixed to second conductive layer 50.
In this embodiment, the lead terminal 60 is fixed to the first conductive layer 12 as an example. The lead terminal 60 includes a power terminal 61 and a control terminal 62, the power terminal 61 includes an emitter power terminal 61A and a collector power terminal 61B, the first conductive layer 12 includes a first circuit pattern 121 and a second circuit pattern 122 on opposite sides of the power module, and the first circuit pattern 121 includes an emitter pad 121A and a collector pad 121B disposed side by side on the same side of the power module. The polarity pins of the lower surfaces of the IGBT21 and FRD 22 are electrically connected to the collector pad 121B of the first circuit pattern 121, and the collector power terminal 61B is electrically connected to the collector pad 121B; the polarity pins of the upper surfaces of the IGBTs 21 and FRDs 22 are electrically connected to the emitter pads 121A and the second circuit patterns 122 of the first circuit patterns 121 through the conductive substance in the corresponding through holes 42 and the second conductive layer 50, respectively, and the control terminals 62 and the emitter power terminals 61 are soldered to the second circuit patterns 122 and the emitter pads 121A of the first circuit patterns 121, respectively. It is understood that the second circuit pattern 122 is also a pin pad.
More specifically, the second conductive layer 50 includes a third circuit pattern 51 and a fourth circuit pattern 52, and the first circuit pattern 121 is connected to the polarity pins of the upper surfaces of the IGBT21 and the FRD 22 through the conductive substance in the corresponding through hole 42 and the third circuit pattern 51. The second circuit pattern 122 is connected to the polarity pin of the upper surface of the IGBT21 through the corresponding conductive substance in the via hole 42 and the fourth circuit pattern 52. In the present embodiment, the IGBT21 is electrically connected to the first circuit pattern 121 by an emitter, electrically connected to the second circuit pattern 122 by a gate, and electrically connected to the intermediate circuit pattern 123 by a collector.
Fig. 3 is a schematic diagram of the overall layout of the power module in the present embodiment. The filled regions are shown as being patterned generally for the first conductive layer 12, and the wire frame black regions are shown as being patterned generally for the second conductive layer 50. The IGBT21 and FRD 22 are soldered at locations corresponding to the first conductive layer 12, and the control terminal 62 and power terminal 61 are also soldered at locations corresponding to the first conductive layer 12, so that the chip polarity is electrically connected to the corresponding terminals via the metallized through holes 42. Control terminal 62 and power terminal 61 are located the module both sides respectively, and the high-voltage power end is kept away from to the low-voltage control end, has reduced the electric interference of high-voltage terminal to the low-voltage end, has improved the reliability of control end.
Referring to fig. 4 to 6, in another embodiment, each pair of power semiconductor chips 20 includes at least one pair of power semiconductor chips 20, each power semiconductor chip 20 forms a bridge arm, and the second conductive layer 50 connects each two pairs of the power semiconductor chips 20 to form the half-bridge power module 1 through the conductive material and the first conductive layer 12. The upper bridge arm comprises an upper bridge IGBT 101 and an upper bridge FRD 103, and the lower bridge arm comprises a lower bridge IGBT 102 and a lower bridge FRD 104. Taking the power semiconductor chip 20 of the bridge arm as an example, the IGBT chip 101 has polarity pins on both the upper and lower surfaces thereof, and in this embodiment, the IGBT chip 101 has two polarity pins on the upper surface thereof, which are a gate and an emitter, respectively, and a collector on the lower surface thereof. The upper bridge FRD chip 103 has an anode on the upper surface and a cathode on the lower surface. As does the power semiconductor chip 20 of the lower arm.
In this embodiment, the lead terminal is fixed to the first conductive layer 12 as an example. The leading terminal includes a control terminal 32 and a power terminal 31, in this embodiment, the control terminal 32 includes a first control terminal 321 and a second control terminal 322 for controlling the upper and lower arms, respectively, and the power terminal 31 includes a positive power terminal 311, an ac power terminal 312, and a negative power terminal 313. The first conductive layer 12 includes a first circuit pattern 121 and a second circuit pattern 122 at opposite sides of the half-bridge power module. The polarity pins of the power semiconductor chip 20 are electrically connected to the first and second circuit patterns 121 and 122, respectively, through the conductive material in the corresponding through holes 42 and the second conductive layer 50, respectively, and the control terminal 32 and the power terminal 31 are fixedly electrically connected to the first and second circuit patterns 121 and 122, respectively. It is understood that the first and second circuit patterns 121 and 122 are pin pads.
Specifically, the first circuit pattern 121 includes three pin pads 121A, 121B, and 121C respectively soldered to the positive power terminal 311, the ac power terminal 312, and the negative power terminal 313, and in this embodiment, the three pin pads 121A, 121B, and 121C are disposed side by side on the same side of the half-bridge power module. Referring to fig. 4, the second circuit pattern 122 includes lead pads 122A and 122B respectively connected to the first control terminal 321 and the second control terminal 322, and the lead pads 122A and 122B are disposed on the other side of the half-bridge power module opposite to the first circuit pattern 121.
More specifically, the second conductive layer 50 includes a third circuit pattern 51 and a fourth circuit pattern 52, and the third circuit pattern 51 and the fourth circuit pattern 52 are used to electrically connect the conductive substance in the polar-pin-fitting corresponding through hole 42 of the power semiconductor chip 20 to the first circuit pattern 121 and the second circuit pattern 122, respectively.
Fig. 6 is a diagram illustrating the overall layout of the power module in the present embodiment. The filled regions are shown as being patterned generally for the first conductive layer 12, and the wire frame black regions are shown as being patterned generally for the second conductive layer 50. The components of the half-bridge driving circuit are soldered to the first conductive layer 12, the control terminal 32 and the power terminal 31 are also soldered to the first conductive layer 12, and the polarity of the chip is electrically connected to the corresponding terminals through the metallized through holes 42. The control terminal 32 and the power terminal 31 are respectively located at two sides of the module, and the low-voltage control end is far away from the high-voltage power end, so that the electrical interference of the high-voltage end to the low-voltage end is reduced, and the reliability of the control end is improved.
In addition, in a preferred embodiment, referring to fig. 2, 5 and 7, the power module further includes a heat sink 70, and the heat sink 70 is disposed on the lower surface of the insulating dielectric substrate 10 and/or the upper surface of the second conductive layer 50. The heat sink 70 may be separately disposed on the lower surface of the power module to contact the insulating and heat conducting material in the opening 14, or disposed on the upper and lower surfaces of the power module to achieve double-sided heat dissipation. Specifically, the lower surface of the insulating dielectric substrate 10 and/or the upper surface of the second conductive layer 50 are connected to the heat sink 70 through the insulating thermal conductive paste 80. The heat sink 70 is a fin or a flat heat pipe. FIG. 7 is a schematic view of a flat plate heat pipe. The heat generated by the power semiconductor chip 20 is conducted to the evaporation surface 71 of the heat pipe, and the working fluid 72 in the capillary tube absorbs the heat to be vaporized and fills the vapor cavity. The condensation surface 73 of the flat heat pipe 70 is cooled with a circulating coolant. The vapor 90 is condensed into liquid again on the condensing surface 73, and the liquid flows back to the evaporating surface 71 again under the action of the capillary force of the capillary wick 74, and the steps are repeated to realize circulation heat dissipation.
In addition, please refer to fig. 2, 3, 7 and 8, further disclose a manufacturing method for manufacturing the power module, which includes the following steps:
step S110 is to provide an insulating dielectric substrate 10 having a first conductive layer 12 on an upper surface thereof, and to provide a heat conduction path from a lower surface to the first conductive layer.
In this step, the insulating dielectric substrate 10 is provided with upper and lower surfaces disposed oppositely, wherein at least one surface is coated with metal. In this embodiment, the upper surface of the insulating dielectric substrate 10 is coated with metal to form a patterned first conductive layer 12, and the lower surface may be coated with metal to form another conductive layer, or may be provided with heat dissipation fins; and, a corresponding circuit pattern should be preset on the first conductive layer 12.
When the insulating dielectric substrate 10 uses a PCB, the thermal conductivity of the resin layer of the PCB is too poor. Therefore, in the present embodiment, a heat conduction path is opened from the lower surface to the first conductive layer 12 in the insulating dielectric substrate 10. The insulating dielectric substrate 10 is provided with an opening 14 reaching or penetrating the first conductive layer 12 from the lower surface (i.e., the conductive layer 13), and the opening 14 is filled with an insulating and heat-conducting material to improve the heat dissipation capability of the lower surface of the power module. It is to be understood that the manner of improving the heat dissipation capability is not limited to the case of using a PCB as the insulating dielectric substrate 10, or any other case of using a metal-clad insulating dielectric substrate.
Step S120 is to provide a power semiconductor chip 20 on the first conductive layer 12, and to form an electrical connection with the first conductive layer 12.
Specifically, the power semiconductor chip 20 includes an IGBT and/or an FRD constituting a drive circuit. The upper surface and the lower surface of the chip are both provided with polar pins, and the power semiconductor chip 20 is attached to the upper surface of the insulating medium substrate 10 and is electrically connected with the first conductive layer 12. Specifically, when the power semiconductor chip 20 is attached to the circuit pattern of the first conductive layer 12 by soldering or pressure welding, the polarity pins on the lower surface thereof are electrically connected to the corresponding circuit pattern forming circuit to be led out.
In step S130, an insulating layer 40 is disposed on the insulating dielectric substrate 10 to cover the power semiconductor chip 20.
In this embodiment, the insulating layer 40 is a prepreg, which is insulating and has a thermal expansion coefficient matched with that of the power semiconductor chip 20 as much as possible.
Step S140, a second conductive layer 50 is disposed on the insulating layer 40, a through hole 42 penetrating through the insulating layer 40 and the second conductive layer 50 is formed, and a conductive material is filled in the through hole 42, so that the second conductive layer 50 electrically connects the power semiconductor chip 20 to the first conductive layer 12 through the conductive material in the through hole 42.
Specifically, the second conductive layer 50 is preferably a conductive metal sheet. And sequentially laminating and pressing the second conductive layer 50, the prepreg and the insulating medium substrate 10 provided with the power semiconductor chip 20, so that the prepreg is filled with glue and covers the power semiconductor chip 20. A polar pin reaching the power semiconductor chip 20 and a via 42 reaching the first conductive layer 12 are made on the second conductive layer 50 and the insulating layer 40 using laser technology, and a conductive material is filled in the via 42 to metalize the via 42. The second conductive layer 50 is patterned before or after lamination, and the polar pins on the upper surface of the power semiconductor chip 20 are electrically connected to the corresponding circuit pattern forming circuit through the metalized through holes 42.
In a more specific embodiment, step S120 further includes: and a step of providing a leading terminal 60, and fixedly and electrically connecting one end of the leading terminal 60 with the first conductive layer 12, and extending the other end outwards. In another embodiment, when the patterned second conductive layer 50 is provided, a lead terminal may be provided such that one end of the lead terminal 60 is fixedly and electrically connected to the second conductive layer 50 and the other end thereof protrudes outward. The leading-out terminal comprises a control terminal 62 and a power terminal 61, and the control terminal 62 and the power terminal 61 are respectively positioned at two opposite sides of the half-bridge power module. The low-voltage control end is far away from the high-voltage power end, so that the electrical interference of the high-voltage end to the low-voltage end is reduced, and the reliability of the control end is improved.
Further, the method further comprises a step of heating, and the insulation is realized by curing the prepreg through heating.
Further, the method also comprises a step of arranging a heat radiator on the lower surface of the insulating medium substrate and/or the upper surface of the second conducting layer.
Therefore, the manufacturing method has the advantages that the power module is packaged without opening a plastic package mold during manufacturing, so that the production cost is saved; the chip is electrically connected through the metallized through hole 42, so that the size of the module is reduced, and the miniaturization of the module is facilitated.
More specifically, the manufacturing method of the power module is as follows: the power semiconductor chip 20, the control terminal 62 and the power terminal 61 are all welded on the patterned first conductive layer 12 of the insulating medium substrate 10, and the prepreg (insulating layer) 40 and the second conductive layer 50 with corresponding thicknesses are laminated with the insulating medium substrate 10 with the chip attached, so that the flowing glue of the prepreg 40 fills and covers the chip, wherein the prepreg 40 is insulating, and the thermal expansion coefficient of the prepreg is required to be matched with that of the power device as much as possible. The second conductive layer 50 of the module after lamination is patterned, and then the through holes 42 are made by using a laser technology and metallized, so that the chip polarity pins are electrically connected with the corresponding lead-out terminals 60. The through holes 42 are arranged as many as possible on the premise of ensuring the reliability of the combination between the metalized through holes 42 and the chip, so that the overcurrent capacity of the circuit is ensured and the heat dissipation capacity of the upper part of the chip is improved. The holes 14 are drilled in the lower surface of the insulating medium substrate 10 and the insulating medium layer 11 by using a laser technology, and the insulating heat conduction material is filled to improve the heat dissipation capacity of the lower surface of the chip, and this step can be performed simultaneously when the through holes 42 are formed after lamination, or can be performed when the insulating substrate 10 is prepared. The lower surface of the module (insulating medium substrate 10) is cooled by the heat sink 70, and the upper surface of the module (second conductive layer 50) is connected with another heat sink 70 to dissipate heat after being coated with the insulating heat-conducting adhesive 80, so that double-sided heat dissipation is realized, and the heat dissipation capability is improved. The two heat sinks 70 do not necessarily need to be provided at the same time, and when the heat radiation condition can be satisfied, only the heat sink 70 on the lower surface may be used alone to perform single-sided heat radiation.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents and improvements made within the spirit and principle of the present invention are intended to be included within the scope of the present invention.

Claims (10)

1. A power module, comprising:
the upper surface of the insulating medium substrate is provided with a first patterned conducting layer, and the insulating medium substrate is provided with a heat conducting path reaching the first conducting layer from the lower surface;
the power semiconductor chip is attached to the upper surface of the insulating medium substrate and is electrically connected with the first conductive layer;
the insulating layer covers the insulating medium substrate and covers the power semiconductor chip, a through hole penetrating through the upper surface and the lower surface of the insulating layer is formed in the insulating layer, and a conductive substance electrically connected with the power semiconductor chip is filled in the through hole;
a patterned second conductive layer disposed over the insulating layer, the second conductive layer electrically connecting the power semiconductor chip through the conductive material and the first conductive layer;
the leading-out terminal is fixedly connected to the first conducting layer, one end of the leading-out terminal is electrically connected with the first conducting layer, and the other end of the leading-out terminal extends outwards;
the power semiconductor chip comprises an IGBT (insulated gate bipolar transistor) and an FRD (field-programmable gate diode), the leading-out terminal comprises a control terminal and a power terminal, the control terminal and the power terminal are respectively positioned at two opposite sides of the power module, the power terminal comprises an emitter power terminal and a collector power terminal, the first conducting layer comprises a first circuit pattern and a second circuit pattern which are positioned at two opposite sides of the power module, and the first circuit pattern comprises an emitter pad and a collector pad which are arranged at the same side of the power module side by side; the polar pins on the lower surfaces of the IGBT and the FRD are electrically connected with a collector pad, and a collector power terminal is electrically connected with the collector pad; the polar pins on the upper surfaces of the IGBT and the FRD are respectively and electrically connected to the emitter pad of the first circuit pattern and the second circuit pattern through the conductive substance in the corresponding through hole and the second conductive layer; the control terminal and the emitter power terminal are respectively welded with the emitter pads of the second circuit pattern and the first circuit pattern.
2. The power module of claim 1, wherein the insulating dielectric substrate defines an opening extending from a lower surface to or through the first conductive layer, and the opening is filled with an insulating and thermally conductive material.
3. The power module of claim 1 including at least one pair of said power semiconductor chips, said second conductive layer electrically connecting each two pairs of said power semiconductor chips through said conductive substance and said first conductive layer to form a half-bridge power module.
4. The power module according to claim 1 or 2, further comprising a heat sink disposed on a lower surface of the insulating dielectric substrate and/or an upper surface of the second conductive layer.
5. The power module of claim 1 wherein the insulating dielectric substrate is a PCB board.
6. The power module of claim 1, wherein the insulating layer is a prepreg.
7. A method of manufacturing a power module, comprising the steps of:
arranging an insulating medium substrate with a first conducting layer on the upper surface, and arranging a heat conducting path reaching the first conducting layer from the lower surface;
arranging at least one power semiconductor chip on the first conductive layer to be electrically connected with the first conductive layer;
arranging an insulating layer on the insulating medium substrate, and coating the power semiconductor chip;
arranging a second conducting layer on the insulating layer, forming a through hole penetrating through the insulating layer and the second conducting layer, and filling a conducting substance in the through hole to enable the second conducting layer to connect the power semiconductor chip circuit through the conducting substance and the first conducting layer;
when at least one power semiconductor chip is arranged on the first conducting layer, an extraction terminal fixedly connected to the first conducting layer is further arranged, so that one end of the extraction terminal is electrically connected with the first conducting layer, and the other end of the extraction terminal extends outwards;
the power semiconductor chip comprises an IGBT (insulated gate bipolar transistor) and an FRD (field-programmable gate diode), the leading-out terminal comprises a control terminal and a power terminal, the control terminal and the power terminal are respectively positioned at two opposite sides of the power module, the power terminal comprises an emitter power terminal and a collector power terminal, the first conducting layer comprises a first circuit pattern and a second circuit pattern which are positioned at two opposite sides of the power module, and the first circuit pattern comprises an emitter pad and a collector pad which are arranged at the same side of the power module side by side; the polar pins on the lower surfaces of the IGBT and the FRD are electrically connected with a collector pad, and a collector power terminal is electrically connected with the collector pad; the polar pins on the upper surfaces of the IGBT and the FRD are respectively and electrically connected to the emitter pad of the first circuit pattern and the second circuit pattern through the conductive substance in the corresponding through hole and the second conductive layer; the control terminal and the emitter power terminal are respectively welded with the emitter pads of the second circuit pattern and the first circuit pattern.
8. The method according to claim 7, wherein the step of providing a heat conduction path from the lower surface to the first conductive layer comprises:
forming an opening reaching or penetrating the first conductive layer from the lower surface on the insulating medium substrate;
and the opening is filled with insulating heat conduction materials.
9. The method of manufacturing a power module according to claim 7, further comprising the step of heating; the insulating layer is a prepreg, and the prepreg is cured by heating to realize insulation.
10. The method of manufacturing a power module according to claim 7, further comprising a heat sink provided on a lower surface of the insulating dielectric substrate and/or an upper surface of the second conductive layer.
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