CN108281442A - Imaging sensor and forming method thereof - Google Patents
Imaging sensor and forming method thereof Download PDFInfo
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- CN108281442A CN108281442A CN201810069702.3A CN201810069702A CN108281442A CN 108281442 A CN108281442 A CN 108281442A CN 201810069702 A CN201810069702 A CN 201810069702A CN 108281442 A CN108281442 A CN 108281442A
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- 238000000034 method Methods 0.000 title claims abstract description 39
- 238000003384 imaging method Methods 0.000 title claims abstract description 28
- 239000000758 substrate Substances 0.000 claims abstract description 116
- 239000004065 semiconductor Substances 0.000 claims abstract description 113
- 238000002955 isolation Methods 0.000 claims abstract description 50
- 238000005530 etching Methods 0.000 claims abstract description 16
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 29
- 239000003989 dielectric material Substances 0.000 claims description 18
- 239000000377 silicon dioxide Substances 0.000 claims description 15
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 14
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 12
- 239000000463 material Substances 0.000 claims description 6
- 230000003071 parasitic effect Effects 0.000 abstract description 7
- 150000002500 ions Chemical class 0.000 description 7
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
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- 229910052681 coesite Inorganic materials 0.000 description 2
- 229910052906 cristobalite Inorganic materials 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 229910052733 gallium Inorganic materials 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 238000005286 illumination Methods 0.000 description 2
- 229910052738 indium Inorganic materials 0.000 description 2
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- 238000002161 passivation Methods 0.000 description 2
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- 229910052905 tridymite Inorganic materials 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- 230000009471 action Effects 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052787 antimony Inorganic materials 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
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- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 238000003701 mechanical milling Methods 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14603—Special geometry or disposition of pixel-elements, address-lines or gate-electrodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
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- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Electromagnetism (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Element Separation (AREA)
- Solid State Image Pick-Up Elements (AREA)
Abstract
A kind of imaging sensor and forming method thereof, the method includes：Semiconductor substrate is provided, the semiconductor substrate includes logic region and pixel region arranged side by side, wherein is formed with isolation structure in the front of the semiconductor substrate, the logic region；The logic region is performed etching from the back side of the semiconductor substrate, to form groove, wherein the bottom-exposed of the groove goes out the isolation structure；The filled media layer in the groove.The present invention program helps to reduce leakage current and parasitic capacitance, the generation of latch-up is avoided, to improve device quality.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors more particularly to a kind of imaging sensor and forming method thereof.
Background technology
Imaging sensor is the core component of picture pick-up device, and image taking work(is realized by converting optical signals into electric signal
Energy.By taking cmos image sensor (CMOS Image Sensors, CIS) device as an example, since it is with low-power consumption and high noise
Than the advantages of, therefore be widely applied in various fields.
In a kind of existing manufacturing process of CIS, first logical device, pixel can be formed in the front of semiconductor substrate
Then device and metal interconnection structure are bonded using carrying wafer with the front of the semiconductor substrate, and then to semiconductor
The back of substrate is thinned, and then forms the subsequent technique of CIS at the back side of semiconductor substrate, such as in the pixel device
The semiconductor substrate back side form filter etc..
Wherein, the logical device may include grid, source region and drain region, and isolation is could be formed in the logic region
Structure, the isolation structure is for being isolated the logical device.
However, in existing CIS techniques, the depth of isolation structure is usually shallower, reduces the isolation to logical device
Effect, or even there is carrier to be moved to the drain region of neighbor logic device from source region around the bottom end of isolation structure, cause to generate leakage
Latch-up even occurs when serious for electric current and parasitic capacitance, damages semiconductor devices.
Invention content
The technical problem to be solved by the present invention is to provide a kind of imaging sensor and forming method thereof, help to reduce leakage current
And parasitic capacitance, the generation of latch-up is avoided, to improve device quality.
In order to solve the above technical problems, the embodiment of the present invention provides a kind of forming method of imaging sensor, including：It provides
Semiconductor substrate, the semiconductor substrate include logic region and pixel region arranged side by side, wherein in the semiconductor substrate
Front is formed with isolation structure in the logic region；The logic region is carved from the back side of the semiconductor substrate
Erosion, to form groove, wherein the bottom-exposed of the groove goes out the isolation structure；The filled media layer in the groove.
Optionally, filled media layer includes in the groove：Dielectric material is formed, the dielectric material filling is described recessed
Slot and the pixel region for covering the semiconductor substrate back side；The dielectric material is planarized, to expose the picture
The back side of the semiconductor substrate in plain region.
Optionally, the dielectric material is silica and/or silicon nitride.
Optionally, the logic region is performed etching from the back side of the semiconductor substrate, with before forming groove, institute
The forming method for the imaging sensor stated further includes：The semiconductor substrate is carried out from the back side to be thinned to preset thickness.
Optionally, the logic region is performed etching from the back side of the semiconductor substrate, includes to form groove：
The back side of the semiconductor substrate forms patterned mask layer；Using the patterned mask layer as mask, to the logic
Region performs etching, to form the groove.
Optionally, logical device is formed in the semiconductor substrate of the logic region, the isolation structure is for being isolated
The logical device.
In order to solve the above technical problems, the embodiment of the present invention provides a kind of imaging sensor, including：Semiconductor substrate, institute
State logic region and pixel region that semiconductor substrate includes arranged side by side；Isolation structure is located at the positive of the semiconductor substrate
In the logic region；Groove is located in the logic region at the back side of the semiconductor substrate, wherein the groove
Bottom-exposed goes out the isolation structure；Dielectric layer is filled in the groove.
Optionally, the surface of the dielectric layer is flushed with the back side of the semiconductor substrate of the pixel region.
Optionally, the material of the dielectric layer is silica and/or silicon nitride.
Optionally, logical device is formed in the semiconductor substrate of the logic region, the isolation structure is for being isolated
The logical device.
Compared with prior art, the technical solution of the embodiment of the present invention has the advantages that：
In embodiments of the present invention, semiconductor substrate is provided, the semiconductor substrate includes logic region and picture arranged side by side
Plain region, wherein be formed with isolation structure in the front of the semiconductor substrate, the logic region；From the semiconductor
The back side of substrate performs etching the logic region, to form groove, wherein the bottom-exposed of the groove goes out the isolation
Structure；The filled media layer in the groove.Using the scheme of the embodiment of the present invention, formed by the back side in semiconductor substrate
Groove, and the bottom-exposed of the groove goes out the isolation structure, and the filled media layer in groove, can be to carrier from source
Area is effectively isolated around the access in the drain region that the bottom end of isolation structure is moved to neighbor logic device, is helped to reduce and be leaked
Electric current and parasitic capacitance avoid the generation of latch-up, to improve device quality.
Further, the dielectric material is planarized, to expose the back of the body of the semiconductor substrate of the pixel region
Face can be such that the semiconductor substrate back side of pixel region is not influenced by logic region, restore to thickness in the prior art,
It can continue the parameter using subsequent technique, reduce the influence to subsequent technique.
Description of the drawings
Fig. 1 is a kind of cross-sectional view of imaging sensor in the prior art；
Fig. 2 is a kind of flow chart of the forming method of imaging sensor in the embodiment of the present invention；
Fig. 3 to Fig. 7 is that the corresponding device of each step cuts open in a kind of forming method of imaging sensor in the embodiment of the present invention
Face structural schematic diagram.
Specific implementation mode
In a kind of existing manufacturing process of CIS, first logical device, pixel can be formed in the front of semiconductor substrate
Then device and metal interconnection structure are bonded using carrying wafer with the front of the semiconductor substrate, and then to semiconductor
The back of substrate is thinned, and then forms the subsequent technique of CIS at the back side of semiconductor substrate, such as in the pixel device
The semiconductor substrate back side form filter etc..
Referring to Fig.1, Fig. 1 is a kind of cross-sectional view of imaging sensor in the prior art.Described image sensor
May include semiconductor substrate 100, logical device, metal interconnection structure 150 and carrying wafer (Carrier Wafer) 160.
Wherein, the semiconductor substrate 100 includes logic region A arranged side by side and pixel region B, the semiconductor substrate
100 have front and back.
Specifically, logical device and isolation structure 110 are formed in the semiconductor substrate 100 of the logic region A,
The isolation structure 110 is for being isolated the logical device.Wherein, the logical device may include grid 130, source region 120
With drain region 122.
However in existing CIS techniques, dotted arrow direction as shown in Figure 1, there are carrier from source region 120 around
The case where bottom end of isolation structure 110 is moved to drain region 126 of neighbor logic device is crossed, leakage current and parasitic electricity are easy tod produce
Hold, latch-up even occurs when serious, semiconductor devices is caused to be damaged.
The present inventor passes through the study found that in the prior art, the depth of isolation structure 110 is usually shallower, drop
The low isolation effect to logical device.Specifically, due to semiconductor substrate 100 can be thinned from the back side, semiconductor
The thickness of substrate 100 is often relatively thin (being, for example, 2.5 μm or so), therefore isolation structure 110 is also difficult to unlimitedly deepen, and causes
Finite thickness.
In embodiments of the present invention, semiconductor substrate is provided, the semiconductor substrate includes logic region and picture arranged side by side
Plain region, wherein be formed with isolation structure in the front of the semiconductor substrate, the logic region；From the semiconductor
The back side of substrate performs etching the logic region, to form groove, wherein the bottom-exposed of the groove goes out the isolation
Structure；The filled media layer in the groove.Using the scheme of the embodiment of the present invention, formed by the back side in semiconductor substrate
Groove, and the bottom-exposed of the groove goes out the isolation structure, and the filled media layer in groove, can be to carrier from source
Area is effectively isolated around the access in the drain region that the bottom end of isolation structure is moved to neighbor logic device, is helped to reduce and be leaked
Electric current and parasitic capacitance avoid the generation of latch-up, to improve device quality.
It is understandable to enable above-mentioned purpose, feature and the advantageous effect of the present invention to become apparent, below in conjunction with the accompanying drawings to this
The specific embodiment of invention is described in detail.
With reference to Fig. 2, Fig. 2 is a kind of flow chart of the forming method of imaging sensor in the embodiment of the present invention.Described image
The forming method of sensor may include step S21 to step S23：
Step S21：Semiconductor substrate is provided, the semiconductor substrate includes logic region and pixel region arranged side by side,
In, it is formed with isolation structure in the front of the semiconductor substrate, the logic region；
Step S22：The logic region is performed etching from the back side of the semiconductor substrate, to form groove, wherein
The bottom-exposed of the groove goes out the isolation structure；
Step S23：The filled media layer in the groove.
Above-mentioned each step is illustrated with reference to Fig. 3 to Fig. 7.
Fig. 3 to Fig. 7 is that the corresponding device of each step cuts open in a kind of forming method of imaging sensor in the embodiment of the present invention
Face structural schematic diagram.
With reference to Fig. 3, semiconductor substrate 200 is provided, the semiconductor substrate 200 includes logic region A and pixel arranged side by side
Region, the semiconductor substrate 200 have front and back.
Wherein, logical device and isolation structure 210, institute are formed in the semiconductor substrate 200 of the logic region A
It can be multiple to state logical device, and the isolation structure 210 is for being isolated each logical device.Wherein, as unrestricted
Example, the logical device can be MOS transistor, including grid 230, source region 220 and drain region 222, alternatively, the logic device
Part can also be other type of device appropriate.As a non-limiting example, the isolation structure 210 can be shallow-trench isolation
Structure (STI), alternatively, the isolation structure 210 can also be the isolation structure of other appropriate types.
In specific implementation, the semiconductor substrate 200 can be silicon substrate or the material of the semiconductor substrate 200
Material can also be germanium, SiGe, silicon carbide, GaAs or gallium indium, and the semiconductor substrate 200 can also be insulator surface
Silicon substrate or insulator surface germanium substrate, or growth have epitaxial layer (Epitaxy layer, Epi layer)
Substrate.
Preferably, the semiconductor substrate 200 is the semiconductor substrate being lightly doped, and doping type in subsequent technique
The source region 220 formed in the semiconductor substrate 200 and drain region 222 are opposite.It specifically, can be by the semiconductor substrate
200 carry out ion implanting, realize deep trap doping (Deep WellImplant).If the doping of the source region 220 and drain region 222
The type of ion is N-type, then the Doped ions of the semiconductor substrate 200 are p-type ion, such as including B, Ga or In；Conversely,
If the type of the Doped ions in the source region 220 and drain region 222 is p-type, the Doped ions of the semiconductor substrate 200 are
N-type ion, such as including P, As or Sb.
It should be pointed out that although pixel region B is not showed that in imaging sensor shown in Fig. 3, specific
In implementation, pixel region B can have pixel device and isolation structure, the isolation structure to be used to that multiple pixel devices to be isolated,
The pixel device may include photodiode, transmission grid and floating diffusion region.In embodiments of the present invention, to pixel
The specific device architecture and forming step of region B is not limited.
With reference to Fig. 4, metal interconnection structure 250 is formed in the front of the semiconductor substrate 200, and with carrying wafer
260 are bonded.
It should be pointed out that the treatment process carried out in the front of the semiconductor substrate 200 can be existing image
Any conventional treatment process of sensor, the embodiment of the present invention are not restricted this.
Further, the semiconductor substrate 200 is carried out from the back side being thinned to preset thickness.
Specifically, the preset thickness can be 1 μm to 4 μm.
It is understood that the thickness of the semiconductor substrate 200 cannot be excessively thin, the complexity of reduction process otherwise can be improved
Degree and wafer fragment rate；The thickness of the semiconductor substrate 200 cannot be blocked up, is otherwise difficult to be subsequently formed backside trench
When, realize backside trench connection corresponding with front groove.Preferably, the thickness of the semiconductor substrate 200 is 2.5 μm.
With reference to Fig. 5, the logic region A is performed etching from the back side of the semiconductor substrate 200, to form groove
240, wherein the bottom-exposed of the groove 240 goes out the isolation structure 210.
Specifically, the logic region A is performed etching from the back side of the semiconductor substrate 200, to form groove 240
The step of may include：Patterned mask layer 270 is formed at the back side of the semiconductor substrate 200；With described patterned
Mask layer 270 is mask, is performed etching to the logic region A, to form the groove 240.
More specifically, the front of the semiconductor substrate 200 has alignment mark, in the semiconductor substrate 200
The back side forms patterned mask layer 270, and the pattern of the mask layer 270 is aligned according to the alignment mark.
Wherein, the positive alignment mark (Alignment Mark) of the semiconductor substrate 200 can be multiplexed active region
The alignment mark of (Active Area, AA) layer, pair that can also use other that can be determined at the back side of semiconductor substrate 200
Fiducial mark is remembered.
Further, can be dry etching (DryEtch) to the technique that the logic region A is performed etching.
With reference to Fig. 6, the filled media layer 242 in the groove 240.
Specifically, dielectric material is formed, the dielectric material fills the groove 240 and covers the semiconductor substrate
The pixel region B at 200 back sides.Since 240 bottom-exposed of groove goes out isolation structure 210, the dielectric material of filling be isolated
Structure 210 connects.
Specifically, the dielectric material of the dielectric layer 242 can be silica and/or silicon nitride.
In a kind of specific implementation mode of the embodiment of the present invention, the laminated construction that silica and silicon nitride may be used is made
For dielectric layer 242, for example, SiO2And Si3N4, since the stress of two kinds of materials of silica and silicon nitride is on the contrary, can be to avoid right
Semiconductor substrate 200 forms excessively high stress, influences device performance, and the silicon nitride can be used as subsequent chemical mechanical to throw
Stop-layer (Stop Layer) in light (Chemical Mechanical Polishing, CMP) technique.
In another specific implementation mode of the embodiment of the present invention, silicon oxide or silicon nitride may be used as dielectric layer
242, for example, SiO2Or Si3N4.Wherein, since the stress of silica is less than the stress of silicon nitride.
Preferably, silica may be used can improve device quality as dielectric layer 242 compared to silicon nitride.
Further, the thickness of the dielectric layer 242 can be more than or equal to the depth of groove 240.It is unrestricted as one
Property example, the thickness of the dielectric layer 242 can be 0.7 μm to 5 μm.
It is understood that the thickness of the dielectric layer 242 cannot be excessively thin, it is enough to be otherwise difficult to the filling in groove 240
The dielectric material of thickness causes the buffer action to the logical device in logic region A weaker；The thickness of the dielectric layer 242
Cannot be blocked up, otherwise increase the process time of subsequent planarization technique, and lead to the wasting of resources.
With reference to Fig. 7, the dielectric material is planarized, to expose the semiconductor substrate 200 of the pixel region B
The back side.
Wherein, the technique of the planarization process includes chemical mechanical milling tech.
It is understood that in specific implementation, may be used and compare the etching of semiconductor substrate 200 and dielectric material
High lapping liquid, to during planarization, reduce the damage to semiconductor substrate 200.
It should be pointed out that in another specific implementation mode of the embodiment of the present invention, in next subsequent technique
In, need the backside deposition oxide layer in semiconductor substrate 200, for example, silica.Therefore, when the dielectric material is oxidation
When silicon, the pixel region B can be made to retain a part of silica, to reduce subsequent deposition process in flatening process
Take and silica consumption.
Next, can the back side of the semiconductor substrate 200 formed break-through layer (Through Silicon Via),
The late stage process steps such as aluminum cushion layer (Pad), filter structure (Filter) passivation layer (Passivation Layer).
It should be pointed out that in embodiments of the present invention, after being planarized to the dielectric material, partly being led described
The treatment process that the back side of body substrate 200 carries out can be any conventional treatment process of existing imaging sensor, this hair
Bright embodiment is not restricted this.
In embodiments of the present invention, by forming groove 240, and the groove 200 at the back side of semiconductor substrate 200
Bottom-exposed goes out the isolation structure 210, and the filled media layer 242 in groove 240, can to carrier from source region 220 around
The access in the drain region 226 that the bottom end for crossing isolation structure 210 is moved to neighbor logic device is effectively isolated, and helps to reduce
Leakage current and parasitic capacitance avoid the generation of latch-up, to improve device quality.
In embodiments of the present invention, a kind of imaging sensor is additionally provided, with reference to Fig. 7, described image sensor can wrap
It includes：
Semiconductor substrate 200, the semiconductor substrate 200 include logic region A and pixel region B arranged side by side；
Isolation structure 210 is located in the positive logic region A of the semiconductor substrate 200；
Groove 240 is located in the logic region A at the back side of the semiconductor substrate 200, wherein the groove 240
Bottom-exposed go out the isolation structure 210；
Dielectric layer 242 is filled in the groove 240.
Further, the surface of the dielectric layer 240 can be with the back side of the semiconductor substrate 200 of the pixel region A
It flushes.
The material of the dielectric layer can be silica and/or silicon nitride.
Logical device is formed in the semiconductor substrate 200 of the logic region A, the isolation structure 210 is for being isolated
The logical device.
The thickness of the semiconductor substrate 200 can be preset thickness, described default as a unrestricted example
Thickness can be 1 μm to 4 μm.
The thickness of the dielectric layer 242 can be more than or equal to the depth of groove 240.As a unrestricted example,
The thickness of the dielectric layer 242 can be 0.7 μm to 5 μm.
In addition, CIS may include preceding illuminated (Front-side Illumination, abbreviation FSI) CIS and rear illuminated
(Back-side Illumination, abbreviation BSI) CIS, the rear illuminated CIS are referred to as back-illuminated type CIS.In back-illuminated type
In CIS, light from back side illuminaton to photodiode on generate photo-generated carrier, and then form electric signal.
In embodiments of the present invention, described image sensor can be back-illuminated type CIS.
Although present disclosure is as above, present invention is not limited to this.Any those skilled in the art are not departing from this
It in the spirit and scope of invention, can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
Subject to the range of restriction.
Claims (10)
1. a kind of forming method of imaging sensor, which is characterized in that including：
Semiconductor substrate is provided, the semiconductor substrate includes logic region and pixel region arranged side by side, wherein is partly led described
The front of body substrate is formed with isolation structure in the logic region；
The logic region is performed etching from the back side of the semiconductor substrate, to form groove, wherein the bottom of the groove
Portion exposes the isolation structure；
The filled media layer in the groove.
2. the forming method of imaging sensor according to claim 1, which is characterized in that the filled media in the groove
Layer include：
Dielectric material is formed, the dielectric material fills the groove and covers the pixel region at the semiconductor substrate back side；
The dielectric material is planarized, to expose the back side of the semiconductor substrate of the pixel region.
3. the forming method of imaging sensor according to claim 2, which is characterized in that the dielectric material is silica
And/or silicon nitride.
4. the forming method of imaging sensor according to claim 1, which is characterized in that from the back of the body of the semiconductor substrate
It is performed etching in face of the logic region, before forming groove, to further include：
The semiconductor substrate is carried out from the back side to be thinned to preset thickness.
5. the forming method of imaging sensor according to claim 1, which is characterized in that from the back of the body of the semiconductor substrate
It is performed etching in face of the logic region, includes to form groove：
Patterned mask layer is formed at the back side of the semiconductor substrate；
Using the patterned mask layer as mask, the logic region is performed etching, to form the groove.
6. the forming method of imaging sensor according to claim 1, which is characterized in that the semiconductor of the logic region
Logical device is formed in substrate, the isolation structure is for being isolated the logical device.
7. a kind of imaging sensor, which is characterized in that including：
Semiconductor substrate, the semiconductor substrate include logic region and pixel region arranged side by side；
Isolation structure is located in the positive logic region of the semiconductor substrate；
Groove is located in the logic region at the back side of the semiconductor substrate, wherein the bottom-exposed of the groove goes out institute
State isolation structure；
Dielectric layer is filled in the groove.
8. imaging sensor according to claim 7, which is characterized in that the surface of the dielectric layer and the pixel region
The back side of semiconductor substrate flush.
9. imaging sensor according to claim 7, which is characterized in that the material of the dielectric layer be silica and/or
Silicon nitride.
10. imaging sensor according to claim 7, which is characterized in that shape in the semiconductor substrate of the logic region
At there is logical device, the isolation structure is for being isolated the logical device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810069702.3A CN108281442B (en) | 2018-01-24 | 2018-01-24 | Image sensor and forming method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810069702.3A CN108281442B (en) | 2018-01-24 | 2018-01-24 | Image sensor and forming method thereof |
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| Publication Number | Publication Date |
|---|---|
| CN108281442A true CN108281442A (en) | 2018-07-13 |
| CN108281442B CN108281442B (en) | 2021-01-22 |
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| CN201810069702.3A Active CN108281442B (en) | 2018-01-24 | 2018-01-24 | Image sensor and forming method thereof |
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| CN109348118A (en) * | 2018-12-04 | 2019-02-15 | 德淮半导体有限公司 | Imaging sensor, production method and imaging device |
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| CN104882460A (en) * | 2014-02-27 | 2015-09-02 | 三星电子株式会社 | Image Sensors Having Deep Trenches Including Negative Charge Material And Methods Of Fabricating The Same |
| US20170047373A1 (en) * | 2014-05-04 | 2017-02-16 | Semiconductor Manufacturing International (Shanghai) Corporation | Method for reducing crosstalk in cmos image sensor |
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