CN108281436A - Cmos image sensor and forming method thereof - Google Patents
Cmos image sensor and forming method thereof Download PDFInfo
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- CN108281436A CN108281436A CN201810036256.6A CN201810036256A CN108281436A CN 108281436 A CN108281436 A CN 108281436A CN 201810036256 A CN201810036256 A CN 201810036256A CN 108281436 A CN108281436 A CN 108281436A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/1463—Pixel isolation structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14603—Special geometry or disposition of pixel-elements, address-lines or gate-electrodes
- H01L27/14605—Structural or functional details relating to the position of the pixel elements, e.g. smaller pixel elements in the center of the imager compared to pixel elements at the periphery
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
- H01L27/14687—Wafer level processing
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Abstract
A kind of cmos image sensor and forming method thereof, the method includes：Semiconductor substrate is provided, the semiconductor substrate includes photodiode area, doped region and channel region；Groove is formed in the semiconductor substrate around the photodiode area, the groove extends since the channel region and to the distal end of the photodiode area, and the distal end is the one end of the photodiode area far from the channel region；Spacer medium layer is formed in the groove and extends grid；Ion implanting is carried out to the photodiode area and doped region；Gate dielectric layer and transmission grid are sequentially formed in the semiconductor substrate surface of the channel region, the transmission grid is located at the gate dielectric layer surface, wherein the transmission grid is connect with the extension grid.The present invention program can reduce the charge residue in photodiode area distal end, help to improve device performance.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors more particularly to a kind of cmos image sensor and forming method thereof.
Background technology
Imaging sensor is the semiconductor devices that optical imagery is converted into electric signal, due to cmos image sensor
(CMOS Image Sensor, CIS) has the advantages that low-power consumption and high s/n ratio, therefore has been obtained extensively in various fields
Using.
In the prior art, CIS generally includes photodiode, floating diffusion region and transmission grid, and is reading
When, conducting channel is opened by transmitting grid, by the electric charge transfer of photodiode to floating diffusion region.However due to photoelectricity two
The depth of pole pipe is usually relatively deep, is often difficult to exhaust positioned at the charge of deep place, to which there are charge residues, schemes in output
As when cause image information to malfunction or the problems such as image information is distorted, such as lead to streaking.
If the day for announcing is the utility model patent that June 4, Authorization Notice No. in 2014 are CN203631555U, disclosure
A kind of CIS, the part that grid is transmitted by setting are placed in shallow-trench isolation (Shallow Trench Isolation, STI)
It is interior, shorten transmission grid to the distance of photodiode depths, the charge residue to mitigate in photodiode depths is asked
Topic.
However, in photodiode, however it remains the charge in the region at a distance from transmission grid farther out, the region
The problems such as being difficult to be transferred away, image information error or image information distortion still can occur.
Invention content
The technical problem to be solved by the present invention is to provide a kind of cmos image sensors and forming method thereof, it is possible to reduce in light
The charge residue of photodiode area distal end, helps to improve device performance.
In order to solve the above technical problems, the embodiment of the present invention provides a kind of forming method of cmos image sensor, including：
There is provided semiconductor substrate, the semiconductor substrate include photodiode area, doped region and be located at two pole of the photoelectricity
Channel region between area under control domain and doped region；Ditch is formed in the semiconductor substrate around the photodiode area
Slot, the groove extend since the channel region and to the distal end of the photodiode area, and the distal end is described
The one end of photodiode area far from the channel region；Spacer medium layer is formed in the groove and extends grid,
The spacer medium layer covers the bottom and side wall of the groove, and the extension grid fills the groove and is located at the isolation
On dielectric layer；Ion implanting is carried out to the photodiode area and doped region, in the photodiode area
Interior formation photodiode, floating diffusion region is formed in the doped region；In the semiconductor substrate table of the channel region
Face sequentially forms gate dielectric layer and transmission grid, and the transmission grid is located at the gate dielectric layer surface, wherein the transmission grid
Pole is connect with the extension grid.
Optionally, the groove includes two sections of grooves of separation, respectively since the opposite both sides of the channel region, and
It extends between two sections of grooves of the distal end with interval.
Optionally, the groove is extended to flushes with the distal end, or surrounds a part for the distal end.
Optionally, the transmission grid is to extension other than the channel region, so that the transmission grid and the extension
Grid connects.
Optionally, the upper level for extending grid is higher than the gate dielectric layer, and the part being higher by and the biography
Defeated grid connection.
Optionally, the forming method of the cmos image sensor further includes：Source region and drain region are formed, one of them is located at
Between the photodiode and the transmission grid, another is located between the floating diffusion region and the transmission grid.
In order to solve the above technical problems, the embodiment of the present invention provides a kind of cmos image sensor, including：Semiconductor serves as a contrast
Bottom, the semiconductor substrate include photodiode area, doped region and be located at the photodiode area and doping
Channel region between region is formed with photodiode in the photodiode area, is formed in the doped region
Floating diffusion region；Gate dielectric layer is located at the surface of the semiconductor substrate of the channel region；Grid is transmitted, is located at the grid and is situated between
Matter layer surface；Groove is located in the semiconductor substrate around the photodiode area, and the groove is from the channel region
Start and extend to the distal end of the photodiode area, the distal end is the photodiode area far from the raceway groove
The one end in region；Spacer medium layer covers the bottom and side wall of the groove；Extend grid, fill the groove and is located at institute
It states on spacer medium layer；Wherein, the transmission grid is connect with the extension grid.
Optionally, the groove includes two sections of grooves of separation, respectively since the opposite both sides of the channel region, and
It extends between two sections of grooves of the distal end with interval.
Optionally, the groove is extended to flushes with the distal end, or surrounds a part for the distal end.
Optionally, the transmission grid is connect with described with the extension grid to extension other than the channel region.
Optionally, the upper level for extending grid is higher than the gate dielectric layer, and the part being higher by and the biography
Defeated grid connection.
Compared with prior art, the technical solution of the embodiment of the present invention has the advantages that：
In embodiments of the present invention, groove is formed in the semiconductor substrate around the photodiode area, it is described
Groove extends since the channel region and to the distal end of the photodiode area, and the distal end is two pole of the photoelectricity
The one end of area under control domain far from the channel region；Spacer medium layer is formed in the groove and extends grid；To the light
Photodiode area and doped region carry out ion implanting, to form photodiode in the photodiode area,
Floating diffusion region is formed in the doped region；Gate dielectric layer is sequentially formed in the semiconductor substrate surface of the channel region
With transmission grid, the transmission grid is connect with the extension grid.Using the above scheme, by being arranged in two pole of the photoelectricity
The groove in semiconductor substrate around the domain of area under control, so formed in the trench with the extension grid that connect of transmission grid, can be with
Extend the access areas of transmission grid and photodiode area, and then depletion layer is formed in access areas, so that reading
When taking, the charge of the one end of photodiode area far from transmission grid is easy under the action of transmitting grid voltage, toward transmission
The edge of grid accumulates, and smoothly reads, and to reduce the charge residue in photodiode area distal end, mitigation is contributed to scheme
As information error or the generation of image information problem of dtmf distortion DTMF.Middle transmission grid is only located at channel region compared with the prior art simultaneously
Near, using the scheme of the embodiment of the present invention, since the access areas of transmission grid and photodiode area increases, Ke Yi
The depletion layer is formed in the region of bigger, is helped to be better protected from cross talk of electrons, is improved the device performance of CIS；Further
Ground, compared with the prior art in be initially formed STI separation layers, and then etch the oxide in STI separation layers, the process is more complicated and
It is difficult to control each uniformity to etching, in embodiments of the present invention, by being initially formed groove, redeposited oxide layer is formed suitably
Then the spacer medium layer of thickness forms in spacer medium layer and extends grid, help to reduce process complexity, and improve device
Part performance.
Further, by the way that two sections of grooves that the groove includes separation are arranged, respectively from the channel region it is opposite two
Side starts, and extends between two sections of grooves of the distal end with interval, and the transmission grid and the extension may be implemented
Two sections of grid are separately connected, and to reduce the charge residue in photodiode area distant place to a greater degree, mitigate image
Information malfunctions or the generation of image information problem of dtmf distortion DTMF.
Further, the part for being flushed with the distal end, or surrounding the distal end is extended to by the way that the groove is arranged,
The extension grid can be made to extend to most remote areas, the charge residue in photodiode area distant place is further reduced, subtracts
Light image information error or the generation of image information problem of dtmf distortion DTMF.
Further, by the way that the transmission grid is arranged to extension other than the channel region, with the described and extension grid
Pole connects, and helps, by adjusting the Extendible Extent of transmission grid, to realize that transmission grid is connect with grid is extended.
Further, it is higher than the gate dielectric layer, and the part being higher by by the way that the upper level for extending grid is arranged
It is connect with the transmission grid, helps, by adjusting the height of grid is extended, to realize that transmission grid is connect with grid is extended.
Description of the drawings
Fig. 1 is a kind of vertical view of cmos image sensor in the prior art；
Fig. 2 is cross-sectional views of the Fig. 1 along cutting line A1-A2；
Fig. 3 is the vertical view of another cmos image sensor in the prior art；
Fig. 4 is cross-sectional views of the Fig. 3 along cutting line B1-B2；
Fig. 5 is a kind of flow chart of the forming method of cmos image sensor in the embodiment of the present invention；
Fig. 6 to Figure 19 is each step respective devices in a kind of forming method of cmos image sensor in the embodiment of the present invention
Structural schematic diagram；
Figure 20 is vertical view of the cmos image sensor under no applied voltage state in the embodiment of the present invention；
Figure 21 is charge movement schematic diagram of the cmos image sensor under reading state in the embodiment of the present invention.
Specific implementation mode
In the prior art, cmos image sensor generally includes photodiode, floating diffusion region and transmission grid,
And conducting channel at the time of reading, is opened by transmitting grid, by the electric charge transfer of photodiode to floating diffusion region.However
It is easy there are charge residue, causes image information to malfunction or the problems such as image information distortion when export image, such as cause
Streaking.
In conjunction with referring to Fig.1 and Fig. 2, Fig. 1 are that a kind of vertical view of cmos image sensor, Fig. 2 are Fig. 1 in the prior art
Along the cross-sectional view of cutting line A1-A2.
The cmos image sensor may include：Semiconductor substrate 100, gate dielectric layer 132, transmission grid 130 and
Shallow-trench isolation 110.
Wherein, the semiconductor substrate 100 includes photodiode 121 and floating diffusion region 125.
Semiconductor substrate of the gate dielectric layer 132 between the photodiode 121 and floating diffusion region 125
100 surface；The transmission grid 130 is located at the surface of the gate dielectric layer 132.
The shallow-trench isolation 110 is located in the semiconductor substrate around the photodiode 121.
Further, due to the depth of photodiode 121 usually compared with depth and area occupied it is larger, Distance Transmission grid
130 farther out the charge of position (such as at M) and the charge apart from deep place (such as at N) be often difficult to exhaust, to deposit
The problems such as having charge residue, image information error or image information is caused to be distorted when exporting image, such as image is caused to drag
Tail.
In conjunction with the vertical view for reference to Fig. 3 and Fig. 4, Fig. 3 being another cmos image sensor in the prior art, Fig. 4 is
Cross-sectional views of the Fig. 3 along cutting line B1-B2.
Described another kind cmos image sensor and Fig. 1 extremely Fig. 2 shows the different place of cmos image sensor be：
It transmits grid 134 to the direction of shallow-trench isolation 110 to extend, and a part is placed in shallow-trench isolation 110.
It will be appreciated by persons skilled in the art that gate dielectric layer 132 also can be with transmission grid 134 to shallow-trench isolation
110 direction extends, to keep transmission grid 134 to be located at the surface of the gate dielectric layer 132.
In another cmos image sensor, the part that grid 134 is transmitted by setting is placed in shallow-trench isolation
In 110, transmission grid 134 can be shortened to the distance of 121 depths of photodiode, to which mitigation is deep in photodiode 121
The problem of charge residue at place, wherein the charge of 121 depths of the photodiode for example can be positioned at Fig. 2 shows N at
Charge.
The present inventor by the study found that positioned at Fig. 2 shows M at charge, be far from transmission grid
134, therefore still have and be difficult to be transmitted the problem of grid 134 is transferred out, leads to charge residue, and then when exporting image
The problems such as still causing image information error or image information to be distorted, reduce equipment performance.
In embodiments of the present invention, semiconductor substrate is provided, the semiconductor substrate includes photodiode area, doping
Region and the channel region between the photodiode area and doped region；In photodiode area week
Form groove in the semiconductor substrate enclosed, the groove is since the channel region and to the remote of the photodiode area
End extends, and the distal end is the one end of the photodiode area far from the channel region；In the groove formed every
From dielectric layer and extend grid, the spacer medium layer covers the bottom and side wall of the groove, the extension grid filling
The groove is simultaneously located on the spacer medium layer；Ion implanting is carried out to the photodiode area and doped region,
To form photodiode in the photodiode area, floating diffusion region is formed in the doped region；Described
The semiconductor substrate surface of channel region sequentially forms gate dielectric layer and transmission grid, and the transmission grid is located at the gate medium
Layer surface, wherein the transmission grid is connect with the extension grid.
Using the above scheme, by the groove being arranged in the semiconductor substrate around the photodiode area, into
And formed in the trench with the extension grid that connect of transmission grid, approaching for transmission grid and photodiode area can be extended
Region, and then depletion layer is formed in access areas, so that at the time of reading, the one of the separate transmission grid of photodiode area
The charge at end is easy under the action of transmitting grid voltage, toward the edge accumulation of transmission grid, and is smoothly read, to reduce
The charge residue of photodiode area distal end helps to mitigate image information error or the generation of image information problem of dtmf distortion DTMF；
Middle transmission grid is only located near channel region compared with the prior art simultaneously, using the scheme of the embodiment of the present invention, due to passing
The access areas of defeated grid and photodiode area increases, and can form the depletion layer in the region of bigger, contribute to
It is better protected from cross talk of electrons, improves the device performance of CIS；Further, compared with the prior art in be initially formed STI isolation
Layer, and then the oxide in STI separation layers is etched, the process is more complicated and is difficult to control each uniformity to etching, in this hair
In bright embodiment, by being initially formed groove, redeposited oxide layer forms the spacer medium layer of suitable thickness, then in spacer medium
It is formed in layer and extends grid, help to reduce process complexity, and improve device performance.
It is understandable to enable above-mentioned purpose, feature and the advantageous effect of the present invention to become apparent, below in conjunction with the accompanying drawings to this
The specific embodiment of invention is described in detail.
With reference to Fig. 5, Fig. 5 is a kind of flow chart of the forming method of cmos image sensor in the embodiment of the present invention.It is described
The forming method of cmos image sensor may include step S51 to step S55：
Step S51：There is provided semiconductor substrate, the semiconductor substrate include photodiode area, doped region and
Channel region between the photodiode area and doped region；
Step S52：Groove is formed in the semiconductor substrate around the photodiode area, the groove is described in
Channel region starts and extends to the distal end of the photodiode area, and the distal end is that the photodiode area is separate
One end of the channel region；
Step S53：Spacer medium layer is formed in the groove and extends grid, described in the spacer medium layer covering
The bottom and side wall of groove, the extension grid fill the groove and on the spacer medium layers；
Step S54：Ion implanting is carried out to the photodiode area and doped region, in two pole of the photoelectricity
Photodiode is formed in the domain of area under control, and floating diffusion region is formed in the doped region；
Step S55：Gate dielectric layer and transmission grid are sequentially formed in the semiconductor substrate surface of the channel region, it is described
Transmission grid is located at the gate dielectric layer surface, wherein the transmission grid is connect with the extension grid.
Above-mentioned each step is illustrated with reference to Fig. 6 to Figure 19.
Fig. 6 to Figure 19 is each step respective devices in a kind of forming method of cmos image sensor in the embodiment of the present invention
Structural schematic diagram.
In conjunction with reference to Fig. 6 and Fig. 7, Fig. 6 is vertical view, and Fig. 7 is cross-sectional views of the Fig. 6 along cutting line C1-C2.
Semiconductor substrate 200 is provided, forms groove 211 in the semiconductor substrate 200.
Wherein, the semiconductor substrate include photodiode area 220, doped region 224 and be located at the photoelectricity
Channel region 222 between diode area 220 and doped region 224.
Groove 211 is formed in semiconductor substrate 200 around the photodiode area 220, the groove 211 is certainly
The channel region 222 starts and extends to the distal end of the photodiode area 220, and the distal end is two pole of the photoelectricity
The one end of area under control domain 220 far from the channel region 222.
In specific implementation, the semiconductor substrate 200 can be silicon substrate or the material of the semiconductor substrate 200
Material can also be germanium, SiGe, silicon carbide, GaAs or gallium indium, and the semiconductor substrate 200 can also be insulator surface
Silicon substrate or insulator surface germanium substrate, or growth have epitaxial layer (Epitaxy layer, Epi layer)
Substrate.
Preferably, the semiconductor substrate 200 is the semiconductor substrate being lightly doped, and doping type is opposite with drain region.Tool
Body, it can realize deep trap doping (Deep Well Implant) by carrying out ion implanting to the semiconductor substrate 200.
Specifically, the implant energy of the semiconductor substrate 200 could be provided as 30keV to 110keV；The semiconductor
The dopant dose of substrate 200 could be provided as 2E15atom/cm3To 1E17atom/cm3。
More specifically, the type of the Doped ions of the photodiode area 220 and doped region 224 with it is described
The doping type of semiconductor substrate 200 is opposite.If the doping of the photodiode area 220 and doped region 224 from
The type of son is N-type, then the Doped ions of the semiconductor substrate 200 are p-type ion, such as including B, Ga or In；Conversely, such as
The type of the Doped ions of photodiode area 220 and doped region 224 described in fruit is p-type, then the semiconductor substrate
100 Doped ions are N-type ion, such as including P, As or Sb.
Further, by etching technics, can in the semiconductor substrate 200 around photodiode area 220 shape
At groove 211.
Specifically, can the surface of semiconductor substrate 200 formed patterned photoresist layer (Photo Resist,
PR), and then using the patterned photoresist layer as mask, etching forms the groove 211.
Preferably, the groove 211 can be formed in the part etching of preset sti region according to the domain of STI.
Preferably, the width of the groove 211 could be provided as 50nm to 100nm.
Preferably, the depth of the groove 211 could be provided as 10nm to 100nm.
Further, the groove 211 may include two sections of grooves of separation, opposite from the channel region 222 respectively
Both sides start, and extend to there is between two sections of grooves of the distal end interval.
In embodiments of the present invention, by the way that two sections of grooves that the groove 211 includes separation are arranged, respectively from the raceway groove
The opposite both sides in region start, and extend to and have interval between two sections of grooves of the distal end, may be implemented transmission grid with
Extend grid two sections are separately connected, can be with bigger journey compared to the extension grid only connected in the unilateral setting of transmission grid
Degree ground reduces the charge residue in photodiode area distant place, mitigates the hair of image information error or image information problem of dtmf distortion DTMF
It is raw.
In the embodiment of the present invention shown in Fig. 6 in a kind of vertical view of cmos image sensor, groove 211 surrounds described
A part for distal end.
In the embodiment of the present invention illustrated in figure 8 in the vertical view of another cmos image sensor, groove 212 is to described
The distal end of photodiode area 220 extends, but is not extended to distal end.
In the embodiment of the present invention shown in Fig. 9 in the vertical view of another cmos image sensor, groove 213 extends to
It is flushed with the distal end.
It is understood that groove extends remoter, more contribute to reduce to a greater degree remote in photodiode area
The charge residue at place mitigates image information error or the generation of image information problem of dtmf distortion DTMF, however forms the cost for extending grid
Also higher.In specific implementation, any one cmos image sensor shown in Fig. 6 to Fig. 9 can be selected as the case may be.
In embodiments of the present invention, it is extended to by setting groove and is flushed with the distal end, or surround the distal end
A part can make the extension grid extend to most remote areas, be further reduced the electricity in 220 distant place of photodiode area
Lotus remains, and mitigates image information error or the generation of image information problem of dtmf distortion DTMF.
In conjunction with referring to Fig.1 0 to Figure 11, Figure 10 is vertical view, and Figure 11 is that Figure 10 illustrates along the cross-section structure of cutting line C1-C2
Figure.Spacer medium layer 210 is formed in the groove 211 (with reference to Fig. 6) and extends grid 236, the spacer medium layer 210
The bottom and side wall of the groove 211 is covered, the extension grid 236 fills the groove 211 and is located at the spacer medium
On layer 210.
Further, the thickness of the spacer medium layer 210 can account for the 1% to 15% of 211 depth of the groove, to
Ensure that there is sufficient space to accommodate and extend grid 236 for groove 211.
Further, the spacer medium layer 210 can be dielectric, for example, silica, silicon nitride or without fixed
Shape carbon (Amorphous Carbon).
Further, may include the step of formation spacer medium layer 210 in the groove 211：Using live water
Vapour generates (In-situ Steam Generation, ISSG) technique and forms the spacer medium layer 210.The ISSG techniques quilt
It is considered as a kind of low pressure and quickly aoxidizes thermal annealing technology, oxidation life is compensated while the film to deposit carries out thermal annealing
It is long, contribute to form consistency higher, spacer medium layer 210 evenly.
The extension grid 236 can be polysilicon gate, such as may include being sequentially formed at the spacer medium layer 210
The polysilicon layer and cap layer on surface；The extension grid 236 can be with metal gates, for example, high-dielectric coefficient metal gates
(High-k metal gate, HKMG)；The extension grid 236 can also be that grid are lightly doped in N-type heavy doping grid or N-type
Pole.It should be pointed out that in embodiments of the present invention, the concrete mode for forming extension grid 236 is not restricted.
Preferably, the extension grid 236 can be doping (Insitu-doping) polysilicon in situ, in situ to adulterate work
Skill makes the doping of Uniform polycrystalline silicon for being passed through the gas containing impurity while depositing polysilicon.Compared to other doping
Method needs once to inject in deposition of intrinsic polysilicon and then progress or diffusion technique can using the technique adulterated in situ
To improve production efficiency and cost-effective.
As previously mentioned, the groove can be formed in the part etching of preset sti region according to the domain of STI
211.It is preferred that the spacer medium layer 210 and extension grid 236 can be located in the shallow trench isolation areas.
Referring to Fig.1 2, ion implanting is carried out to the photodiode area 220 and doped region 224, with described
Photodiode 221 is formed in photodiode area 220, and floating diffusion region 225 is formed in the doped region 224.
Specifically, when the type of the photodiode area 220 and the Doped ions of doped region 224 is N-type,
It could be provided as including P, As or Sb；When the type of the photodiode area 220 and the Doped ions of doped region 224
For p-type when, could be provided as including B, Ga or In.
Preferably, the Doped ions of the photodiode area 220 can be boron ion (P) or arsenic ion (As), institute
The Doped ions for stating doped region 224 can be boron ion or arsenic ion.
Preferably, the implant energy that the photodiode area 220 can be arranged is 250keV to 4500keV；Setting
The dopant dose of the photodiode area is 1E17atom/cm3To 5E19atom/cm3。
The implant energy that the doped region 224 can be arranged is 5keV to 30keV；The doped region 224 is set
Implant angle is 7 degree；The dopant dose that the doped region 224 is arranged is 5E19atom/cm3To 5E21atom/cm3。
Figure 13 to Figure 15 shows that 200 surface of semiconductor substrate in the channel region 222 sequentially forms gate medium
A kind of specific implementation mode of layer and transmission grid.
In conjunction with referring to Fig.1 3 to Figure 15, Figure 13 is vertical view, and Figure 14 is that Figure 13 illustrates along the cross-section structure of cutting line C1-C2
Figure, Figure 15 is cross-sectional views of the Figure 13 along cutting line D1-D2.In 200 table of semiconductor substrate of the channel region 222
Face sequentially forms gate dielectric layer 232 and transmission grid 230, and the transmission grid 230 is located at 232 surface of the gate dielectric layer,
In, the transmission grid 230 is connect with the extension grid 236.
Specifically, the upper level for extending grid 236 can be set and be higher than the gate dielectric layer 232, and be higher by
Part connect with the transmission grid 230.
With the continuous reduction of high density integrated circuit characteristic size, the thickness of gate dielectric layer also decreases, such as
In technique or more advanced technique that critical feature size is 65nm, the thickness of gate dielectric layer can be 5nm or less.Therefore,
The mode that conventional formation grid may be used keeps the upper surface for the extension grid 236 to be formed high by increasing the thickness of grid
Degree is higher than the gate dielectric layer 232.
In embodiments of the present invention, it is higher than the gate dielectric layer by the way that the upper level for extending grid 236 is arranged
232, and the part being higher by is connect with the transmission grid 230, helps, by adjusting the height of grid 236 is extended, to realize and pass
Defeated grid 230 is connect with grid 236 is extended.
Further, when the material of the transmission grid 230 is polysilicon, the transmission grid 230 can be carried out
The type of doping, the Doped ions of the transmission grid 230 can be with the photodiode 221 and floating diffusion region 225
Doped ions type it is consistent.
Figure 16 to Figure 18 shows that 200 surface of semiconductor substrate in the channel region 222 sequentially forms gate medium
Another specific implementation mode of layer and transmission grid.
In conjunction with referring to Fig.1 6 to Figure 18, Figure 16 is vertical view, and Figure 17 is that Figure 16 illustrates along the cross-section structure of cutting line C1-C2
Figure, Figure 18 is cross-sectional views of the Figure 16 along cutting line D1-D2.In 200 table of semiconductor substrate of the channel region 222
Face sequentially forms gate dielectric layer 232 and transmission grid 234, and the transmission grid 234 is located at 232 surface of the gate dielectric layer,
In, the transmission grid 234 is connect with the extension grid 236.
Specifically, the transmission grid 234 can be set to extension other than the channel region 222, so that the transmission
Grid 234 is connect with the extension grid 236.
In embodiments of the present invention, extended in addition to the channel region 222 by the way that the transmission grid 234 is arranged, with
It is described to be connect with the extension grid 236, help, by adjusting the Extendible Extent of transmission grid 234, to realize transmission grid 234
It is connect with grid 236 is extended.
Further, the transmission grid 230 (234) can be polysilicon gate, such as may include being sequentially formed at institute
State the polysilicon layer and cap layer on 232 surface of gate dielectric；The transmission grid 230 (234) can be with metal gates, for example,
High-dielectric coefficient metal gates；The transmission grid 230 (234) can also be fin formula field effect transistor (Fin Field
Effect Transistor, FinFET) in covering protrude from semiconductor substrate surface fin top and side wall grid；
The transmission grid 230 (234) can also be that grid is lightly doped in N-type heavy doping grid or N-type.It should be pointed out that at this
In inventive embodiments, the concrete mode for forming 230 (234) is not restricted.
When the material of the transmission grid 234 is polysilicon, the transmission grid 234 can be doped, it is described
The type for transmitting the Doped ions of grid 234 can be with the photodiode 221 and the Doped ions of floating diffusion region 225
Type it is consistent.
Referring to Fig.1 9, on the basis of the cmos image sensor shown in Figure 14, form source region and drain region 240, the source
One of area and drain region 240 are located between the photodiode 221 and the transmission grid 230, another is located at institute
It states between floating diffusion region 225 and the transmission grid 230.
In specific implementation, the type of the Doped ions in the source region and drain region 240 can be with the photodiode 221
And the type of the Doped ions of floating diffusion region 225 is consistent
Preferably, the Doped ions in the source region and drain region 240 can be boron ion or arsenic ion.
Preferably, the implant energy in the source region and drain region 240 can be 1keV to 30keV；The source region and drain region 240
Dopant dose can be 5E18atom/cm3To 1E20atom/cm3。
In specific implementation, it is formed after transmission grid 230 (234), is formed before the source region and drain region 240, may be used also
To include being formed that ion implanting drain region (Lightly Doped Drain, LDD) and formation offset side wall (Spacer) is lightly doped
The step of.
Wherein, the implant angle of the LDD could be provided as 30 degree to 60 degree.
In conjunction with reference to Figure 20 and Figure 21, Figure 20 is cmos image sensor in the embodiment of the present invention in no applied voltage shape
Vertical view under state, Figure 21 are charge movement signal of the cmos image sensor under reading state in the embodiment of the present invention
Figure.
Specifically, in the case of no applied voltage, due to there is the extension grid 236 for surrounding photodiode 221, meeting
Close to the region for extending grid 236 in photodiode 221, depletion layer 242 (also known as inversion layer 242), the consumption are formed
Layer 242 can be effectively prevented cross talk of electrons to the greatest extent.
Further, in the state of applying voltage, the depletion layer 242 at 221 edge of photodiode disappears, and forms electronics
Channel is read, is finally read from transmission grid 230.Specifically, using the type of the Doped ions of photodiode 221 as N-type
For, under reading state, positive voltage can be applied on transmission grid 230, then extend the also positively charged pressure of grid 236, cause to consume
Layer 242, which is thinned, to the greatest extent even disappears, and the negative electrical charge of 221 depths of photodiode is past to extend 236 side of grid under the action of positive voltage
Edge accumulates, and then is smoothly read from transmission grid 230.
In embodiments of the present invention, by the way that partly leading around the photodiode area 220 (referring to Fig.1 9) is arranged
Groove 211 (with reference to Fig. 6) in body substrate 200, and then the extension grid being connect with transmission grid 230 is formed in groove 211
236, the access areas of transmission grid 230 and photodiode area 220 can be extended, and then depletion layer is formed in access areas
242, so that at the time of reading, the charge of the one end of photodiode area 220 far from transmission grid 230 is easy in transmission grid
Under the action of 230 voltage of pole, toward the edge accumulation of transmission grid 230, and smoothly read, to reduce in photodiode area
The charge residue of 220 distal ends helps to mitigate image information error or the generation of image information problem of dtmf distortion DTMF；Simultaneously compared to existing
There is transmission grid in technology to be only located near channel region, using the scheme of the embodiment of the present invention, due to transmission grid 230 and light
The access areas of photodiode area 220 increases, and the depletion layer 242 can be formed in the region of bigger, contributes to more preferable
Ground prevents cross talk of electrons, improves the device performance of cmos image sensor；Further, compared with the prior art in be initially formed
STI separation layers, and then the oxide in STI separation layers is etched, the process is more complicated and is difficult to control each uniformity to etching,
In embodiments of the present invention, by being initially formed groove 211, redeposited oxide layer forms the spacer medium layer 210 of suitable thickness, so
It is formed in spacer medium layer 210 afterwards and extends grid 236, help to reduce process complexity, and improve device performance.
Next, it is possible to implement conventional semiconductor devices back end fabrication, including：The shape of multiple interconnecting metal layers
It is completed at, generally use dual damascene process；The formation of metal pad, for implementing wire bonding when device encapsulation.
In embodiments of the present invention, a kind of semiconductor devices is additionally provided, in conjunction with referring to Fig.1 3 to Figure 15, the CMOS schemes
As sensor may include：
Semiconductor substrate 200, the semiconductor substrate 200 include photodiode area 220, doped region 224 and
Channel region 222 between the photodiode area 220 and doped region 224, the photodiode area 220
It is inside formed with photodiode 221, floating diffusion region 225 is formed in the doped region 224；
Gate dielectric layer 232 is located at the surface of the semiconductor substrate 200 of the channel region 222；
Grid 230 is transmitted, 232 surface of the gate dielectric layer is located at；
Groove 211 (with reference to Fig. 6), is located in the semiconductor substrate 200 around the photodiode area 220, described
Groove 211 extends since the channel region 222 and to the distal end of the photodiode area 220, and the distal end is institute
State the one end of photodiode area 220 far from the channel region 222；
Spacer medium layer 210 covers the bottom and side wall of the groove 211；
Extend grid 236, fills the groove 211 and on the spacer medium layer 210；
Wherein, the transmission grid 230 is connect with the extension grid 236.
Further, the groove 211 may include two sections of grooves of separation, opposite from the channel region 222 respectively
Both sides start, and extend to there is between two sections of grooves of the distal end interval.
Further, the groove 211 can be extended to flushes with the distal end, or surrounds one of the distal end
Point.
Further, the transmission grid 234 (referring to Fig.1 8) can be to extension other than the channel region 222, with institute
It states and is connect with the extension grid 236.
Further, the upper level for extending grid 236 can be higher than the gate dielectric layer, and the part being higher by
It is connect with the transmission grid 230.
In embodiments of the present invention, the cmos image sensor may include preceding illuminated (Front-side
Illumination, abbreviation FSI) cmos image sensor and rear illuminated (Back-side Illumination, abbreviation BSI)
Cmos image sensor.Wherein, rear illuminated cmos image sensor is referred to as back-illuminated cmos image sensors.
It is please referred to above and shown in Fig. 5 to Figure 19 about the principle of the imaging sensor, specific implementation and advantageous effect
The associated description of forming method about imaging sensor, details are not described herein again.
Although present disclosure is as above, present invention is not limited to this.Any those skilled in the art are not departing from this
It in the spirit and scope of invention, can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
Subject to the range of restriction.
Claims (11)
1. a kind of forming method of cmos image sensor, which is characterized in that including：
There is provided semiconductor substrate, the semiconductor substrate include photodiode area, doped region and be located at the photoelectricity
Channel region between diode area and doped region；
Groove is formed in the semiconductor substrate around the photodiode area, the groove is since the channel region
And extend to the distal end of the photodiode area, the distal end is the photodiode area far from the channel region
One end；
In the groove formed spacer medium layer and extend grid, the spacer medium layer cover the groove bottom and
Side wall, the extension grid fill the groove and on the spacer medium layers；
Ion implanting is carried out to the photodiode area and doped region, to be formed in the photodiode area
Photodiode forms floating diffusion region in the doped region；
Gate dielectric layer and transmission grid are sequentially formed in the semiconductor substrate surface of the channel region, the transmission grid is located at
The gate dielectric layer surface, wherein the transmission grid is connect with the extension grid.
2. the forming method of cmos image sensor according to claim 1, which is characterized in that the groove includes separation
Two sections of grooves, respectively since the opposite both sides of the channel region, and extend between two sections of grooves of the distal end and have
There is interval.
3. the forming method of cmos image sensor according to claim 1, which is characterized in that the groove extend to
The distal end flushes, or surrounds a part for the distal end.
4. the forming method of cmos image sensor according to claim 1, which is characterized in that the transmission grid is to institute
It states and extends other than channel region, so that the transmission grid is connect with the extension grid.
5. the forming method of cmos image sensor according to claim 1, which is characterized in that described to extend the upper of grid
Apparent height is higher than the gate dielectric layer, and the part being higher by is connect with the transmission grid.
6. the forming method of cmos image sensor according to claim 1, which is characterized in that further include：
Source region and drain region are formed, one of them is located between the photodiode and the transmission grid, another is located at institute
It states between floating diffusion region and the transmission grid.
7. a kind of cmos image sensor, which is characterized in that including：
Semiconductor substrate, the semiconductor substrate include photodiode area, doped region and be located at two pole of the photoelectricity
Channel region between area under control domain and doped region is formed with photodiode, the doping in the photodiode area
Floating diffusion region is formed in region；
Gate dielectric layer is located at the surface of the semiconductor substrate of the channel region；
Grid is transmitted, the gate dielectric layer surface is located at；
Groove is located in the semiconductor substrate around the photodiode area, and the groove is since the channel region
And extend to the distal end of the photodiode area, the distal end is the photodiode area far from the channel region
One end；
Spacer medium layer covers the bottom and side wall of the groove；
Extend grid, fills the groove and on the spacer medium layer；
Wherein, the transmission grid is connect with the extension grid.
8. cmos image sensor according to claim 7, which is characterized in that
The groove includes two sections of grooves of separation, respectively since the opposite both sides of the channel region, and is extended to described
There is interval between two sections of grooves of distal end.
9. cmos image sensor according to claim 7, which is characterized in that the groove extends to neat with the distal end
It is flat, or surround a part for the distal end.
10. cmos image sensor according to claim 7, which is characterized in that the transmission grid is to the channel region
Extend other than domain, is connect with the extension grid with described.
11. cmos image sensor according to claim 7, which is characterized in that the upper level for extending grid
Higher than the gate dielectric layer, and the part being higher by is connect with the transmission grid.
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Application publication date: 20180713 |